Blackfin arch: Fix CCLK and SCLK checks

Fix CCLK and SCLK checks, combine all arch checks into one file
for maintance. Checkins that remove more lines than they add are always
good.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S
index 04194dca0151..39fbc2861107 100644
--- a/arch/blackfin/mach-common/dpmc.S
+++ b/arch/blackfin/mach-common/dpmc.S
@@ -300,7 +300,7 @@ ENTRY(_sleep_deeper)
         P0.H = hi(PLL_CTL);
         P0.L = lo(PLL_CTL);
         R5 = W[P0](z);
-        R0.L = (MIN_VC/CONFIG_CLKIN_HZ) << 9;
+        R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
         W[P0] = R0.l;
 
         SSYNC;