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author | Ingo Molnar <mingo@elte.hu> | 2009-02-11 04:17:42 -0500 |
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committer | Ingo Molnar <mingo@elte.hu> | 2009-02-11 04:17:42 -0500 |
commit | f437e8b53eab92a5829e65781e29aed23d8ffd0c (patch) | |
tree | 48982c8818a4ac5cddb84ca6a1d55620eb9680ee /arch/blackfin/mach-common/clocks-init.c | |
parent | 140573d33b703194b7e1893711e78b7f546cca7c (diff) | |
parent | 8e4921515c1a379539607eb443d51c30f4f7f338 (diff) |
Merge commit 'v2.6.29-rc4' into sched/core
Diffstat (limited to 'arch/blackfin/mach-common/clocks-init.c')
-rw-r--r-- | arch/blackfin/mach-common/clocks-init.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c index 5d182abefc7b..9dddb6f8cc85 100644 --- a/arch/blackfin/mach-common/clocks-init.c +++ b/arch/blackfin/mach-common/clocks-init.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <asm/clocks.h> | 14 | #include <asm/clocks.h> |
15 | #include <asm/mem_init.h> | 15 | #include <asm/mem_init.h> |
16 | 16 | ||
17 | #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ | ||
17 | #define PLL_CTL_VAL \ | 18 | #define PLL_CTL_VAL \ |
18 | (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ | 19 | (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ |
19 | (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0)) | 20 | (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0)) |
@@ -76,7 +77,7 @@ void init_clocks(void) | |||
76 | bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); | 77 | bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); |
77 | #ifdef EBIU_SDGCTL | 78 | #ifdef EBIU_SDGCTL |
78 | bfin_write_EBIU_SDRRC(mem_SDRRC); | 79 | bfin_write_EBIU_SDRRC(mem_SDRRC); |
79 | bfin_write_EBIU_SDGCTL(mem_SDGCTL); | 80 | bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL); |
80 | #else | 81 | #else |
81 | bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); | 82 | bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); |
82 | do_sync(); | 83 | do_sync(); |