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authorMichael Hennerich <michael.hennerich@analog.com>2009-01-07 10:14:39 -0500
committerBryan Wu <cooloney@kernel.org>2009-01-07 10:14:39 -0500
commit73feb5c09dcf0d64beb67aa5e1f79e11a388e0ff (patch)
tree09fa1f153a2ca810ad72978736f85359205d64a3 /arch/blackfin/mach-common/clocks-init.c
parentc97618d3b7b8ef86a966c4b67b54e5ca15814905 (diff)
Blackfin arch: fix bugs and unify BFIN_KERNEL_CLOCK option
- remove duplicated code and headers - add option allowing arbitrary SDRAM/DDR Timing parameters. - mark automatically calculated timings as EXPERIMENTAL - fix comment header block Related to BUGs: - kernel boot up fails with CONFIG_BFIN_KERNEL_CLOCK item on. - kernel does not boot if re-program clocks [ Mike Frysinger <vapier.adi@gmail.com> - fix comment header - mark do_sync static - document the DMA shutdown - simplify SIC_IWR handling - fix ANOMALY_05000265 handling to work as intended ] Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-common/clocks-init.c')
-rw-r--r--arch/blackfin/mach-common/clocks-init.c93
1 files changed, 93 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
new file mode 100644
index 000000000000..39a94b3a2ed7
--- /dev/null
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -0,0 +1,93 @@
1/*
2 * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory
3 *
4 * Copyright 2004-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/linkage.h>
10#include <linux/init.h>
11#include <asm/blackfin.h>
12
13#include <asm/dma.h>
14#include <asm/clocks.h>
15#include <asm/mem_init.h>
16
17#define PLL_CTL_VAL \
18 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
19 (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0))
20
21__attribute__((l1_text))
22static void do_sync(void)
23{
24 __builtin_bfin_ssync();
25}
26
27__attribute__((l1_text))
28void init_clocks(void)
29{
30 /* Kill any active DMAs as they may trigger external memory accesses
31 * in the middle of reprogramming things, and that'll screw us up.
32 * For example, any automatic DMAs left by U-Boot for splash screens.
33 */
34 size_t i;
35 for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; ++i) {
36 struct dma_register *dma = dma_io_base_addr[i];
37 dma->cfg = 0;
38 }
39
40 do_sync();
41
42#ifdef SIC_IWR0
43 bfin_write_SIC_IWR0(IWR_ENABLE(0));
44# ifdef SIC_IWR1
45 /* BF52x system reset does not properly reset SIC_IWR1 which
46 * will screw up the bootrom as it relies on MDMA0/1 waking it
47 * up from IDLE instructions. See this report for more info:
48 * http://blackfin.uclinux.org/gf/tracker/4323
49 */
50 if (ANOMALY_05000435)
51 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
52 else
53 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
54# endif
55# ifdef SIC_IWR2
56 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
57# endif
58#else
59 bfin_write_SIC_IWR(IWR_ENABLE(0));
60#endif
61 do_sync();
62#ifdef EBIU_SDGCTL
63 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
64 do_sync();
65#endif
66
67#ifdef CLKBUFOE
68 bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
69 do_sync();
70 __asm__ __volatile__("IDLE;");
71#endif
72 bfin_write_PLL_LOCKCNT(0x300);
73 do_sync();
74 bfin_write16(PLL_CTL, PLL_CTL_VAL);
75 __asm__ __volatile__("IDLE;");
76 bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
77#ifdef EBIU_SDGCTL
78 bfin_write_EBIU_SDRRC(mem_SDRRC);
79 bfin_write_EBIU_SDGCTL(mem_SDGCTL);
80#else
81 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
82 do_sync();
83 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
84 bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
85 bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
86 bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
87#ifdef CONFIG_MEM_EBIU_DDRQUE
88 bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
89#endif
90#endif
91 do_sync();
92 bfin_read16(0);
93}