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authorMichael Hennerich <michael.hennerich@analog.com>2009-02-04 03:49:45 -0500
committerBryan Wu <cooloney@kernel.org>2009-02-04 03:49:45 -0500
commit331693129d1764e38b15561e5712347fd591b2a9 (patch)
tree7114d0bd0f8149f0e5ed041a91942a4d712e2d27 /arch/blackfin/mach-common/clocks-init.c
parent41245ac5952e5b05e6fbb7c188eae0947f640189 (diff)
Blackfin arch: Fix Bug - Kernel does not boot if re-program clocks
On BF561 EBIU_SDGCTL bit 31 controls the SDRAM external data path width, typically set 0 for a 32-bit bus width. On other Blackfin derivatives this bit should be set by default. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-common/clocks-init.c')
-rw-r--r--arch/blackfin/mach-common/clocks-init.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index 5d182abefc7b..9dddb6f8cc85 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -14,6 +14,7 @@
14#include <asm/clocks.h> 14#include <asm/clocks.h>
15#include <asm/mem_init.h> 15#include <asm/mem_init.h>
16 16
17#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
17#define PLL_CTL_VAL \ 18#define PLL_CTL_VAL \
18 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ 19 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
19 (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0)) 20 (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0))
@@ -76,7 +77,7 @@ void init_clocks(void)
76 bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); 77 bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
77#ifdef EBIU_SDGCTL 78#ifdef EBIU_SDGCTL
78 bfin_write_EBIU_SDRRC(mem_SDRRC); 79 bfin_write_EBIU_SDRRC(mem_SDRRC);
79 bfin_write_EBIU_SDGCTL(mem_SDGCTL); 80 bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL);
80#else 81#else
81 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); 82 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
82 do_sync(); 83 do_sync();