Blackfin arch: SMP supporting patchset: Blackfin header files and machine common code

Blackfin dual core BF561 processor can support SMP like features.
https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like

In this patch, we provide SMP extend to Blackfin header files
and machine common code

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

1 files changed, 36 insertions, 0 deletions

diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 3c98dacbf289..118751287437 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -97,3 +97,39 @@ ENTRY(_blackfin_dflush_page)
         P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
         jump .Ldfr;
 ENDPROC(_blackfin_dflush_page)
+
+/* Invalidate the Entire Data cache by
+ * clearing DMC[1:0] bits
+ */
+ENTRY(_blackfin_invalidate_entire_dcache)
+        [--SP] = ( R7:5);
+
+        P0.L = LO(DMEM_CONTROL);
+        P0.H = HI(DMEM_CONTROL);
+        R7 = [P0];
+        R5 = R7;        /* Save DMEM_CNTR */
+
+        /* Clear the DMC[1:0] bits, All valid bits in the data
+         * cache are set to the invalid state
+         */
+        BITCLR(R7,DMC0_P);
+        BITCLR(R7,DMC1_P);
+        CLI R6;
+        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+        .align 8;
+        [P0] = R7;
+        SSYNC;
+        STI R6;
+
+        /* Configures the data cache again */
+
+        CLI R6;
+        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+        .align 8;
+        [P0] = R5;
+        SSYNC;
+        STI R6;
+
+        ( R7:5) = [SP++];
+        RTS;
+ENDPROC(_blackfin_invalidate_entire_dcache)