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author | James Morris <jmorris@namei.org> | 2009-03-23 19:52:46 -0400 |
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committer | James Morris <jmorris@namei.org> | 2009-03-23 19:52:46 -0400 |
commit | 703a3cd72817e99201cef84a8a7aecc60b2b3581 (patch) | |
tree | 3e943755178ff410694722bb031f523136fbc432 /arch/blackfin/mach-common/cache.S | |
parent | df7f54c012b92ec93d56b68547351dcdf8a163d3 (diff) | |
parent | 8e0ee43bc2c3e19db56a4adaa9a9b04ce885cd84 (diff) |
Merge branch 'master' into next
Diffstat (limited to 'arch/blackfin/mach-common/cache.S')
-rw-r--r-- | arch/blackfin/mach-common/cache.S | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index 3c98dacbf289..aa0648c6a9fe 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S | |||
@@ -66,11 +66,33 @@ | |||
66 | 66 | ||
67 | /* Invalidate all instruction cache lines assocoiated with this memory area */ | 67 | /* Invalidate all instruction cache lines assocoiated with this memory area */ |
68 | ENTRY(_blackfin_icache_flush_range) | 68 | ENTRY(_blackfin_icache_flush_range) |
69 | /* | ||
70 | * Walkaround to avoid loading wrong instruction after invalidating icache | ||
71 | * and following sequence is met. | ||
72 | * | ||
73 | * 1) One instruction address is cached in the instruction cache. | ||
74 | * 2) This instruction in SDRAM is changed. | ||
75 | * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range(). | ||
76 | * 4) This instruction is executed again, but the old one is loaded. | ||
77 | */ | ||
78 | P0 = R0; | ||
79 | IFLUSH[P0]; | ||
69 | do_flush IFLUSH, , nop | 80 | do_flush IFLUSH, , nop |
70 | ENDPROC(_blackfin_icache_flush_range) | 81 | ENDPROC(_blackfin_icache_flush_range) |
71 | 82 | ||
72 | /* Flush all cache lines assocoiated with this area of memory. */ | 83 | /* Flush all cache lines assocoiated with this area of memory. */ |
73 | ENTRY(_blackfin_icache_dcache_flush_range) | 84 | ENTRY(_blackfin_icache_dcache_flush_range) |
85 | /* | ||
86 | * Walkaround to avoid loading wrong instruction after invalidating icache | ||
87 | * and following sequence is met. | ||
88 | * | ||
89 | * 1) One instruction address is cached in the instruction cache. | ||
90 | * 2) This instruction in SDRAM is changed. | ||
91 | * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range(). | ||
92 | * 4) This instruction is executed again, but the old one is loaded. | ||
93 | */ | ||
94 | P0 = R0; | ||
95 | IFLUSH[P0]; | ||
74 | do_flush FLUSH, IFLUSH | 96 | do_flush FLUSH, IFLUSH |
75 | ENDPROC(_blackfin_icache_dcache_flush_range) | 97 | ENDPROC(_blackfin_icache_dcache_flush_range) |
76 | 98 | ||