diff options
author | Mike Frysinger <vapier.adi@gmail.com> | 2008-11-18 04:48:22 -0500 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-11-18 04:48:22 -0500 |
commit | 3c1fbd5184f9c3c52c0a392fae0efb0b0d99a079 (patch) | |
tree | 1b94bd6487234e7cbfc0b09bf6221e25e02e0a12 /arch/blackfin/mach-common/cache.S | |
parent | fe85cad25e56aad5e020ea5cab50a100892f645b (diff) |
Blackfin arch: rewrite blackfin_invalidate_entire_dcache function
rewrite blackfin_invalidate_entire_dcache() in C for easier management,
better optimization, and so we take all SSYNC anomalies into account
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-common/cache.S')
-rw-r--r-- | arch/blackfin/mach-common/cache.S | 36 |
1 files changed, 0 insertions, 36 deletions
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index 118751287437..3c98dacbf289 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S | |||
@@ -97,39 +97,3 @@ ENTRY(_blackfin_dflush_page) | |||
97 | P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT); | 97 | P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT); |
98 | jump .Ldfr; | 98 | jump .Ldfr; |
99 | ENDPROC(_blackfin_dflush_page) | 99 | ENDPROC(_blackfin_dflush_page) |
100 | |||
101 | /* Invalidate the Entire Data cache by | ||
102 | * clearing DMC[1:0] bits | ||
103 | */ | ||
104 | ENTRY(_blackfin_invalidate_entire_dcache) | ||
105 | [--SP] = ( R7:5); | ||
106 | |||
107 | P0.L = LO(DMEM_CONTROL); | ||
108 | P0.H = HI(DMEM_CONTROL); | ||
109 | R7 = [P0]; | ||
110 | R5 = R7; /* Save DMEM_CNTR */ | ||
111 | |||
112 | /* Clear the DMC[1:0] bits, All valid bits in the data | ||
113 | * cache are set to the invalid state | ||
114 | */ | ||
115 | BITCLR(R7,DMC0_P); | ||
116 | BITCLR(R7,DMC1_P); | ||
117 | CLI R6; | ||
118 | SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ | ||
119 | .align 8; | ||
120 | [P0] = R7; | ||
121 | SSYNC; | ||
122 | STI R6; | ||
123 | |||
124 | /* Configures the data cache again */ | ||
125 | |||
126 | CLI R6; | ||
127 | SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ | ||
128 | .align 8; | ||
129 | [P0] = R5; | ||
130 | SSYNC; | ||
131 | STI R6; | ||
132 | |||
133 | ( R7:5) = [SP++]; | ||
134 | RTS; | ||
135 | ENDPROC(_blackfin_invalidate_entire_dcache) | ||