blackfin: Support L1 SRAM parity checking feature on bf60x

Move code for the SEC faults from the IRQ hanlders into IRQ actions.
refine bfin fault routine handle

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Steven Miao <realmz6@gmail.com>

1 files changed, 10 insertions, 0 deletions

diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c
index 1a5a28829c6b..f4adedc92895 100644
--- a/arch/blackfin/mach-common/cache-c.c
+++ b/arch/blackfin/mach-common/cache-c.c
@@ -41,6 +41,16 @@ bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
                 unsigned long mem_mask)
 {
         int i;
+#ifdef CONFIG_L1_PARITY_CHECK
+        u32 ctrl;
+
+        if (cplb_addr == DCPLB_ADDR0) {
+                ctrl = bfin_read32(mem_control) | (1 << RDCHK);
+                CSYNC();
+                bfin_write32(mem_control, ctrl);
+                SSYNC();
+        }
+#endif
 
         for (i = 0; i < MAX_CPLBS; i++) {
                 bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);