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authorSonic Zhang <sonic.zhang@analog.com>2012-05-16 05:24:33 -0400
committerBob Liu <lliubbo@gmail.com>2012-05-21 02:54:10 -0400
commit22a826288522863fb748851824ce634eda4f1b07 (patch)
treebe067a769fd87f8ae408cd772c5a88fc0844cdea /arch/blackfin/mach-bf609/include
parentb2286f2b4300711e25743d2f9117dcc02bc2e9b1 (diff)
blackfin: mach-bf609: add machine files
Add machine files for bf60x including head files, Kconfig/Makefile and board file. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat (limited to 'arch/blackfin/mach-bf609/include')
-rw-r--r--arch/blackfin/mach-bf609/include/mach/anomaly.h129
-rw-r--r--arch/blackfin/mach-bf609/include/mach/bf609.h93
-rw-r--r--arch/blackfin/mach-bf609/include/mach/bfin_serial.h17
-rw-r--r--arch/blackfin/mach-bf609/include/mach/blackfin.h25
-rw-r--r--arch/blackfin/mach-bf609/include/mach/cdefBF609.h15
-rw-r--r--arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h3252
-rw-r--r--arch/blackfin/mach-bf609/include/mach/defBF609.h15
-rw-r--r--arch/blackfin/mach-bf609/include/mach/defBF60x_base.h3587
-rw-r--r--arch/blackfin/mach-bf609/include/mach/dma.h116
-rw-r--r--arch/blackfin/mach-bf609/include/mach/gpio.h171
-rw-r--r--arch/blackfin/mach-bf609/include/mach/irq.h318
-rw-r--r--arch/blackfin/mach-bf609/include/mach/mem_map.h86
-rw-r--r--arch/blackfin/mach-bf609/include/mach/pll.h1
-rw-r--r--arch/blackfin/mach-bf609/include/mach/portmux.h347
14 files changed, 8172 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
new file mode 100644
index 000000000000..11e94ef321f8
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/anomaly.h
@@ -0,0 +1,129 @@
1/*
2 * DO NOT EDIT THIS FILE
3 * This file is under version control at
4 * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE
7 *
8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */
12
13/* This file should be up to date with:
14 */
15
16#if __SILICON_REVISION__ < 0
17# error will not work on BF506 silicon version
18#endif
19
20#ifndef _MACH_ANOMALY_H_
21#define _MACH_ANOMALY_H_
22
23/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
24#define ANOMALY_05000074 (1)
25/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
26#define ANOMALY_05000119 (1)
27/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
28#define ANOMALY_05000122 (1)
29/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
30#define ANOMALY_05000245 (1)
31/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
32#define ANOMALY_05000254 (1)
33/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
34#define ANOMALY_05000265 (1)
35/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
36#define ANOMALY_05000310 (1)
37/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
38#define ANOMALY_05000366 (1)
39/* Speculative Fetches Can Cause Undesired External FIFO Operations */
40#define ANOMALY_05000416 (1)
41/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
42#define ANOMALY_05000426 (1)
43/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
44#define ANOMALY_05000443 (1)
45/* UART IrDA Receiver Fails on Extended Bit Pulses */
46#define ANOMALY_05000447 (1)
47/* False Hardware Error when RETI Points to Invalid Memory */
48#define ANOMALY_05000461 (1)
49/* PLL Latches Incorrect Settings During Reset */
50#define ANOMALY_05000469 (1)
51/* Incorrect Default MSEL Value in PLL_CTL */
52#define ANOMALY_05000472 (1)
53/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
54#define ANOMALY_05000473 (1)
55/* TESTSET Instruction Cannot Be Interrupted */
56#define ANOMALY_05000477 (1)
57/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
58#define ANOMALY_05000481 (1)
59/* IFLUSH sucks at life */
60#define ANOMALY_05000491 (1)
61
62/* Anomalies that don't exist on this proc */
63#define ANOMALY_05000099 (0)
64#define ANOMALY_05000120 (0)
65#define ANOMALY_05000125 (0)
66#define ANOMALY_05000149 (0)
67#define ANOMALY_05000158 (0)
68#define ANOMALY_05000171 (0)
69#define ANOMALY_05000179 (0)
70#define ANOMALY_05000182 (0)
71#define ANOMALY_05000183 (0)
72#define ANOMALY_05000189 (0)
73#define ANOMALY_05000198 (0)
74#define ANOMALY_05000202 (0)
75#define ANOMALY_05000215 (0)
76#define ANOMALY_05000219 (0)
77#define ANOMALY_05000220 (0)
78#define ANOMALY_05000227 (0)
79#define ANOMALY_05000230 (0)
80#define ANOMALY_05000231 (0)
81#define ANOMALY_05000233 (0)
82#define ANOMALY_05000234 (0)
83#define ANOMALY_05000242 (0)
84#define ANOMALY_05000244 (0)
85#define ANOMALY_05000248 (0)
86#define ANOMALY_05000250 (0)
87#define ANOMALY_05000257 (0)
88#define ANOMALY_05000261 (0)
89#define ANOMALY_05000263 (0)
90#define ANOMALY_05000266 (0)
91#define ANOMALY_05000273 (0)
92#define ANOMALY_05000274 (0)
93#define ANOMALY_05000278 (0)
94#define ANOMALY_05000281 (0)
95#define ANOMALY_05000283 (0)
96#define ANOMALY_05000285 (0)
97#define ANOMALY_05000287 (0)
98#define ANOMALY_05000301 (0)
99#define ANOMALY_05000305 (0)
100#define ANOMALY_05000307 (0)
101#define ANOMALY_05000311 (0)
102#define ANOMALY_05000312 (0)
103#define ANOMALY_05000315 (0)
104#define ANOMALY_05000323 (0)
105#define ANOMALY_05000353 (1)
106#define ANOMALY_05000357 (0)
107#define ANOMALY_05000362 (1)
108#define ANOMALY_05000363 (0)
109#define ANOMALY_05000364 (0)
110#define ANOMALY_05000371 (0)
111#define ANOMALY_05000380 (0)
112#define ANOMALY_05000386 (0)
113#define ANOMALY_05000389 (0)
114#define ANOMALY_05000400 (0)
115#define ANOMALY_05000402 (0)
116#define ANOMALY_05000412 (0)
117#define ANOMALY_05000432 (0)
118#define ANOMALY_05000440 (0)
119#define ANOMALY_05000448 (0)
120#define ANOMALY_05000456 (0)
121#define ANOMALY_05000450 (0)
122#define ANOMALY_05000465 (0)
123#define ANOMALY_05000467 (0)
124#define ANOMALY_05000474 (0)
125#define ANOMALY_05000475 (0)
126#define ANOMALY_05000480 (0)
127#define ANOMALY_05000485 (0)
128
129#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/bf609.h b/arch/blackfin/mach-bf609/include/mach/bf609.h
new file mode 100644
index 000000000000..c897c2a2fbfa
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/bf609.h
@@ -0,0 +1,93 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef __MACH_BF609_H__
8#define __MACH_BF609_H__
9
10#define OFFSET_(x) ((x) & 0x0000FFFF)
11
12/*some misc defines*/
13#define IMASK_IVG15 0x8000
14#define IMASK_IVG14 0x4000
15#define IMASK_IVG13 0x2000
16#define IMASK_IVG12 0x1000
17
18#define IMASK_IVG11 0x0800
19#define IMASK_IVG10 0x0400
20#define IMASK_IVG9 0x0200
21#define IMASK_IVG8 0x0100
22
23#define IMASK_IVG7 0x0080
24#define IMASK_IVGTMR 0x0040
25#define IMASK_IVGHW 0x0020
26
27/***************************/
28
29
30#define BFIN_DSUBBANKS 4
31#define BFIN_DWAYS 2
32#define BFIN_DLINES 64
33#define BFIN_ISUBBANKS 4
34#define BFIN_IWAYS 4
35#define BFIN_ILINES 32
36
37#define WAY0_L 0x1
38#define WAY1_L 0x2
39#define WAY01_L 0x3
40#define WAY2_L 0x4
41#define WAY02_L 0x5
42#define WAY12_L 0x6
43#define WAY012_L 0x7
44
45#define WAY3_L 0x8
46#define WAY03_L 0x9
47#define WAY13_L 0xA
48#define WAY013_L 0xB
49
50#define WAY32_L 0xC
51#define WAY320_L 0xD
52#define WAY321_L 0xE
53#define WAYALL_L 0xF
54
55#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
56
57/********************************* EBIU Settings ************************************/
58#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
59#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
60
61#ifdef CONFIG_C_AMBEN_ALL
62#define V_AMBEN AMBEN_ALL
63#endif
64#ifdef CONFIG_C_AMBEN
65#define V_AMBEN 0x0
66#endif
67#ifdef CONFIG_C_AMBEN_B0
68#define V_AMBEN AMBEN_B0
69#endif
70#ifdef CONFIG_C_AMBEN_B0_B1
71#define V_AMBEN AMBEN_B0_B1
72#endif
73#ifdef CONFIG_C_AMBEN_B0_B1_B2
74#define V_AMBEN AMBEN_B0_B1_B2
75#endif
76#ifdef CONFIG_C_AMCKEN
77#define V_AMCKEN AMCKEN
78#else
79#define V_AMCKEN 0x0
80#endif
81
82#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
83
84#if defined(CONFIG_BF609)
85# define CPU "BF609"
86# define CPUID 0x27fe /* temperary fake value */
87#endif
88
89#ifndef CPU
90#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
91#endif
92
93#endif /* __MACH_BF609_H__ */
diff --git a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..1fd398147fd9
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
@@ -0,0 +1,17 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13#define BFIN_UART_TX_FIFO_SIZE 8
14
15#define BFIN_UART_BF60X_STYLE
16
17#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/blackfin.h b/arch/blackfin/mach-bf609/include/mach/blackfin.h
new file mode 100644
index 000000000000..b1a48c410711
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/blackfin.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_BLACKFIN_H_
8#define _MACH_BLACKFIN_H_
9
10#include "bf609.h"
11#include "anomaly.h"
12
13#include <asm/def_LPBlackfin.h>
14#ifdef CONFIG_BF609
15# include "defBF609.h"
16#endif
17
18#ifndef __ASSEMBLY__
19# include <asm/cdef_LPBlackfin.h>
20# ifdef CONFIG_BF609
21# include "cdefBF609.h"
22# endif
23#endif
24
25#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
new file mode 100644
index 000000000000..c4f3fe19acda
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
@@ -0,0 +1,15 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _CDEF_BF609_H
8#define _CDEF_BF609_H
9
10/* include cdefBF60x_base.h for the set of #defines that are common to all ADSP-BF60x bfin_read_()rocessors */
11#include "cdefBF60x_base.h"
12
13/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
14
15#endif /* _CDEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
new file mode 100644
index 000000000000..88a05264ebda
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
@@ -0,0 +1,3252 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _CDEF_BF60X_H
8#define _CDEF_BF60X_H
9
10/* ************************************************************** */
11/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */
12/* ************************************************************** */
13
14/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
15
16#define bfin_read_CHIPID() bfin_read32(CHIPID)
17#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
18
19/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
20
21/* SEC0 Registers */
22#define bfin_read_SEC0_CCTL() bfin_read32(SEC0_CCTL)
23#define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val)
24#define bfin_read_SEC0_CSID() bfin_read32(SEC0_CSID)
25#define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val)
26#define bfin_read_SEC_GCTL() bfin_read32(SEC_GCTL)
27#define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val)
28
29#define bfin_read_SEC_FCTL() bfin_read32(SEC_FCTL)
30#define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val)
31
32#define bfin_read_SEC_SCTL(sid) bfin_read32((SEC_SCTL0 + (sid) * 8))
33#define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val)
34
35#define bfin_read_SEC_SSTAT(sid) bfin_read32((SEC_SSTAT0 + (sid) * 8))
36#define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
37
38/* RCU0 Registers */
39#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL)
40#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
41
42/* Watchdog Timer Registers */
43#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
44#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
45#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
46#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
47#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
48#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
49
50/* RTC Registers */
51
52/* UART0 Registers */
53
54#define bfin_read_UART0_REVID() bfin_read32(UART0_REVID)
55#define bfin_write_UART0_REVID(val) bfin_write32(UART0_REVID, val)
56#define bfin_read_UART0_GCTL() bfin_read32(UART0_GCTL)
57#define bfin_write_UART0_GCTL(val) bfin_write32(UART0_GCTL, val)
58#define bfin_read_UART0_STAT() bfin_read32(UART0_STAT)
59#define bfin_write_UART0_STAT(val) bfin_write32(UART0_STAT, val)
60#define bfin_read_UART0_SCR() bfin_read32(UART0_SCR)
61#define bfin_write_UART0_SCR(val) bfin_write32(UART0_SCR, val)
62#define bfin_read_UART0_CLK() bfin_read32(UART0_CLK)
63#define bfin_write_UART0_CLK(val) bfin_write32(UART0_CLK, val)
64#define bfin_read_UART0_IER() bfin_read32(UART0_IER)
65#define bfin_write_UART0_IER(val) bfin_write32(UART0_IER, val)
66#define bfin_read_UART0_IER_SET() bfin_read32(UART0_IER_SET)
67#define bfin_write_UART0_IER_SET(val) bfin_write32(UART0_IER_SET, val)
68#define bfin_read_UART0_IER_CLEAR() bfin_read32(UART0_IER_CLEAR)
69#define bfin_write_UART0_IER_CLEAR(val) bfin_write32(UART0_IER_CLEAR, val)
70#define bfin_read_UART0_RBR() bfin_read32(UART0_RBR)
71#define bfin_write_UART0_RBR(val) bfin_write32(UART0_RBR, val)
72#define bfin_read_UART0_THR() bfin_read32(UART0_THR)
73#define bfin_write_UART0_THR(val) bfin_write32(UART0_THR, val)
74#define bfin_read_UART0_TAIP() bfin_read32(UART0_TAIP)
75#define bfin_write_UART0_TAIP(val) bfin_write32(UART0_TAIP, val)
76#define bfin_read_UART0_TSR() bfin_read32(UART0_TSR)
77#define bfin_write_UART0_TSR(val) bfin_write32(UART0_TSR, val)
78#define bfin_read_UART0_RSR() bfin_read32(UART0_RSR)
79#define bfin_write_UART0_RSR(val) bfin_write32(UART0_RSR, val)
80#define bfin_read_UART0_TXCNT() bfin_read32(UART0_TXCNT)
81#define bfin_write_UART0_TXCNT(val) bfin_write32(UART0_TXCNT, val)
82#define bfin_read_UART0_RXCNT() bfin_read32(UART0_RXCNT)
83#define bfin_write_UART0_RXCNT(val) bfin_write32(UART0_RXCNT, val)
84
85/* UART1 Registers */
86
87#define bfin_read_UART1_REVID() bfin_read32(UART1_REVID)
88#define bfin_write_UART1_REVID(val) bfin_write32(UART1_REVID, val)
89#define bfin_read_UART1_GCTL() bfin_read32(UART1_GCTL)
90#define bfin_write_UART1_GCTL(val) bfin_write32(UART1_GCTL, val)
91#define bfin_read_UART1_STAT() bfin_read32(UART1_STAT)
92#define bfin_write_UART1_STAT(val) bfin_write32(UART1_STAT, val)
93#define bfin_read_UART1_SCR() bfin_read32(UART1_SCR)
94#define bfin_write_UART1_SCR(val) bfin_write32(UART1_SCR, val)
95#define bfin_read_UART1_CLK() bfin_read32(UART1_CLK)
96#define bfin_write_UART1_CLK(val) bfin_write32(UART1_CLK, val)
97#define bfin_read_UART1_IER() bfin_read32(UART1_IER)
98#define bfin_write_UART1_IER(val) bfin_write32(UART1_IER, val)
99#define bfin_read_UART1_IER_SET() bfin_read32(UART1_IER_SET)
100#define bfin_write_UART1_IER_SET(val) bfin_write32(UART1_IER_SET, val)
101#define bfin_read_UART1_IER_CLEAR() bfin_read32(UART1_IER_CLEAR)
102#define bfin_write_UART1_IER_CLEAR(val) bfin_write32(UART1_IER_CLEAR, val)
103#define bfin_read_UART1_RBR() bfin_read32(UART1_RBR)
104#define bfin_write_UART1_RBR(val) bfin_write32(UART1_RBR, val)
105#define bfin_read_UART1_THR() bfin_read32(UART1_THR)
106#define bfin_write_UART1_THR(val) bfin_write32(UART1_THR, val)
107#define bfin_read_UART1_TAIP() bfin_read32(UART1_TAIP)
108#define bfin_write_UART1_TAIP(val) bfin_write32(UART1_TAIP, val)
109#define bfin_read_UART1_TSR() bfin_read32(UART1_TSR)
110#define bfin_write_UART1_TSR(val) bfin_write32(UART1_TSR, val)
111#define bfin_read_UART1_RSR() bfin_read32(UART1_RSR)
112#define bfin_write_UART1_RSR(val) bfin_write32(UART1_RSR, val)
113#define bfin_read_UART1_TXCNT() bfin_read32(UART1_TXCNT)
114#define bfin_write_UART1_TXCNT(val) bfin_write32(UART1_TXCNT, val)
115#define bfin_read_UART1_RXCNT() bfin_read32(UART1_RXCNT)
116#define bfin_write_UART1_RXCNT(val) bfin_write32(UART1_RXCNT, val)
117
118
119/* SPI0 Registers */
120
121#define bfin_read_SPI0_CTL() bfin_read32(SPI0_CTL)
122#define bfin_write_SPI0_CTL(val) bfin_write32(SPI0_CTL, val)
123#define bfin_read_SPI0_RXCTL() bfin_read32(SPI0_RXCTL)
124#define bfin_write_SPI0_RXCTL(val) bfin_write32(SPI0_RXCTL, val)
125#define bfin_read_SPI0_TXCTL() bfin_read32(SPI0_TXCTL)
126#define bfin_write_SPI0_TXCTL(val) bfin_write32(SPI0_TXCTL, val)
127#define bfin_read_SPI0_CLK() bfin_read32(SPI0_CLK)
128#define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val)
129#define bfin_read_SPI0_DLY() bfin_read32(SPI0_DLY)
130#define bfin_write_SPI0_DLY(val) bfin_write32(SPI0_DLY, val)
131#define bfin_read_SPI0_SLVSEL() bfin_read32(SPI0_SLVSEL)
132#define bfin_write_SPI0_SLVSEL(val) bfin_write32(SPI0_SLVSEL, val)
133#define bfin_read_SPI0_RWC() bfin_read32(SPI0_RWC)
134#define bfin_write_SPI0_RWC(val) bfin_write32(SPI0_RWC, val)
135#define bfin_read_SPI0_RWCR() bfin_read32(SPI0_RWCR)
136#define bfin_write_SPI0_RWCR(val) bfin_write32(SPI0_RWCR, val)
137#define bfin_read_SPI0_TWC() bfin_read32(SPI0_TWC)
138#define bfin_write_SPI0_TWC(val) bfin_write32(SPI0_TWC, val)
139#define bfin_read_SPI0_TWCR() bfin_read32(SPI0_TWCR)
140#define bfin_write_SPI0_TWCR(val) bfin_write32(SPI0_TWCR, val)
141#define bfin_read_SPI0_IMSK() bfin_read32(SPI0_IMSK)
142#define bfin_write_SPI0_IMSK(val) bfin_write32(SPI0_IMSK, val)
143#define bfin_read_SPI0_IMSK_CLR() bfin_read32(SPI0_IMSK_CLR)
144#define bfin_write_SPI0_IMSK_CLR(val) bfin_write32(SPI0_IMSK_CLR, val)
145#define bfin_read_SPI0_IMSK_SET() bfin_read32(SPI0_IMSK_SET)
146#define bfin_write_SPI0_IMSK_SET(val) bfin_write32(SPI0_IMSK_SET, val)
147#define bfin_read_SPI0_STAT() bfin_read32(SPI0_STAT)
148#define bfin_write_SPI0_STAT(val) bfin_write32(SPI0_STAT, val)
149#define bfin_read_SPI0_ILAT() bfin_read32(SPI0_ILAT)
150#define bfin_write_SPI0_ILAT(val) bfin_write32(SPI0_ILAT, val)
151#define bfin_read_SPI0_ILAT_CLR() bfin_read32(SPI0_ILAT_CLR)
152#define bfin_write_SPI0_ILAT_CLR(val) bfin_write32(SPI0_ILAT_CLR, val)
153#define bfin_read_SPI0_RFIFO() bfin_read32(SPI0_RFIFO)
154#define bfin_write_SPI0_RFIFO(val) bfin_write32(SPI0_RFIFO, val)
155#define bfin_read_SPI0_TFIFO() bfin_read32(SPI0_TFIFO)
156#define bfin_write_SPI0_TFIFO(val) bfin_write32(SPI0_TFIFO, val)
157
158/* SPI1 Registers */
159
160#define bfin_read_SPI1_CTL() bfin_read32(SPI1_CTL)
161#define bfin_write_SPI1_CTL(val) bfin_write32(SPI1_CTL, val)
162#define bfin_read_SPI1_RXCTL() bfin_read32(SPI1_RXCTL)
163#define bfin_write_SPI1_RXCTL(val) bfin_write32(SPI1_RXCTL, val)
164#define bfin_read_SPI1_TXCTL() bfin_read32(SPI1_TXCTL)
165#define bfin_write_SPI1_TXCTL(val) bfin_write32(SPI1_TXCTL, val)
166#define bfin_read_SPI1_CLK() bfin_read32(SPI1_CLK)
167#define bfin_write_SPI1_CLK(val) bfin_write32(SPI1_CLK, val)
168#define bfin_read_SPI1_DLY() bfin_read32(SPI1_DLY)
169#define bfin_write_SPI1_DLY(val) bfin_write32(SPI1_DLY, val)
170#define bfin_read_SPI1_SLVSEL() bfin_read32(SPI1_SLVSEL)
171#define bfin_write_SPI1_SLVSEL(val) bfin_write32(SPI1_SLVSEL, val)
172#define bfin_read_SPI1_RWC() bfin_read32(SPI1_RWC)
173#define bfin_write_SPI1_RWC(val) bfin_write32(SPI1_RWC, val)
174#define bfin_read_SPI1_RWCR() bfin_read32(SPI1_RWCR)
175#define bfin_write_SPI1_RWCR(val) bfin_write32(SPI1_RWCR, val)
176#define bfin_read_SPI1_TWC() bfin_read32(SPI1_TWC)
177#define bfin_write_SPI1_TWC(val) bfin_write32(SPI1_TWC, val)
178#define bfin_read_SPI1_TWCR() bfin_read32(SPI1_TWCR)
179#define bfin_write_SPI1_TWCR(val) bfin_write32(SPI1_TWCR, val)
180#define bfin_read_SPI1_IMSK() bfin_read32(SPI1_IMSK)
181#define bfin_write_SPI1_IMSK(val) bfin_write32(SPI1_IMSK, val)
182#define bfin_read_SPI1_IMSK_CLR() bfin_read32(SPI1_IMSK_CLR)
183#define bfin_write_SPI1_IMSK_CLR(val) bfin_write32(SPI1_IMSK_CLR, val)
184#define bfin_read_SPI1_IMSK_SET() bfin_read32(SPI1_IMSK_SET)
185#define bfin_write_SPI1_IMSK_SET(val) bfin_write32(SPI1_IMSK_SET, val)
186#define bfin_read_SPI1_STAT() bfin_read32(SPI1_STAT)
187#define bfin_write_SPI1_STAT(val) bfin_write32(SPI1_STAT, val)
188#define bfin_read_SPI1_ILAT() bfin_read32(SPI1_ILAT)
189#define bfin_write_SPI1_ILAT(val) bfin_write32(SPI1_ILAT, val)
190#define bfin_read_SPI1_ILAT_CLR() bfin_read32(SPI1_ILAT_CLR)
191#define bfin_write_SPI1_ILAT_CLR(val) bfin_write32(SPI1_ILAT_CLR, val)
192#define bfin_read_SPI1_RFIFO() bfin_read32(SPI1_RFIFO)
193#define bfin_write_SPI1_RFIFO(val) bfin_write32(SPI1_RFIFO, val)
194#define bfin_read_SPI1_TFIFO() bfin_read32(SPI1_TFIFO)
195#define bfin_write_SPI1_TFIFO(val) bfin_write32(SPI1_TFIFO, val)
196
197/* Timer 0-7 registers */
198#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
199#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
200#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
201#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
202#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
203#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
204#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
205#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
206#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
207#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
208#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
209#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
210#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
211#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
212#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
213#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
214#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
215#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
216#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
217#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
218#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
219#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
220#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
221#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
222#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
223#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
224#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
225#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
226#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
227#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
228#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
229#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
230#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
231#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
232#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
233#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
234#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
235#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
236#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
237#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
238#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
239#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
240#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
241#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
242#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
243#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
244#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
245#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
246#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
247#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
248#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
249#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
250#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
251#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
252#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
253#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
254#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
255#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
256#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
257#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
258#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
259#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
260#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
261#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
262
263
264
265
266/* Two Wire Interface Registers (TWI0) */
267
268/* SPORT1 Registers */
269
270
271/* SMC Registers */
272#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
273#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
274#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
275#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
276#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
277#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
278#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
279#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
280#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
281#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
282#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
283#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
284#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
285#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
286#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
287#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
288#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
289#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
290#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
291#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
292#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
293#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
294#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
295#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
296#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
297#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
298#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
299
300/* DDR2 Memory Control Registers */
301#define bfin_read_DDR0_CFG() bfin_read32(DDR0_CFG)
302#define bfin_write_DDR0_CFG(val) bfin_write32(DDR0_CFG, val)
303#define bfin_read_DDR0_TR0() bfin_read32(DDR0_TR0)
304#define bfin_write_DDR0_TR0(val) bfin_write32(DDR0_TR0, val)
305#define bfin_read_DDR0_TR1() bfin_read32(DDR0_TR1)
306#define bfin_write_DDR0_TR1(val) bfin_write32(DDR0_TR1, val)
307#define bfin_read_DDR0_TR2() bfin_read32(DDR0_TR2)
308#define bfin_write_DDR0_TR2(val) bfin_write32(DDR0_TR2, val)
309#define bfin_read_DDR0_MR() bfin_read32(DDR0_MR)
310#define bfin_write_DDR0_MR(val) bfin_write32(DDR0_MR, val)
311#define bfin_read_DDR0_EMR1() bfin_read32(DDR0_EMR1)
312#define bfin_write_DDR0_EMR1(val) bfin_write32(DDR0_EMR1, val)
313#define bfin_read_DDR0_CTL() bfin_read32(DDR0_CTL)
314#define bfin_write_DDR0_CTL(val) bfin_write32(DDR0_CTL, val)
315#define bfin_read_DDR0_STAT() bfin_read32(DDR0_STAT)
316#define bfin_write_DDR0_STAT(val) bfin_write32(DDR0_STAT, val)
317#define bfin_read_DDR0_DLLCTL() bfin_read32(DDR0_DLLCTL)
318#define bfin_write_DDR0_DLLCTL(val) bfin_write32(DDR0_DLLCTL, val)
319
320/* DDR BankRead and Write Count Registers */
321
322
323/* DMA Channel 0 Registers */
324
325#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
326#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
327#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
328#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
329#define bfin_read_DMA0_CONFIG() bfin_read32(DMA0_CONFIG)
330#define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CONFIG, val)
331#define bfin_read_DMA0_X_COUNT() bfin_read32(DMA0_X_COUNT)
332#define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_X_COUNT, val)
333#define bfin_read_DMA0_X_MODIFY() bfin_read32(DMA0_X_MODIFY)
334#define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_X_MODIFY, val)
335#define bfin_read_DMA0_Y_COUNT() bfin_read32(DMA0_Y_COUNT)
336#define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_Y_COUNT, val)
337#define bfin_read_DMA0_Y_MODIFY() bfin_read32(DMA0_Y_MODIFY)
338#define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_Y_MODIFY, val)
339#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
340#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
341#define bfin_read_DMA0_PREV_DESC_PTR() bfin_read32(DMA0_PREV_DESC_PTR)
342#define bfin_write_DMA0_PREV_DESC_PTR(val) bfin_write32(DMA0_PREV_DESC_PTR, val)
343#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
344#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
345#define bfin_read_DMA0_IRQ_STATUS() bfin_read32(DMA0_IRQ_STATUS)
346#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write32(DMA0_IRQ_STATUS, val)
347#define bfin_read_DMA0_CURR_X_COUNT() bfin_read32(DMA0_CURR_X_COUNT)
348#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write32(DMA0_CURR_X_COUNT, val)
349#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read32(DMA0_CURR_Y_COUNT)
350#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write32(DMA0_CURR_Y_COUNT, val)
351#define bfin_read_DMA0_BWL_COUNT() bfin_read32(DMA0_BWL_COUNT)
352#define bfin_write_DMA0_BWL_COUNT(val) bfin_write32(DMA0_BWL_COUNT, val)
353#define bfin_read_DMA0_CURR_BWL_COUNT() bfin_read32(DMA0_CURR_BWL_COUNT)
354#define bfin_write_DMA0_CURR_BWL_COUNT(val) bfin_write32(DMA0_CURR_BWL_COUNT, val)
355#define bfin_read_DMA0_BWM_COUNT() bfin_read32(DMA0_BWM_COUNT)
356#define bfin_write_DMA0_BWM_COUNT(val) bfin_write32(DMA0_BWM_COUNT, val)
357#define bfin_read_DMA0_CURR_BWM_COUNT() bfin_read32(DMA0_CURR_BWM_COUNT)
358#define bfin_write_DMA0_CURR_BWM_COUNT(val) bfin_write32(DMA0_CURR_BWM_COUNT, val)
359
360/* DMA Channel 1 Registers */
361
362#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
363#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
364#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
365#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
366#define bfin_read_DMA1_CONFIG() bfin_read32(DMA1_CONFIG)
367#define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CONFIG, val)
368#define bfin_read_DMA1_X_COUNT() bfin_read32(DMA1_X_COUNT)
369#define bfin_write_DMA1_X_COUNT(val) bfin_write32(DMA1_X_COUNT, val)
370#define bfin_read_DMA1_X_MODIFY() bfin_read32(DMA1_X_MODIFY)
371#define bfin_write_DMA1_X_MODIFY(val) bfin_write32(DMA1_X_MODIFY, val)
372#define bfin_read_DMA1_Y_COUNT() bfin_read32(DMA1_Y_COUNT)
373#define bfin_write_DMA1_Y_COUNT(val) bfin_write32(DMA1_Y_COUNT, val)
374#define bfin_read_DMA1_Y_MODIFY() bfin_read32(DMA1_Y_MODIFY)
375#define bfin_write_DMA1_Y_MODIFY(val) bfin_write32(DMA1_Y_MODIFY, val)
376#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
377#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
378#define bfin_read_DMA1_PREV_DESC_PTR() bfin_read32(DMA1_PREV_DESC_PTR)
379#define bfin_write_DMA1_PREV_DESC_PTR(val) bfin_write32(DMA1_PREV_DESC_PTR, val)
380#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
381#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
382#define bfin_read_DMA1_IRQ_STATUS() bfin_read32(DMA1_IRQ_STATUS)
383#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write32(DMA1_IRQ_STATUS, val)
384#define bfin_read_DMA1_CURR_X_COUNT() bfin_read32(DMA1_CURR_X_COUNT)
385#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write32(DMA1_CURR_X_COUNT, val)
386#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read32(DMA1_CURR_Y_COUNT)
387#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write32(DMA1_CURR_Y_COUNT, val)
388#define bfin_read_DMA1_BWL_COUNT() bfin_read32(DMA1_BWL_COUNT)
389#define bfin_write_DMA1_BWL_COUNT(val) bfin_write32(DMA1_BWL_COUNT, val)
390#define bfin_read_DMA1_CURR_BWL_COUNT() bfin_read32(DMA1_CURR_BWL_COUNT)
391#define bfin_write_DMA1_CURR_BWL_COUNT(val) bfin_write32(DMA1_CURR_BWL_COUNT, val)
392#define bfin_read_DMA1_BWM_COUNT() bfin_read32(DMA1_BWM_COUNT)
393#define bfin_write_DMA1_BWM_COUNT(val) bfin_write32(DMA1_BWM_COUNT, val)
394#define bfin_read_DMA1_CURR_BWM_COUNT() bfin_read32(DMA1_CURR_BWM_COUNT)
395#define bfin_write_DMA1_CURR_BWM_COUNT(val) bfin_write32(DMA1_CURR_BWM_COUNT, val)
396
397/* DMA Channel 2 Registers */
398
399#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
400#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
401#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
402#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
403#define bfin_read_DMA2_CONFIG() bfin_read32(DMA2_CONFIG)
404#define bfin_write_DMA2_CONFIG(val) bfin_write32(DMA2_CONFIG, val)
405#define bfin_read_DMA2_X_COUNT() bfin_read32(DMA2_X_COUNT)
406#define bfin_write_DMA2_X_COUNT(val) bfin_write32(DMA2_X_COUNT, val)
407#define bfin_read_DMA2_X_MODIFY() bfin_read32(DMA2_X_MODIFY)
408#define bfin_write_DMA2_X_MODIFY(val) bfin_write32(DMA2_X_MODIFY, val)
409#define bfin_read_DMA2_Y_COUNT() bfin_read32(DMA2_Y_COUNT)
410#define bfin_write_DMA2_Y_COUNT(val) bfin_write32(DMA2_Y_COUNT, val)
411#define bfin_read_DMA2_Y_MODIFY() bfin_read32(DMA2_Y_MODIFY)
412#define bfin_write_DMA2_Y_MODIFY(val) bfin_write32(DMA2_Y_MODIFY, val)
413#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
414#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
415#define bfin_read_DMA2_PREV_DESC_PTR() bfin_read32(DMA2_PREV_DESC_PTR)
416#define bfin_write_DMA2_PREV_DESC_PTR(val) bfin_write32(DMA2_PREV_DESC_PTR, val)
417#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
418#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
419#define bfin_read_DMA2_IRQ_STATUS() bfin_read32(DMA2_IRQ_STATUS)
420#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write32(DMA2_IRQ_STATUS, val)
421#define bfin_read_DMA2_CURR_X_COUNT() bfin_read32(DMA2_CURR_X_COUNT)
422#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write32(DMA2_CURR_X_COUNT, val)
423#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read32(DMA2_CURR_Y_COUNT)
424#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write32(DMA2_CURR_Y_COUNT, val)
425#define bfin_read_DMA2_BWL_COUNT() bfin_read32(DMA2_BWL_COUNT)
426#define bfin_write_DMA2_BWL_COUNT(val) bfin_write32(DMA2_BWL_COUNT, val)
427#define bfin_read_DMA2_CURR_BWL_COUNT() bfin_read32(DMA2_CURR_BWL_COUNT)
428#define bfin_write_DMA2_CURR_BWL_COUNT(val) bfin_write32(DMA2_CURR_BWL_COUNT, val)
429#define bfin_read_DMA2_BWM_COUNT() bfin_read32(DMA2_BWM_COUNT)
430#define bfin_write_DMA2_BWM_COUNT(val) bfin_write32(DMA2_BWM_COUNT, val)
431#define bfin_read_DMA2_CURR_BWM_COUNT() bfin_read32(DMA2_CURR_BWM_COUNT)
432#define bfin_write_DMA2_CURR_BWM_COUNT(val) bfin_write32(DMA2_CURR_BWM_COUNT, val)
433
434/* DMA Channel 3 Registers */
435
436#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
437#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
438#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
439#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
440#define bfin_read_DMA3_CONFIG() bfin_read32(DMA3_CONFIG)
441#define bfin_write_DMA3_CONFIG(val) bfin_write32(DMA3_CONFIG, val)
442#define bfin_read_DMA3_X_COUNT() bfin_read32(DMA3_X_COUNT)
443#define bfin_write_DMA3_X_COUNT(val) bfin_write32(DMA3_X_COUNT, val)
444#define bfin_read_DMA3_X_MODIFY() bfin_read32(DMA3_X_MODIFY)
445#define bfin_write_DMA3_X_MODIFY(val) bfin_write32(DMA3_X_MODIFY, val)
446#define bfin_read_DMA3_Y_COUNT() bfin_read32(DMA3_Y_COUNT)
447#define bfin_write_DMA3_Y_COUNT(val) bfin_write32(DMA3_Y_COUNT, val)
448#define bfin_read_DMA3_Y_MODIFY() bfin_read32(DMA3_Y_MODIFY)
449#define bfin_write_DMA3_Y_MODIFY(val) bfin_write32(DMA3_Y_MODIFY, val)
450#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
451#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
452#define bfin_read_DMA3_PREV_DESC_PTR() bfin_read32(DMA3_PREV_DESC_PTR)
453#define bfin_write_DMA3_PREV_DESC_PTR(val) bfin_write32(DMA3_PREV_DESC_PTR, val)
454#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
455#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
456#define bfin_read_DMA3_IRQ_STATUS() bfin_read32(DMA3_IRQ_STATUS)
457#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_IRQ_STATUS, val)
458#define bfin_read_DMA3_CURR_X_COUNT() bfin_read32(DMA3_CURR_X_COUNT)
459#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write32(DMA3_CURR_X_COUNT, val)
460#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read32(DMA3_CURR_Y_COUNT)
461#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write32(DMA3_CURR_Y_COUNT, val)
462#define bfin_read_DMA3_BWL_COUNT() bfin_read32(DMA3_BWL_COUNT)
463#define bfin_write_DMA3_BWL_COUNT(val) bfin_write32(DMA3_BWL_COUNT, val)
464#define bfin_read_DMA3_CURR_BWL_COUNT() bfin_read32(DMA3_CURR_BWL_COUNT)
465#define bfin_write_DMA3_CURR_BWL_COUNT(val) bfin_write32(DMA3_CURR_BWL_COUNT, val)
466#define bfin_read_DMA3_BWM_COUNT() bfin_read32(DMA3_BWM_COUNT)
467#define bfin_write_DMA3_BWM_COUNT(val) bfin_write32(DMA3_BWM_COUNT, val)
468#define bfin_read_DMA3_CURR_BWM_COUNT() bfin_read32(DMA3_CURR_BWM_COUNT)
469#define bfin_write_DMA3_CURR_BWM_COUNT(val) bfin_write32(DMA3_CURR_BWM_COUNT, val)
470
471/* DMA Channel 4 Registers */
472
473#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
474#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
475#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
476#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
477#define bfin_read_DMA4_CONFIG() bfin_read32(DMA4_CONFIG)
478#define bfin_write_DMA4_CONFIG(val) bfin_write32(DMA4_CONFIG, val)
479#define bfin_read_DMA4_X_COUNT() bfin_read32(DMA4_X_COUNT)
480#define bfin_write_DMA4_X_COUNT(val) bfin_write32(DMA4_X_COUNT, val)
481#define bfin_read_DMA4_X_MODIFY() bfin_read32(DMA4_X_MODIFY)
482#define bfin_write_DMA4_X_MODIFY(val) bfin_write32(DMA4_X_MODIFY, val)
483#define bfin_read_DMA4_Y_COUNT() bfin_read32(DMA4_Y_COUNT)
484#define bfin_write_DMA4_Y_COUNT(val) bfin_write32(DMA4_Y_COUNT, val)
485#define bfin_read_DMA4_Y_MODIFY() bfin_read32(DMA4_Y_MODIFY)
486#define bfin_write_DMA4_Y_MODIFY(val) bfin_write32(DMA4_Y_MODIFY, val)
487#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
488#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
489#define bfin_read_DMA4_PREV_DESC_PTR() bfin_read32(DMA4_PREV_DESC_PTR)
490#define bfin_write_DMA4_PREV_DESC_PTR(val) bfin_write32(DMA4_PREV_DESC_PTR, val)
491#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
492#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
493#define bfin_read_DMA4_IRQ_STATUS() bfin_read32(DMA4_IRQ_STATUS)
494#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write32(DMA4_IRQ_STATUS, val)
495#define bfin_read_DMA4_CURR_X_COUNT() bfin_read32(DMA4_CURR_X_COUNT)
496#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write32(DMA4_CURR_X_COUNT, val)
497#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read32(DMA4_CURR_Y_COUNT)
498#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write32(DMA4_CURR_Y_COUNT, val)
499#define bfin_read_DMA4_BWL_COUNT() bfin_read32(DMA4_BWL_COUNT)
500#define bfin_write_DMA4_BWL_COUNT(val) bfin_write32(DMA4_BWL_COUNT, val)
501#define bfin_read_DMA4_CURR_BWL_COUNT() bfin_read32(DMA4_CURR_BWL_COUNT)
502#define bfin_write_DMA4_CURR_BWL_COUNT(val) bfin_write32(DMA4_CURR_BWL_COUNT, val)
503#define bfin_read_DMA4_BWM_COUNT() bfin_read32(DMA4_BWM_COUNT)
504#define bfin_write_DMA4_BWM_COUNT(val) bfin_write32(DMA4_BWM_COUNT, val)
505#define bfin_read_DMA4_CURR_BWM_COUNT() bfin_read32(DMA4_CURR_BWM_COUNT)
506#define bfin_write_DMA4_CURR_BWM_COUNT(val) bfin_write32(DMA4_CURR_BWM_COUNT, val)
507
508/* DMA Channel 5 Registers */
509
510#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
511#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
512#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
513#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
514#define bfin_read_DMA5_CONFIG() bfin_read32(DMA5_CONFIG)
515#define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CONFIG, val)
516#define bfin_read_DMA5_X_COUNT() bfin_read32(DMA5_X_COUNT)
517#define bfin_write_DMA5_X_COUNT(val) bfin_write32(DMA5_X_COUNT, val)
518#define bfin_read_DMA5_X_MODIFY() bfin_read32(DMA5_X_MODIFY)
519#define bfin_write_DMA5_X_MODIFY(val) bfin_write32(DMA5_X_MODIFY, val)
520#define bfin_read_DMA5_Y_COUNT() bfin_read32(DMA5_Y_COUNT)
521#define bfin_write_DMA5_Y_COUNT(val) bfin_write32(DMA5_Y_COUNT, val)
522#define bfin_read_DMA5_Y_MODIFY() bfin_read32(DMA5_Y_MODIFY)
523#define bfin_write_DMA5_Y_MODIFY(val) bfin_write32(DMA5_Y_MODIFY, val)
524#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
525#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
526#define bfin_read_DMA5_PREV_DESC_PTR() bfin_read32(DMA5_PREV_DESC_PTR)
527#define bfin_write_DMA5_PREV_DESC_PTR(val) bfin_write32(DMA5_PREV_DESC_PTR, val)
528#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
529#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
530#define bfin_read_DMA5_IRQ_STATUS() bfin_read32(DMA5_IRQ_STATUS)
531#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write32(DMA5_IRQ_STATUS, val)
532#define bfin_read_DMA5_CURR_X_COUNT() bfin_read32(DMA5_CURR_X_COUNT)
533#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write32(DMA5_CURR_X_COUNT, val)
534#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read32(DMA5_CURR_Y_COUNT)
535#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write32(DMA5_CURR_Y_COUNT, val)
536#define bfin_read_DMA5_BWL_COUNT() bfin_read32(DMA5_BWL_COUNT)
537#define bfin_write_DMA5_BWL_COUNT(val) bfin_write32(DMA5_BWL_COUNT, val)
538#define bfin_read_DMA5_CURR_BWL_COUNT() bfin_read32(DMA5_CURR_BWL_COUNT)
539#define bfin_write_DMA5_CURR_BWL_COUNT(val) bfin_write32(DMA5_CURR_BWL_COUNT, val)
540#define bfin_read_DMA5_BWM_COUNT() bfin_read32(DMA5_BWM_COUNT)
541#define bfin_write_DMA5_BWM_COUNT(val) bfin_write32(DMA5_BWM_COUNT, val)
542#define bfin_read_DMA5_CURR_BWM_COUNT() bfin_read32(DMA5_CURR_BWM_COUNT)
543#define bfin_write_DMA5_CURR_BWM_COUNT(val) bfin_write32(DMA5_CURR_BWM_COUNT, val)
544
545/* DMA Channel 6 Registers */
546
547#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
548#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
549#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
550#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
551#define bfin_read_DMA6_CONFIG() bfin_read32(DMA6_CONFIG)
552#define bfin_write_DMA6_CONFIG(val) bfin_write32(DMA6_CONFIG, val)
553#define bfin_read_DMA6_X_COUNT() bfin_read32(DMA6_X_COUNT)
554#define bfin_write_DMA6_X_COUNT(val) bfin_write32(DMA6_X_COUNT, val)
555#define bfin_read_DMA6_X_MODIFY() bfin_read32(DMA6_X_MODIFY)
556#define bfin_write_DMA6_X_MODIFY(val) bfin_write32(DMA6_X_MODIFY, val)
557#define bfin_read_DMA6_Y_COUNT() bfin_read32(DMA6_Y_COUNT)
558#define bfin_write_DMA6_Y_COUNT(val) bfin_write32(DMA6_Y_COUNT, val)
559#define bfin_read_DMA6_Y_MODIFY() bfin_read32(DMA6_Y_MODIFY)
560#define bfin_write_DMA6_Y_MODIFY(val) bfin_write32(DMA6_Y_MODIFY, val)
561#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
562#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
563#define bfin_read_DMA6_PREV_DESC_PTR() bfin_read32(DMA6_PREV_DESC_PTR)
564#define bfin_write_DMA6_PREV_DESC_PTR(val) bfin_write32(DMA6_PREV_DESC_PTR, val)
565#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
566#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
567#define bfin_read_DMA6_IRQ_STATUS() bfin_read32(DMA6_IRQ_STATUS)
568#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write32(DMA6_IRQ_STATUS, val)
569#define bfin_read_DMA6_CURR_X_COUNT() bfin_read32(DMA6_CURR_X_COUNT)
570#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write32(DMA6_CURR_X_COUNT, val)
571#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read32(DMA6_CURR_Y_COUNT)
572#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write32(DMA6_CURR_Y_COUNT, val)
573#define bfin_read_DMA6_BWL_COUNT() bfin_read32(DMA6_BWL_COUNT)
574#define bfin_write_DMA6_BWL_COUNT(val) bfin_write32(DMA6_BWL_COUNT, val)
575#define bfin_read_DMA6_CURR_BWL_COUNT() bfin_read32(DMA6_CURR_BWL_COUNT)
576#define bfin_write_DMA6_CURR_BWL_COUNT(val) bfin_write32(DMA6_CURR_BWL_COUNT, val)
577#define bfin_read_DMA6_BWM_COUNT() bfin_read32(DMA6_BWM_COUNT)
578#define bfin_write_DMA6_BWM_COUNT(val) bfin_write32(DMA6_BWM_COUNT, val)
579#define bfin_read_DMA6_CURR_BWM_COUNT() bfin_read32(DMA6_CURR_BWM_COUNT)
580#define bfin_write_DMA6_CURR_BWM_COUNT(val) bfin_write32(DMA6_CURR_BWM_COUNT, val)
581
582/* DMA Channel 7 Registers */
583
584#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
585#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
586#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
587#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
588#define bfin_read_DMA7_CONFIG() bfin_read32(DMA7_CONFIG)
589#define bfin_write_DMA7_CONFIG(val) bfin_write32(DMA7_CONFIG, val)
590#define bfin_read_DMA7_X_COUNT() bfin_read32(DMA7_X_COUNT)
591#define bfin_write_DMA7_X_COUNT(val) bfin_write32(DMA7_X_COUNT, val)
592#define bfin_read_DMA7_X_MODIFY() bfin_read32(DMA7_X_MODIFY)
593#define bfin_write_DMA7_X_MODIFY(val) bfin_write32(DMA7_X_MODIFY, val)
594#define bfin_read_DMA7_Y_COUNT() bfin_read32(DMA7_Y_COUNT)
595#define bfin_write_DMA7_Y_COUNT(val) bfin_write32(DMA7_Y_COUNT, val)
596#define bfin_read_DMA7_Y_MODIFY() bfin_read32(DMA7_Y_MODIFY)
597#define bfin_write_DMA7_Y_MODIFY(val) bfin_write32(DMA7_Y_MODIFY, val)
598#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
599#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
600#define bfin_read_DMA7_PREV_DESC_PTR() bfin_read32(DMA7_PREV_DESC_PTR)
601#define bfin_write_DMA7_PREV_DESC_PTR(val) bfin_write32(DMA7_PREV_DESC_PTR, val)
602#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
603#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
604#define bfin_read_DMA7_IRQ_STATUS() bfin_read32(DMA7_IRQ_STATUS)
605#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_IRQ_STATUS, val)
606#define bfin_read_DMA7_CURR_X_COUNT() bfin_read32(DMA7_CURR_X_COUNT)
607#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write32(DMA7_CURR_X_COUNT, val)
608#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read32(DMA7_CURR_Y_COUNT)
609#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write32(DMA7_CURR_Y_COUNT, val)
610#define bfin_read_DMA7_BWL_COUNT() bfin_read32(DMA7_BWL_COUNT)
611#define bfin_write_DMA7_BWL_COUNT(val) bfin_write32(DMA7_BWL_COUNT, val)
612#define bfin_read_DMA7_CURR_BWL_COUNT() bfin_read32(DMA7_CURR_BWL_COUNT)
613#define bfin_write_DMA7_CURR_BWL_COUNT(val) bfin_write32(DMA7_CURR_BWL_COUNT, val)
614#define bfin_read_DMA7_BWM_COUNT() bfin_read32(DMA7_BWM_COUNT)
615#define bfin_write_DMA7_BWM_COUNT(val) bfin_write32(DMA7_BWM_COUNT, val)
616#define bfin_read_DMA7_CURR_BWM_COUNT() bfin_read32(DMA7_CURR_BWM_COUNT)
617#define bfin_write_DMA7_CURR_BWM_COUNT(val) bfin_write32(DMA7_CURR_BWM_COUNT, val)
618
619/* DMA Channel 8 Registers */
620
621#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
622#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
623#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
624#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
625#define bfin_read_DMA8_CONFIG() bfin_read32(DMA8_CONFIG)
626#define bfin_write_DMA8_CONFIG(val) bfin_write32(DMA8_CONFIG, val)
627#define bfin_read_DMA8_X_COUNT() bfin_read32(DMA8_X_COUNT)
628#define bfin_write_DMA8_X_COUNT(val) bfin_write32(DMA8_X_COUNT, val)
629#define bfin_read_DMA8_X_MODIFY() bfin_read32(DMA8_X_MODIFY)
630#define bfin_write_DMA8_X_MODIFY(val) bfin_write32(DMA8_X_MODIFY, val)
631#define bfin_read_DMA8_Y_COUNT() bfin_read32(DMA8_Y_COUNT)
632#define bfin_write_DMA8_Y_COUNT(val) bfin_write32(DMA8_Y_COUNT, val)
633#define bfin_read_DMA8_Y_MODIFY() bfin_read32(DMA8_Y_MODIFY)
634#define bfin_write_DMA8_Y_MODIFY(val) bfin_write32(DMA8_Y_MODIFY, val)
635#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
636#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
637#define bfin_read_DMA8_PREV_DESC_PTR() bfin_read32(DMA8_PREV_DESC_PTR)
638#define bfin_write_DMA8_PREV_DESC_PTR(val) bfin_write32(DMA8_PREV_DESC_PTR, val)
639#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
640#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
641#define bfin_read_DMA8_IRQ_STATUS() bfin_read32(DMA8_IRQ_STATUS)
642#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_IRQ_STATUS, val)
643#define bfin_read_DMA8_CURR_X_COUNT() bfin_read32(DMA8_CURR_X_COUNT)
644#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write32(DMA8_CURR_X_COUNT, val)
645#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read32(DMA8_CURR_Y_COUNT)
646#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write32(DMA8_CURR_Y_COUNT, val)
647#define bfin_read_DMA8_BWL_COUNT() bfin_read32(DMA8_BWL_COUNT)
648#define bfin_write_DMA8_BWL_COUNT(val) bfin_write32(DMA8_BWL_COUNT, val)
649#define bfin_read_DMA8_CURR_BWL_COUNT() bfin_read32(DMA8_CURR_BWL_COUNT)
650#define bfin_write_DMA8_CURR_BWL_COUNT(val) bfin_write32(DMA8_CURR_BWL_COUNT, val)
651#define bfin_read_DMA8_BWM_COUNT() bfin_read32(DMA8_BWM_COUNT)
652#define bfin_write_DMA8_BWM_COUNT(val) bfin_write32(DMA8_BWM_COUNT, val)
653#define bfin_read_DMA8_CURR_BWM_COUNT() bfin_read32(DMA8_CURR_BWM_COUNT)
654#define bfin_write_DMA8_CURR_BWM_COUNT(val) bfin_write32(DMA8_CURR_BWM_COUNT, val)
655
656/* DMA Channel 9 Registers */
657
658#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
659#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
660#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
661#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
662#define bfin_read_DMA9_CONFIG() bfin_read32(DMA9_CONFIG)
663#define bfin_write_DMA9_CONFIG(val) bfin_write32(DMA9_CONFIG, val)
664#define bfin_read_DMA9_X_COUNT() bfin_read32(DMA9_X_COUNT)
665#define bfin_write_DMA9_X_COUNT(val) bfin_write32(DMA9_X_COUNT, val)
666#define bfin_read_DMA9_X_MODIFY() bfin_read32(DMA9_X_MODIFY)
667#define bfin_write_DMA9_X_MODIFY(val) bfin_write32(DMA9_X_MODIFY, val)
668#define bfin_read_DMA9_Y_COUNT() bfin_read32(DMA9_Y_COUNT)
669#define bfin_write_DMA9_Y_COUNT(val) bfin_write32(DMA9_Y_COUNT, val)
670#define bfin_read_DMA9_Y_MODIFY() bfin_read32(DMA9_Y_MODIFY)
671#define bfin_write_DMA9_Y_MODIFY(val) bfin_write32(DMA9_Y_MODIFY, val)
672#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
673#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
674#define bfin_read_DMA9_PREV_DESC_PTR() bfin_read32(DMA9_PREV_DESC_PTR)
675#define bfin_write_DMA9_PREV_DESC_PTR(val) bfin_write32(DMA9_PREV_DESC_PTR, val)
676#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
677#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
678#define bfin_read_DMA9_IRQ_STATUS() bfin_read32(DMA9_IRQ_STATUS)
679#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write32(DMA9_IRQ_STATUS, val)
680#define bfin_read_DMA9_CURR_X_COUNT() bfin_read32(DMA9_CURR_X_COUNT)
681#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write32(DMA9_CURR_X_COUNT, val)
682#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read32(DMA9_CURR_Y_COUNT)
683#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write32(DMA9_CURR_Y_COUNT, val)
684#define bfin_read_DMA9_BWL_COUNT() bfin_read32(DMA9_BWL_COUNT)
685#define bfin_write_DMA9_BWL_COUNT(val) bfin_write32(DMA9_BWL_COUNT, val)
686#define bfin_read_DMA9_CURR_BWL_COUNT() bfin_read32(DMA9_CURR_BWL_COUNT)
687#define bfin_write_DMA9_CURR_BWL_COUNT(val) bfin_write32(DMA9_CURR_BWL_COUNT, val)
688#define bfin_read_DMA9_BWM_COUNT() bfin_read32(DMA9_BWM_COUNT)
689#define bfin_write_DMA9_BWM_COUNT(val) bfin_write32(DMA9_BWM_COUNT, val)
690#define bfin_read_DMA9_CURR_BWM_COUNT() bfin_read32(DMA9_CURR_BWM_COUNT)
691#define bfin_write_DMA9_CURR_BWM_COUNT(val) bfin_write32(DMA9_CURR_BWM_COUNT, val)
692
693/* DMA Channel 10 Registers */
694
695#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
696#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
697#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
698#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
699#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CONFIG)
700#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CONFIG, val)
701#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_X_COUNT)
702#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_X_COUNT, val)
703#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_X_MODIFY)
704#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_X_MODIFY, val)
705#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_Y_COUNT)
706#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_Y_COUNT, val)
707#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_Y_MODIFY)
708#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_Y_MODIFY, val)
709#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
710#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
711#define bfin_read_DMA10_PREV_DESC_PTR() bfin_read32(DMA10_PREV_DESC_PTR)
712#define bfin_write_DMA10_PREV_DESC_PTR(val) bfin_write32(DMA10_PREV_DESC_PTR, val)
713#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
714#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
715#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_IRQ_STATUS)
716#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_IRQ_STATUS, val)
717#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_CURR_X_COUNT)
718#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_CURR_X_COUNT, val)
719#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_CURR_Y_COUNT)
720#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_CURR_Y_COUNT, val)
721#define bfin_read_DMA10_BWL_COUNT() bfin_read32(DMA10_BWL_COUNT)
722#define bfin_write_DMA10_BWL_COUNT(val) bfin_write32(DMA10_BWL_COUNT, val)
723#define bfin_read_DMA10_CURR_BWL_COUNT() bfin_read32(DMA10_CURR_BWL_COUNT)
724#define bfin_write_DMA10_CURR_BWL_COUNT(val) bfin_write32(DMA10_CURR_BWL_COUNT, val)
725#define bfin_read_DMA10_BWM_COUNT() bfin_read32(DMA10_BWM_COUNT)
726#define bfin_write_DMA10_BWM_COUNT(val) bfin_write32(DMA10_BWM_COUNT, val)
727#define bfin_read_DMA10_CURR_BWM_COUNT() bfin_read32(DMA10_CURR_BWM_COUNT)
728#define bfin_write_DMA10_CURR_BWM_COUNT(val) bfin_write32(DMA10_CURR_BWM_COUNT, val)
729
730/* DMA Channel 11 Registers */
731
732#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
733#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
734#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
735#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
736#define bfin_read_DMA11_CONFIG() bfin_read32(DMA11_CONFIG)
737#define bfin_write_DMA11_CONFIG(val) bfin_write32(DMA11_CONFIG, val)
738#define bfin_read_DMA11_X_COUNT() bfin_read32(DMA11_X_COUNT)
739#define bfin_write_DMA11_X_COUNT(val) bfin_write32(DMA11_X_COUNT, val)
740#define bfin_read_DMA11_X_MODIFY() bfin_read32(DMA11_X_MODIFY)
741#define bfin_write_DMA11_X_MODIFY(val) bfin_write32(DMA11_X_MODIFY, val)
742#define bfin_read_DMA11_Y_COUNT() bfin_read32(DMA11_Y_COUNT)
743#define bfin_write_DMA11_Y_COUNT(val) bfin_write32(DMA11_Y_COUNT, val)
744#define bfin_read_DMA11_Y_MODIFY() bfin_read32(DMA11_Y_MODIFY)
745#define bfin_write_DMA11_Y_MODIFY(val) bfin_write32(DMA11_Y_MODIFY, val)
746#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
747#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
748#define bfin_read_DMA11_PREV_DESC_PTR() bfin_read32(DMA11_PREV_DESC_PTR)
749#define bfin_write_DMA11_PREV_DESC_PTR(val) bfin_write32(DMA11_PREV_DESC_PTR, val)
750#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
751#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
752#define bfin_read_DMA11_IRQ_STATUS() bfin_read32(DMA11_IRQ_STATUS)
753#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write32(DMA11_IRQ_STATUS, val)
754#define bfin_read_DMA11_CURR_X_COUNT() bfin_read32(DMA11_CURR_X_COUNT)
755#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write32(DMA11_CURR_X_COUNT, val)
756#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read32(DMA11_CURR_Y_COUNT)
757#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write32(DMA11_CURR_Y_COUNT, val)
758#define bfin_read_DMA11_BWL_COUNT() bfin_read32(DMA11_BWL_COUNT)
759#define bfin_write_DMA11_BWL_COUNT(val) bfin_write32(DMA11_BWL_COUNT, val)
760#define bfin_read_DMA11_CURR_BWL_COUNT() bfin_read32(DMA11_CURR_BWL_COUNT)
761#define bfin_write_DMA11_CURR_BWL_COUNT(val) bfin_write32(DMA11_CURR_BWL_COUNT, val)
762#define bfin_read_DMA11_BWM_COUNT() bfin_read32(DMA11_BWM_COUNT)
763#define bfin_write_DMA11_BWM_COUNT(val) bfin_write32(DMA11_BWM_COUNT, val)
764#define bfin_read_DMA11_CURR_BWM_COUNT() bfin_read32(DMA11_CURR_BWM_COUNT)
765#define bfin_write_DMA11_CURR_BWM_COUNT(val) bfin_write32(DMA11_CURR_BWM_COUNT, val)
766
767/* DMA Channel 12 Registers */
768
769#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
770#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
771#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
772#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
773#define bfin_read_DMA12_CONFIG() bfin_read32(DMA12_CONFIG)
774#define bfin_write_DMA12_CONFIG(val) bfin_write32(DMA12_CONFIG, val)
775#define bfin_read_DMA12_X_COUNT() bfin_read32(DMA12_X_COUNT)
776#define bfin_write_DMA12_X_COUNT(val) bfin_write32(DMA12_X_COUNT, val)
777#define bfin_read_DMA12_X_MODIFY() bfin_read32(DMA12_X_MODIFY)
778#define bfin_write_DMA12_X_MODIFY(val) bfin_write32(DMA12_X_MODIFY, val)
779#define bfin_read_DMA12_Y_COUNT() bfin_read32(DMA12_Y_COUNT)
780#define bfin_write_DMA12_Y_COUNT(val) bfin_write32(DMA12_Y_COUNT, val)
781#define bfin_read_DMA12_Y_MODIFY() bfin_read32(DMA12_Y_MODIFY)
782#define bfin_write_DMA12_Y_MODIFY(val) bfin_write32(DMA12_Y_MODIFY, val)
783#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
784#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
785#define bfin_read_DMA12_PREV_DESC_PTR() bfin_read32(DMA12_PREV_DESC_PTR)
786#define bfin_write_DMA12_PREV_DESC_PTR(val) bfin_write32(DMA12_PREV_DESC_PTR, val)
787#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
788#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
789#define bfin_read_DMA12_IRQ_STATUS() bfin_read32(DMA12_IRQ_STATUS)
790#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write32(DMA12_IRQ_STATUS, val)
791#define bfin_read_DMA12_CURR_X_COUNT() bfin_read32(DMA12_CURR_X_COUNT)
792#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write32(DMA12_CURR_X_COUNT, val)
793#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read32(DMA12_CURR_Y_COUNT)
794#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write32(DMA12_CURR_Y_COUNT, val)
795#define bfin_read_DMA12_BWL_COUNT() bfin_read32(DMA12_BWL_COUNT)
796#define bfin_write_DMA12_BWL_COUNT(val) bfin_write32(DMA12_BWL_COUNT, val)
797#define bfin_read_DMA12_CURR_BWL_COUNT() bfin_read32(DMA12_CURR_BWL_COUNT)
798#define bfin_write_DMA12_CURR_BWL_COUNT(val) bfin_write32(DMA12_CURR_BWL_COUNT, val)
799#define bfin_read_DMA12_BWM_COUNT() bfin_read32(DMA12_BWM_COUNT)
800#define bfin_write_DMA12_BWM_COUNT(val) bfin_write32(DMA12_BWM_COUNT, val)
801#define bfin_read_DMA12_CURR_BWM_COUNT() bfin_read32(DMA12_CURR_BWM_COUNT)
802#define bfin_write_DMA12_CURR_BWM_COUNT(val) bfin_write32(DMA12_CURR_BWM_COUNT, val)
803
804/* DMA Channel 13 Registers */
805
806#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
807#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
808#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
809#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
810#define bfin_read_DMA13_CONFIG() bfin_read32(DMA13_CONFIG)
811#define bfin_write_DMA13_CONFIG(val) bfin_write32(DMA13_CONFIG, val)
812#define bfin_read_DMA13_X_COUNT() bfin_read32(DMA13_X_COUNT)
813#define bfin_write_DMA13_X_COUNT(val) bfin_write32(DMA13_X_COUNT, val)
814#define bfin_read_DMA13_X_MODIFY() bfin_read32(DMA13_X_MODIFY)
815#define bfin_write_DMA13_X_MODIFY(val) bfin_write32(DMA13_X_MODIFY, val)
816#define bfin_read_DMA13_Y_COUNT() bfin_read32(DMA13_Y_COUNT)
817#define bfin_write_DMA13_Y_COUNT(val) bfin_write32(DMA13_Y_COUNT, val)
818#define bfin_read_DMA13_Y_MODIFY() bfin_read32(DMA13_Y_MODIFY)
819#define bfin_write_DMA13_Y_MODIFY(val) bfin_write32(DMA13_Y_MODIFY, val)
820#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
821#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
822#define bfin_read_DMA13_PREV_DESC_PTR() bfin_read32(DMA13_PREV_DESC_PTR)
823#define bfin_write_DMA13_PREV_DESC_PTR(val) bfin_write32(DMA13_PREV_DESC_PTR, val)
824#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
825#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
826#define bfin_read_DMA13_IRQ_STATUS() bfin_read32(DMA13_IRQ_STATUS)
827#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write32(DMA13_IRQ_STATUS, val)
828#define bfin_read_DMA13_CURR_X_COUNT() bfin_read32(DMA13_CURR_X_COUNT)
829#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write32(DMA13_CURR_X_COUNT, val)
830#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read32(DMA13_CURR_Y_COUNT)
831#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write32(DMA13_CURR_Y_COUNT, val)
832#define bfin_read_DMA13_BWL_COUNT() bfin_read32(DMA13_BWL_COUNT)
833#define bfin_write_DMA13_BWL_COUNT(val) bfin_write32(DMA13_BWL_COUNT, val)
834#define bfin_read_DMA13_CURR_BWL_COUNT() bfin_read32(DMA13_CURR_BWL_COUNT)
835#define bfin_write_DMA13_CURR_BWL_COUNT(val) bfin_write32(DMA13_CURR_BWL_COUNT, val)
836#define bfin_read_DMA13_BWM_COUNT() bfin_read32(DMA13_BWM_COUNT)
837#define bfin_write_DMA13_BWM_COUNT(val) bfin_write32(DMA13_BWM_COUNT, val)
838#define bfin_read_DMA13_CURR_BWM_COUNT() bfin_read32(DMA13_CURR_BWM_COUNT)
839#define bfin_write_DMA13_CURR_BWM_COUNT(val) bfin_write32(DMA13_CURR_BWM_COUNT, val)
840
841/* DMA Channel 14 Registers */
842
843#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
844#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
845#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
846#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
847#define bfin_read_DMA14_CONFIG() bfin_read32(DMA14_CONFIG)
848#define bfin_write_DMA14_CONFIG(val) bfin_write32(DMA14_CONFIG, val)
849#define bfin_read_DMA14_X_COUNT() bfin_read32(DMA14_X_COUNT)
850#define bfin_write_DMA14_X_COUNT(val) bfin_write32(DMA14_X_COUNT, val)
851#define bfin_read_DMA14_X_MODIFY() bfin_read32(DMA14_X_MODIFY)
852#define bfin_write_DMA14_X_MODIFY(val) bfin_write32(DMA14_X_MODIFY, val)
853#define bfin_read_DMA14_Y_COUNT() bfin_read32(DMA14_Y_COUNT)
854#define bfin_write_DMA14_Y_COUNT(val) bfin_write32(DMA14_Y_COUNT, val)
855#define bfin_read_DMA14_Y_MODIFY() bfin_read32(DMA14_Y_MODIFY)
856#define bfin_write_DMA14_Y_MODIFY(val) bfin_write32(DMA14_Y_MODIFY, val)
857#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
858#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
859#define bfin_read_DMA14_PREV_DESC_PTR() bfin_read32(DMA14_PREV_DESC_PTR)
860#define bfin_write_DMA14_PREV_DESC_PTR(val) bfin_write32(DMA14_PREV_DESC_PTR, val)
861#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
862#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
863#define bfin_read_DMA14_IRQ_STATUS() bfin_read32(DMA14_IRQ_STATUS)
864#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write32(DMA14_IRQ_STATUS, val)
865#define bfin_read_DMA14_CURR_X_COUNT() bfin_read32(DMA14_CURR_X_COUNT)
866#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write32(DMA14_CURR_X_COUNT, val)
867#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read32(DMA14_CURR_Y_COUNT)
868#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write32(DMA14_CURR_Y_COUNT, val)
869#define bfin_read_DMA14_BWL_COUNT() bfin_read32(DMA14_BWL_COUNT)
870#define bfin_write_DMA14_BWL_COUNT(val) bfin_write32(DMA14_BWL_COUNT, val)
871#define bfin_read_DMA14_CURR_BWL_COUNT() bfin_read32(DMA14_CURR_BWL_COUNT)
872#define bfin_write_DMA14_CURR_BWL_COUNT(val) bfin_write32(DMA14_CURR_BWL_COUNT, val)
873#define bfin_read_DMA14_BWM_COUNT() bfin_read32(DMA14_BWM_COUNT)
874#define bfin_write_DMA14_BWM_COUNT(val) bfin_write32(DMA14_BWM_COUNT, val)
875#define bfin_read_DMA14_CURR_BWM_COUNT() bfin_read32(DMA14_CURR_BWM_COUNT)
876#define bfin_write_DMA14_CURR_BWM_COUNT(val) bfin_write32(DMA14_CURR_BWM_COUNT, val)
877
878/* DMA Channel 15 Registers */
879
880#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
881#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
882#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
883#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
884#define bfin_read_DMA15_CONFIG() bfin_read32(DMA15_CONFIG)
885#define bfin_write_DMA15_CONFIG(val) bfin_write32(DMA15_CONFIG, val)
886#define bfin_read_DMA15_X_COUNT() bfin_read32(DMA15_X_COUNT)
887#define bfin_write_DMA15_X_COUNT(val) bfin_write32(DMA15_X_COUNT, val)
888#define bfin_read_DMA15_X_MODIFY() bfin_read32(DMA15_X_MODIFY)
889#define bfin_write_DMA15_X_MODIFY(val) bfin_write32(DMA15_X_MODIFY, val)
890#define bfin_read_DMA15_Y_COUNT() bfin_read32(DMA15_Y_COUNT)
891#define bfin_write_DMA15_Y_COUNT(val) bfin_write32(DMA15_Y_COUNT, val)
892#define bfin_read_DMA15_Y_MODIFY() bfin_read32(DMA15_Y_MODIFY)
893#define bfin_write_DMA15_Y_MODIFY(val) bfin_write32(DMA15_Y_MODIFY, val)
894#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
895#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
896#define bfin_read_DMA15_PREV_DESC_PTR() bfin_read32(DMA15_PREV_DESC_PTR)
897#define bfin_write_DMA15_PREV_DESC_PTR(val) bfin_write32(DMA15_PREV_DESC_PTR, val)
898#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
899#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
900#define bfin_read_DMA15_IRQ_STATUS() bfin_read32(DMA15_IRQ_STATUS)
901#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write32(DMA15_IRQ_STATUS, val)
902#define bfin_read_DMA15_CURR_X_COUNT() bfin_read32(DMA15_CURR_X_COUNT)
903#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write32(DMA15_CURR_X_COUNT, val)
904#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read32(DMA15_CURR_Y_COUNT)
905#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write32(DMA15_CURR_Y_COUNT, val)
906#define bfin_read_DMA15_BWL_COUNT() bfin_read32(DMA15_BWL_COUNT)
907#define bfin_write_DMA15_BWL_COUNT(val) bfin_write32(DMA15_BWL_COUNT, val)
908#define bfin_read_DMA15_CURR_BWL_COUNT() bfin_read32(DMA15_CURR_BWL_COUNT)
909#define bfin_write_DMA15_CURR_BWL_COUNT(val) bfin_write32(DMA15_CURR_BWL_COUNT, val)
910#define bfin_read_DMA15_BWM_COUNT() bfin_read32(DMA15_BWM_COUNT)
911#define bfin_write_DMA15_BWM_COUNT(val) bfin_write32(DMA15_BWM_COUNT, val)
912#define bfin_read_DMA15_CURR_BWM_COUNT() bfin_read32(DMA15_CURR_BWM_COUNT)
913#define bfin_write_DMA15_CURR_BWM_COUNT(val) bfin_write32(DMA15_CURR_BWM_COUNT, val)
914
915/* DMA Channel 16 Registers */
916
917#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
918#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
919#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
920#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
921#define bfin_read_DMA16_CONFIG() bfin_read32(DMA16_CONFIG)
922#define bfin_write_DMA16_CONFIG(val) bfin_write32(DMA16_CONFIG, val)
923#define bfin_read_DMA16_X_COUNT() bfin_read32(DMA16_X_COUNT)
924#define bfin_write_DMA16_X_COUNT(val) bfin_write32(DMA16_X_COUNT, val)
925#define bfin_read_DMA16_X_MODIFY() bfin_read32(DMA16_X_MODIFY)
926#define bfin_write_DMA16_X_MODIFY(val) bfin_write32(DMA16_X_MODIFY, val)
927#define bfin_read_DMA16_Y_COUNT() bfin_read32(DMA16_Y_COUNT)
928#define bfin_write_DMA16_Y_COUNT(val) bfin_write32(DMA16_Y_COUNT, val)
929#define bfin_read_DMA16_Y_MODIFY() bfin_read32(DMA16_Y_MODIFY)
930#define bfin_write_DMA16_Y_MODIFY(val) bfin_write32(DMA16_Y_MODIFY, val)
931#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
932#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
933#define bfin_read_DMA16_PREV_DESC_PTR() bfin_read32(DMA16_PREV_DESC_PTR)
934#define bfin_write_DMA16_PREV_DESC_PTR(val) bfin_write32(DMA16_PREV_DESC_PTR, val)
935#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
936#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
937#define bfin_read_DMA16_IRQ_STATUS() bfin_read32(DMA16_IRQ_STATUS)
938#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write32(DMA16_IRQ_STATUS, val)
939#define bfin_read_DMA16_CURR_X_COUNT() bfin_read32(DMA16_CURR_X_COUNT)
940#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write32(DMA16_CURR_X_COUNT, val)
941#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read32(DMA16_CURR_Y_COUNT)
942#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write32(DMA16_CURR_Y_COUNT, val)
943#define bfin_read_DMA16_BWL_COUNT() bfin_read32(DMA16_BWL_COUNT)
944#define bfin_write_DMA16_BWL_COUNT(val) bfin_write32(DMA16_BWL_COUNT, val)
945#define bfin_read_DMA16_CURR_BWL_COUNT() bfin_read32(DMA16_CURR_BWL_COUNT)
946#define bfin_write_DMA16_CURR_BWL_COUNT(val) bfin_write32(DMA16_CURR_BWL_COUNT, val)
947#define bfin_read_DMA16_BWM_COUNT() bfin_read32(DMA16_BWM_COUNT)
948#define bfin_write_DMA16_BWM_COUNT(val) bfin_write32(DMA16_BWM_COUNT, val)
949#define bfin_read_DMA16_CURR_BWM_COUNT() bfin_read32(DMA16_CURR_BWM_COUNT)
950#define bfin_write_DMA16_CURR_BWM_COUNT(val) bfin_write32(DMA16_CURR_BWM_COUNT, val)
951
952/* DMA Channel 17 Registers */
953
954#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
955#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
956#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
957#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
958#define bfin_read_DMA17_CONFIG() bfin_read32(DMA17_CONFIG)
959#define bfin_write_DMA17_CONFIG(val) bfin_write32(DMA17_CONFIG, val)
960#define bfin_read_DMA17_X_COUNT() bfin_read32(DMA17_X_COUNT)
961#define bfin_write_DMA17_X_COUNT(val) bfin_write32(DMA17_X_COUNT, val)
962#define bfin_read_DMA17_X_MODIFY() bfin_read32(DMA17_X_MODIFY)
963#define bfin_write_DMA17_X_MODIFY(val) bfin_write32(DMA17_X_MODIFY, val)
964#define bfin_read_DMA17_Y_COUNT() bfin_read32(DMA17_Y_COUNT)
965#define bfin_write_DMA17_Y_COUNT(val) bfin_write32(DMA17_Y_COUNT, val)
966#define bfin_read_DMA17_Y_MODIFY() bfin_read32(DMA17_Y_MODIFY)
967#define bfin_write_DMA17_Y_MODIFY(val) bfin_write32(DMA17_Y_MODIFY, val)
968#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
969#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
970#define bfin_read_DMA17_PREV_DESC_PTR() bfin_read32(DMA17_PREV_DESC_PTR)
971#define bfin_write_DMA17_PREV_DESC_PTR(val) bfin_write32(DMA17_PREV_DESC_PTR, val)
972#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
973#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
974#define bfin_read_DMA17_IRQ_STATUS() bfin_read32(DMA17_IRQ_STATUS)
975#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write32(DMA17_IRQ_STATUS, val)
976#define bfin_read_DMA17_CURR_X_COUNT() bfin_read32(DMA17_CURR_X_COUNT)
977#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write32(DMA17_CURR_X_COUNT, val)
978#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read32(DMA17_CURR_Y_COUNT)
979#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write32(DMA17_CURR_Y_COUNT, val)
980#define bfin_read_DMA17_BWL_COUNT() bfin_read32(DMA17_BWL_COUNT)
981#define bfin_write_DMA17_BWL_COUNT(val) bfin_write32(DMA17_BWL_COUNT, val)
982#define bfin_read_DMA17_CURR_BWL_COUNT() bfin_read32(DMA17_CURR_BWL_COUNT)
983#define bfin_write_DMA17_CURR_BWL_COUNT(val) bfin_write32(DMA17_CURR_BWL_COUNT, val)
984#define bfin_read_DMA17_BWM_COUNT() bfin_read32(DMA17_BWM_COUNT)
985#define bfin_write_DMA17_BWM_COUNT(val) bfin_write32(DMA17_BWM_COUNT, val)
986#define bfin_read_DMA17_CURR_BWM_COUNT() bfin_read32(DMA17_CURR_BWM_COUNT)
987#define bfin_write_DMA17_CURR_BWM_COUNT(val) bfin_write32(DMA17_CURR_BWM_COUNT, val)
988
989/* DMA Channel 18 Registers */
990
991#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
992#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
993#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
994#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
995#define bfin_read_DMA18_CONFIG() bfin_read32(DMA18_CONFIG)
996#define bfin_write_DMA18_CONFIG(val) bfin_write32(DMA18_CONFIG, val)
997#define bfin_read_DMA18_X_COUNT() bfin_read32(DMA18_X_COUNT)
998#define bfin_write_DMA18_X_COUNT(val) bfin_write32(DMA18_X_COUNT, val)
999#define bfin_read_DMA18_X_MODIFY() bfin_read32(DMA18_X_MODIFY)
1000#define bfin_write_DMA18_X_MODIFY(val) bfin_write32(DMA18_X_MODIFY, val)
1001#define bfin_read_DMA18_Y_COUNT() bfin_read32(DMA18_Y_COUNT)
1002#define bfin_write_DMA18_Y_COUNT(val) bfin_write32(DMA18_Y_COUNT, val)
1003#define bfin_read_DMA18_Y_MODIFY() bfin_read32(DMA18_Y_MODIFY)
1004#define bfin_write_DMA18_Y_MODIFY(val) bfin_write32(DMA18_Y_MODIFY, val)
1005#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
1006#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
1007#define bfin_read_DMA18_PREV_DESC_PTR() bfin_read32(DMA18_PREV_DESC_PTR)
1008#define bfin_write_DMA18_PREV_DESC_PTR(val) bfin_write32(DMA18_PREV_DESC_PTR, val)
1009#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
1010#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
1011#define bfin_read_DMA18_IRQ_STATUS() bfin_read32(DMA18_IRQ_STATUS)
1012#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write32(DMA18_IRQ_STATUS, val)
1013#define bfin_read_DMA18_CURR_X_COUNT() bfin_read32(DMA18_CURR_X_COUNT)
1014#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write32(DMA18_CURR_X_COUNT, val)
1015#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read32(DMA18_CURR_Y_COUNT)
1016#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write32(DMA18_CURR_Y_COUNT, val)
1017#define bfin_read_DMA18_BWL_COUNT() bfin_read32(DMA18_BWL_COUNT)
1018#define bfin_write_DMA18_BWL_COUNT(val) bfin_write32(DMA18_BWL_COUNT, val)
1019#define bfin_read_DMA18_CURR_BWL_COUNT() bfin_read32(DMA18_CURR_BWL_COUNT)
1020#define bfin_write_DMA18_CURR_BWL_COUNT(val) bfin_write32(DMA18_CURR_BWL_COUNT, val)
1021#define bfin_read_DMA18_BWM_COUNT() bfin_read32(DMA18_BWM_COUNT)
1022#define bfin_write_DMA18_BWM_COUNT(val) bfin_write32(DMA18_BWM_COUNT, val)
1023#define bfin_read_DMA18_CURR_BWM_COUNT() bfin_read32(DMA18_CURR_BWM_COUNT)
1024#define bfin_write_DMA18_CURR_BWM_COUNT(val) bfin_write32(DMA18_CURR_BWM_COUNT, val)
1025
1026/* DMA Channel 19 Registers */
1027
1028#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
1029#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
1030#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
1031#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
1032#define bfin_read_DMA19_CONFIG() bfin_read32(DMA19_CONFIG)
1033#define bfin_write_DMA19_CONFIG(val) bfin_write32(DMA19_CONFIG, val)
1034#define bfin_read_DMA19_X_COUNT() bfin_read32(DMA19_X_COUNT)
1035#define bfin_write_DMA19_X_COUNT(val) bfin_write32(DMA19_X_COUNT, val)
1036#define bfin_read_DMA19_X_MODIFY() bfin_read32(DMA19_X_MODIFY)
1037#define bfin_write_DMA19_X_MODIFY(val) bfin_write32(DMA19_X_MODIFY, val)
1038#define bfin_read_DMA19_Y_COUNT() bfin_read32(DMA19_Y_COUNT)
1039#define bfin_write_DMA19_Y_COUNT(val) bfin_write32(DMA19_Y_COUNT, val)
1040#define bfin_read_DMA19_Y_MODIFY() bfin_read32(DMA19_Y_MODIFY)
1041#define bfin_write_DMA19_Y_MODIFY(val) bfin_write32(DMA19_Y_MODIFY, val)
1042#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
1043#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
1044#define bfin_read_DMA19_PREV_DESC_PTR() bfin_read32(DMA19_PREV_DESC_PTR)
1045#define bfin_write_DMA19_PREV_DESC_PTR(val) bfin_write32(DMA19_PREV_DESC_PTR, val)
1046#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
1047#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
1048#define bfin_read_DMA19_IRQ_STATUS() bfin_read32(DMA19_IRQ_STATUS)
1049#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write32(DMA19_IRQ_STATUS, val)
1050#define bfin_read_DMA19_CURR_X_COUNT() bfin_read32(DMA19_CURR_X_COUNT)
1051#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write32(DMA19_CURR_X_COUNT, val)
1052#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read32(DMA19_CURR_Y_COUNT)
1053#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write32(DMA19_CURR_Y_COUNT, val)
1054#define bfin_read_DMA19_BWL_COUNT() bfin_read32(DMA19_BWL_COUNT)
1055#define bfin_write_DMA19_BWL_COUNT(val) bfin_write32(DMA19_BWL_COUNT, val)
1056#define bfin_read_DMA19_CURR_BWL_COUNT() bfin_read32(DMA19_CURR_BWL_COUNT)
1057#define bfin_write_DMA19_CURR_BWL_COUNT(val) bfin_write32(DMA19_CURR_BWL_COUNT, val)
1058#define bfin_read_DMA19_BWM_COUNT() bfin_read32(DMA19_BWM_COUNT)
1059#define bfin_write_DMA19_BWM_COUNT(val) bfin_write32(DMA19_BWM_COUNT, val)
1060#define bfin_read_DMA19_CURR_BWM_COUNT() bfin_read32(DMA19_CURR_BWM_COUNT)
1061#define bfin_write_DMA19_CURR_BWM_COUNT(val) bfin_write32(DMA19_CURR_BWM_COUNT, val)
1062
1063/* DMA Channel 20 Registers */
1064
1065#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
1066#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
1067#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
1068#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
1069#define bfin_read_DMA20_CONFIG() bfin_read32(DMA20_CONFIG)
1070#define bfin_write_DMA20_CONFIG(val) bfin_write32(DMA20_CONFIG, val)
1071#define bfin_read_DMA20_X_COUNT() bfin_read32(DMA20_X_COUNT)
1072#define bfin_write_DMA20_X_COUNT(val) bfin_write32(DMA20_X_COUNT, val)
1073#define bfin_read_DMA20_X_MODIFY() bfin_read32(DMA20_X_MODIFY)
1074#define bfin_write_DMA20_X_MODIFY(val) bfin_write32(DMA20_X_MODIFY, val)
1075#define bfin_read_DMA20_Y_COUNT() bfin_read32(DMA20_Y_COUNT)
1076#define bfin_write_DMA20_Y_COUNT(val) bfin_write32(DMA20_Y_COUNT, val)
1077#define bfin_read_DMA20_Y_MODIFY() bfin_read32(DMA20_Y_MODIFY)
1078#define bfin_write_DMA20_Y_MODIFY(val) bfin_write32(DMA20_Y_MODIFY, val)
1079#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
1080#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
1081#define bfin_read_DMA20_PREV_DESC_PTR() bfin_read32(DMA20_PREV_DESC_PTR)
1082#define bfin_write_DMA20_PREV_DESC_PTR(val) bfin_write32(DMA20_PREV_DESC_PTR, val)
1083#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
1084#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
1085#define bfin_read_DMA20_IRQ_STATUS() bfin_read32(DMA20_IRQ_STATUS)
1086#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write32(DMA20_IRQ_STATUS, val)
1087#define bfin_read_DMA20_CURR_X_COUNT() bfin_read32(DMA20_CURR_X_COUNT)
1088#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write32(DMA20_CURR_X_COUNT, val)
1089#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read32(DMA20_CURR_Y_COUNT)
1090#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write32(DMA20_CURR_Y_COUNT, val)
1091#define bfin_read_DMA20_BWL_COUNT() bfin_read32(DMA20_BWL_COUNT)
1092#define bfin_write_DMA20_BWL_COUNT(val) bfin_write32(DMA20_BWL_COUNT, val)
1093#define bfin_read_DMA20_CURR_BWL_COUNT() bfin_read32(DMA20_CURR_BWL_COUNT)
1094#define bfin_write_DMA20_CURR_BWL_COUNT(val) bfin_write32(DMA20_CURR_BWL_COUNT, val)
1095#define bfin_read_DMA20_BWM_COUNT() bfin_read32(DMA20_BWM_COUNT)
1096#define bfin_write_DMA20_BWM_COUNT(val) bfin_write32(DMA20_BWM_COUNT, val)
1097#define bfin_read_DMA20_CURR_BWM_COUNT() bfin_read32(DMA20_CURR_BWM_COUNT)
1098#define bfin_write_DMA20_CURR_BWM_COUNT(val) bfin_write32(DMA20_CURR_BWM_COUNT, val)
1099
1100
1101/* MDMA Stream 0 Registers (DMA Channel 21 and 22) */
1102
1103#define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR)
1104#define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val)
1105#define bfin_read_MDMA0_DEST_CRC0_START_ADDR() bfin_read32(MDMA0_DEST_CRC0_START_ADDR)
1106#define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val)
1107#define bfin_read_MDMA0_DEST_CRC0_CONFIG() bfin_read32(MDMA0_DEST_CRC0_CONFIG)
1108#define bfin_write_MDMA0_DEST_CRC0_CONFIG(val) bfin_write32(MDMA0_DEST_CRC0_CONFIG, val)
1109#define bfin_read_MDMA0_DEST_CRC0_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_X_COUNT)
1110#define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val)
1111#define bfin_read_MDMA0_DEST_CRC0_X_MODIFY() bfin_read32(MDMA0_DEST_CRC0_X_MODIFY)
1112#define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val)
1113#define bfin_read_MDMA0_DEST_CRC0_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_Y_COUNT)
1114#define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val)
1115#define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY() bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY)
1116#define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val)
1117#define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR)
1118#define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val)
1119#define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR)
1120#define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val)
1121#define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR() bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR)
1122#define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val)
1123#define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS() bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS)
1124#define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val)
1125#define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT)
1126#define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val)
1127#define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT)
1128#define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val)
1129#define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR)
1130#define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val)
1131#define bfin_read_MDMA0_SRC_CRC0_START_ADDR() bfin_read32(MDMA0_SRC_CRC0_START_ADDR)
1132#define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val)
1133#define bfin_read_MDMA0_SRC_CRC0_CONFIG() bfin_read32(MDMA0_SRC_CRC0_CONFIG)
1134#define bfin_write_MDMA0_SRC_CRC0_CONFIG(val) bfin_write32(MDMA0_SRC_CRC0_CONFIG, val)
1135#define bfin_read_MDMA0_SRC_CRC0_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_X_COUNT)
1136#define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val)
1137#define bfin_read_MDMA0_SRC_CRC0_X_MODIFY() bfin_read32(MDMA0_SRC_CRC0_X_MODIFY)
1138#define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val)
1139#define bfin_read_MDMA0_SRC_CRC0_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_Y_COUNT)
1140#define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val)
1141#define bfin_read_MDMA0_SRC_CRC0_Y_MODIFY() bfin_read32(MDMA0_SRC_CRC0_Y_MODIFY)
1142#define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val)
1143#define bfin_read_MDMA0_SRC_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_CURR_DESC_PTR)
1144#define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val)
1145#define bfin_read_MDMA0_SRC_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_PREV_DESC_PTR)
1146#define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val)
1147#define bfin_read_MDMA0_SRC_CRC0_CURR_ADDR() bfin_read32(MDMA0_SRC_CRC0_CURR_ADDR)
1148#define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val)
1149#define bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS() bfin_read32(MDMA0_SRC_CRC0_IRQ_STATUS)
1150#define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val)
1151#define bfin_read_MDMA0_SRC_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_X_COUNT)
1152#define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val)
1153#define bfin_read_MDMA0_SRC_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_Y_COUNT)
1154#define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val)
1155
1156/* MDMA Stream 1 Registers (DMA Channel 23 and 24) */
1157
1158#define bfin_read_MDMA1_DEST_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_NEXT_DESC_PTR)
1159#define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val)
1160#define bfin_read_MDMA1_DEST_CRC1_START_ADDR() bfin_read32(MDMA1_DEST_CRC1_START_ADDR)
1161#define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val)
1162#define bfin_read_MDMA1_DEST_CRC1_CONFIG() bfin_read32(MDMA1_DEST_CRC1_CONFIG)
1163#define bfin_write_MDMA1_DEST_CRC1_CONFIG(val) bfin_write32(MDMA1_DEST_CRC1_CONFIG, val)
1164#define bfin_read_MDMA1_DEST_CRC1_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_X_COUNT)
1165#define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val)
1166#define bfin_read_MDMA1_DEST_CRC1_X_MODIFY() bfin_read32(MDMA1_DEST_CRC1_X_MODIFY)
1167#define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val)
1168#define bfin_read_MDMA1_DEST_CRC1_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_Y_COUNT)
1169#define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val)
1170#define bfin_read_MDMA1_DEST_CRC1_Y_MODIFY() bfin_read32(MDMA1_DEST_CRC1_Y_MODIFY)
1171#define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val)
1172#define bfin_read_MDMA1_DEST_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_CURR_DESC_PTR)
1173#define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val)
1174#define bfin_read_MDMA1_DEST_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_PREV_DESC_PTR)
1175#define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val)
1176#define bfin_read_MDMA1_DEST_CRC1_CURR_ADDR() bfin_read32(MDMA1_DEST_CRC1_CURR_ADDR)
1177#define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val)
1178#define bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS() bfin_read32(MDMA1_DEST_CRC1_IRQ_STATUS)
1179#define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val)
1180#define bfin_read_MDMA1_DEST_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_X_COUNT)
1181#define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val)
1182#define bfin_read_MDMA1_DEST_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_Y_COUNT)
1183#define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val)
1184#define bfin_read_MDMA1_SRC_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_NEXT_DESC_PTR)
1185#define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val)
1186#define bfin_read_MDMA1_SRC_CRC1_START_ADDR() bfin_read32(MDMA1_SRC_CRC1_START_ADDR)
1187#define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val)
1188#define bfin_read_MDMA1_SRC_CRC1_CONFIG() bfin_read32(MDMA1_SRC_CRC1_CONFIG)
1189#define bfin_write_MDMA1_SRC_CRC1_CONFIG(val) bfin_write32(MDMA1_SRC_CRC1_CONFIG, val)
1190#define bfin_read_MDMA1_SRC_CRC1_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_X_COUNT)
1191#define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val)
1192#define bfin_read_MDMA1_SRC_CRC1_X_MODIFY() bfin_read32(MDMA1_SRC_CRC1_X_MODIFY)
1193#define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val)
1194#define bfin_read_MDMA1_SRC_CRC1_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_Y_COUNT)
1195#define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val)
1196#define bfin_read_MDMA1_SRC_CRC1_Y_MODIFY() bfin_read32(MDMA1_SRC_CRC1_Y_MODIFY)
1197#define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val)
1198#define bfin_read_MDMA1_SRC_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_CURR_DESC_PTR)
1199#define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val)
1200#define bfin_read_MDMA1_SRC_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_PREV_DESC_PTR)
1201#define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val)
1202#define bfin_read_MDMA1_SRC_CRC1_CURR_ADDR() bfin_read32(MDMA1_SRC_CRC1_CURR_ADDR)
1203#define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val)
1204#define bfin_read_MDMA1_SRC_CRC1_IRQ_STATUS() bfin_read32(MDMA1_SRC_CRC1_IRQ_STATUS)
1205#define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val)
1206#define bfin_read_MDMA1_SRC_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_X_COUNT)
1207#define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val)
1208#define bfin_read_MDMA1_SRC_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_Y_COUNT)
1209#define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val)
1210
1211
1212/* MDMA Stream 2 Registers (DMA Channel 25 and 26) */
1213
1214#define bfin_read_MDMA2_DEST_NEXT_DESC_PTR() bfin_read32(MDMA2_DEST_NEXT_DESC_PTR)
1215#define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val)
1216#define bfin_read_MDMA2_DEST_START_ADDR() bfin_read32(MDMA2_DEST_START_ADDR)
1217#define bfin_write_MDMA2_DEST_START_ADDR(val) bfin_write32(MDMA2_DEST_START_ADDR, val)
1218#define bfin_read_MDMA2_DEST_CONFIG() bfin_read32(MDMA2_DEST_CONFIG)
1219#define bfin_write_MDMA2_DEST_CONFIG(val) bfin_write32(MDMA2_DEST_CONFIG, val)
1220#define bfin_read_MDMA2_DEST_X_COUNT() bfin_read32(MDMA2_DEST_X_COUNT)
1221#define bfin_write_MDMA2_DEST_X_COUNT(val) bfin_write32(MDMA2_DEST_X_COUNT, val)
1222#define bfin_read_MDMA2_DEST_X_MODIFY() bfin_read32(MDMA2_DEST_X_MODIFY)
1223#define bfin_write_MDMA2_DEST_X_MODIFY(val) bfin_write32(MDMA2_DEST_X_MODIFY, val)
1224#define bfin_read_MDMA2_DEST_Y_COUNT() bfin_read32(MDMA2_DEST_Y_COUNT)
1225#define bfin_write_MDMA2_DEST_Y_COUNT(val) bfin_write32(MDMA2_DEST_Y_COUNT, val)
1226#define bfin_read_MDMA2_DEST_Y_MODIFY() bfin_read32(MDMA2_DEST_Y_MODIFY)
1227#define bfin_write_MDMA2_DEST_Y_MODIFY(val) bfin_write32(MDMA2_DEST_Y_MODIFY, val)
1228#define bfin_read_MDMA2_DEST_CURR_DESC_PTR() bfin_read32(MDMA2_DEST_CURR_DESC_PTR)
1229#define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val)
1230#define bfin_read_MDMA2_DEST_PREV_DESC_PTR() bfin_read32(MDMA2_DEST_PREV_DESC_PTR)
1231#define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val)
1232#define bfin_read_MDMA2_DEST_CURR_ADDR() bfin_read32(MDMA2_DEST_CURR_ADDR)
1233#define bfin_write_MDMA2_DEST_CURR_ADDR(val) bfin_write32(MDMA2_DEST_CURR_ADDR, val)
1234#define bfin_read_MDMA2_DEST_IRQ_STATUS() bfin_read32(MDMA2_DEST_IRQ_STATUS)
1235#define bfin_write_MDMA2_DEST_IRQ_STATUS(val) bfin_write32(MDMA2_DEST_IRQ_STATUS, val)
1236#define bfin_read_MDMA2_DEST_CURR_X_COUNT() bfin_read32(MDMA2_DEST_CURR_X_COUNT)
1237#define bfin_write_MDMA2_DEST_CURR_X_COUNT(val) bfin_write32(MDMA2_DEST_CURR_X_COUNT, val)
1238#define bfin_read_MDMA2_DEST_CURR_Y_COUNT() bfin_read32(MDMA2_DEST_CURR_Y_COUNT)
1239#define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val)
1240#define bfin_read_MDMA2_SRC_NEXT_DESC_PTR() bfin_read32(MDMA2_SRC_NEXT_DESC_PTR)
1241#define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val)
1242#define bfin_read_MDMA2_SRC_START_ADDR() bfin_read32(MDMA2_SRC_START_ADDR)
1243#define bfin_write_MDMA2_SRC_START_ADDR(val) bfin_write32(MDMA2_SRC_START_ADDR, val)
1244#define bfin_read_MDMA2_SRC_CONFIG() bfin_read32(MDMA2_SRC_CONFIG)
1245#define bfin_write_MDMA2_SRC_CONFIG(val) bfin_write32(MDMA2_SRC_CONFIG, val)
1246#define bfin_read_MDMA2_SRC_X_COUNT() bfin_read32(MDMA2_SRC_X_COUNT)
1247#define bfin_write_MDMA2_SRC_X_COUNT(val) bfin_write32(MDMA2_SRC_X_COUNT, val)
1248#define bfin_read_MDMA2_SRC_X_MODIFY() bfin_read32(MDMA2_SRC_X_MODIFY)
1249#define bfin_write_MDMA2_SRC_X_MODIFY(val) bfin_write32(MDMA2_SRC_X_MODIFY, val)
1250#define bfin_read_MDMA2_SRC_Y_COUNT() bfin_read32(MDMA2_SRC_Y_COUNT)
1251#define bfin_write_MDMA2_SRC_Y_COUNT(val) bfin_write32(MDMA2_SRC_Y_COUNT, val)
1252#define bfin_read_MDMA2_SRC_Y_MODIFY() bfin_read32(MDMA2_SRC_Y_MODIFY)
1253#define bfin_write_MDMA2_SRC_Y_MODIFY(val) bfin_write32(MDMA2_SRC_Y_MODIFY, val)
1254#define bfin_read_MDMA2_SRC_CURR_DESC_PTR() bfin_read32(MDMA2_SRC_CURR_DESC_PTR)
1255#define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val)
1256#define bfin_read_MDMA2_SRC_PREV_DESC_PTR() bfin_read32(MDMA2_SRC_PREV_DESC_PTR)
1257#define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val)
1258#define bfin_read_MDMA2_SRC_CURR_ADDR() bfin_read32(MDMA2_SRC_CURR_ADDR)
1259#define bfin_write_MDMA2_SRC_CURR_ADDR(val) bfin_write32(MDMA2_SRC_CURR_ADDR, val)
1260#define bfin_read_MDMA2_SRC_IRQ_STATUS() bfin_read32(MDMA2_SRC_IRQ_STATUS)
1261#define bfin_write_MDMA2_SRC_IRQ_STATUS(val) bfin_write32(MDMA2_SRC_IRQ_STATUS, val)
1262#define bfin_read_MDMA2_SRC_CURR_X_COUNT() bfin_read32(MDMA2_SRC_CURR_X_COUNT)
1263#define bfin_write_MDMA2_SRC_CURR_X_COUNT(val) bfin_write32(MDMA2_SRC_CURR_X_COUNT, val)
1264#define bfin_read_MDMA2_SRC_CURR_Y_COUNT() bfin_read32(MDMA2_SRC_CURR_Y_COUNT)
1265#define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val)
1266
1267/* MDMA Stream 3 Registers (DMA Channel 27 and 28) */
1268
1269#define bfin_read_MDMA3_DEST_NEXT_DESC_PTR() bfin_read32(MDMA3_DEST_NEXT_DESC_PTR)
1270#define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val)
1271#define bfin_read_MDMA3_DEST_START_ADDR() bfin_read32(MDMA3_DEST_START_ADDR)
1272#define bfin_write_MDMA3_DEST_START_ADDR(val) bfin_write32(MDMA3_DEST_START_ADDR, val)
1273#define bfin_read_MDMA3_DEST_CONFIG() bfin_read32(MDMA3_DEST_CONFIG)
1274#define bfin_write_MDMA3_DEST_CONFIG(val) bfin_write32(MDMA3_DEST_CONFIG, val)
1275#define bfin_read_MDMA3_DEST_X_COUNT() bfin_read32(MDMA3_DEST_X_COUNT)
1276#define bfin_write_MDMA3_DEST_X_COUNT(val) bfin_write32(MDMA3_DEST_X_COUNT, val)
1277#define bfin_read_MDMA3_DEST_X_MODIFY() bfin_read32(MDMA3_DEST_X_MODIFY)
1278#define bfin_write_MDMA3_DEST_X_MODIFY(val) bfin_write32(MDMA3_DEST_X_MODIFY, val)
1279#define bfin_read_MDMA3_DEST_Y_COUNT() bfin_read32(MDMA3_DEST_Y_COUNT)
1280#define bfin_write_MDMA3_DEST_Y_COUNT(val) bfin_write32(MDMA3_DEST_Y_COUNT, val)
1281#define bfin_read_MDMA3_DEST_Y_MODIFY() bfin_read32(MDMA3_DEST_Y_MODIFY)
1282#define bfin_write_MDMA3_DEST_Y_MODIFY(val) bfin_write32(MDMA3_DEST_Y_MODIFY, val)
1283#define bfin_read_MDMA3_DEST_CURR_DESC_PTR() bfin_read32(MDMA3_DEST_CURR_DESC_PTR)
1284#define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val)
1285#define bfin_read_MDMA3_DEST_PREV_DESC_PTR() bfin_read32(MDMA3_DEST_PREV_DESC_PTR)
1286#define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val)
1287#define bfin_read_MDMA3_DEST_CURR_ADDR() bfin_read32(MDMA3_DEST_CURR_ADDR)
1288#define bfin_write_MDMA3_DEST_CURR_ADDR(val) bfin_write32(MDMA3_DEST_CURR_ADDR, val)
1289#define bfin_read_MDMA3_DEST_IRQ_STATUS() bfin_read32(MDMA3_DEST_IRQ_STATUS)
1290#define bfin_write_MDMA3_DEST_IRQ_STATUS(val) bfin_write32(MDMA3_DEST_IRQ_STATUS, val)
1291#define bfin_read_MDMA3_DEST_CURR_X_COUNT() bfin_read32(MDMA3_DEST_CURR_X_COUNT)
1292#define bfin_write_MDMA3_DEST_CURR_X_COUNT(val) bfin_write32(MDMA3_DEST_CURR_X_COUNT, val)
1293#define bfin_read_MDMA3_DEST_CURR_Y_COUNT() bfin_read32(MDMA3_DEST_CURR_Y_COUNT)
1294#define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val)
1295#define bfin_read_MDMA3_SRC_NEXT_DESC_PTR() bfin_read32(MDMA3_SRC_NEXT_DESC_PTR)
1296#define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val)
1297#define bfin_read_MDMA3_SRC_START_ADDR() bfin_read32(MDMA3_SRC_START_ADDR)
1298#define bfin_write_MDMA3_SRC_START_ADDR(val) bfin_write32(MDMA3_SRC_START_ADDR, val)
1299#define bfin_read_MDMA3_SRC_CONFIG() bfin_read32(MDMA3_SRC_CONFIG)
1300#define bfin_write_MDMA3_SRC_CONFIG(val) bfin_write32(MDMA3_SRC_CONFIG, val)
1301#define bfin_read_MDMA3_SRC_X_COUNT() bfin_read32(MDMA3_SRC_X_COUNT)
1302#define bfin_write_MDMA3_SRC_X_COUNT(val) bfin_write32(MDMA3_SRC_X_COUNT, val)
1303#define bfin_read_MDMA3_SRC_X_MODIFY() bfin_read32(MDMA3_SRC_X_MODIFY)
1304#define bfin_write_MDMA3_SRC_X_MODIFY(val) bfin_write32(MDMA3_SRC_X_MODIFY, val)
1305#define bfin_read_MDMA3_SRC_Y_COUNT() bfin_read32(MDMA3_SRC_Y_COUNT)
1306#define bfin_write_MDMA3_SRC_Y_COUNT(val) bfin_write32(MDMA3_SRC_Y_COUNT, val)
1307#define bfin_read_MDMA3_SRC_Y_MODIFY() bfin_read32(MDMA3_SRC_Y_MODIFY)
1308#define bfin_write_MDMA3_SRC_Y_MODIFY(val) bfin_write32(MDMA3_SRC_Y_MODIFY, val)
1309#define bfin_read_MDMA3_SRC_CURR_DESC_PTR() bfin_read32(MDMA3_SRC_CURR_DESC_PTR)
1310#define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val)
1311#define bfin_read_MDMA3_SRC_PREV_DESC_PTR() bfin_read32(MDMA3_SRC_PREV_DESC_PTR)
1312#define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val)
1313#define bfin_read_MDMA3_SRC_CURR_ADDR() bfin_read32(MDMA3_SRC_CURR_ADDR)
1314#define bfin_write_MDMA3_SRC_CURR_ADDR(val) bfin_write32(MDMA3_SRC_CURR_ADDR, val)
1315#define bfin_read_MDMA3_SRC_IRQ_STATUS() bfin_read32(MDMA3_SRC_IRQ_STATUS)
1316#define bfin_write_MDMA3_SRC_IRQ_STATUS(val) bfin_write32(MDMA3_SRC_IRQ_STATUS, val)
1317#define bfin_read_MDMA3_SRC_CURR_X_COUNT() bfin_read32(MDMA3_SRC_CURR_X_COUNT)
1318#define bfin_write_MDMA3_SRC_CURR_X_COUNT(val) bfin_write32(MDMA3_SRC_CURR_X_COUNT, val)
1319#define bfin_read_MDMA3_SRC_CURR_Y_COUNT() bfin_read32(MDMA3_SRC_CURR_Y_COUNT)
1320#define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val)
1321
1322
1323/* DMA Channel 29 Registers */
1324
1325#define bfin_read_DMA29_NEXT_DESC_PTR() bfin_read32(DMA29_NEXT_DESC_PTR)
1326#define bfin_write_DMA29_NEXT_DESC_PTR(val) bfin_write32(DMA29_NEXT_DESC_PTR, val)
1327#define bfin_read_DMA29_START_ADDR() bfin_read32(DMA29_START_ADDR)
1328#define bfin_write_DMA29_START_ADDR(val) bfin_write32(DMA29_START_ADDR, val)
1329#define bfin_read_DMA29_CONFIG() bfin_read32(DMA29_CONFIG)
1330#define bfin_write_DMA29_CONFIG(val) bfin_write32(DMA29_CONFIG, val)
1331#define bfin_read_DMA29_X_COUNT() bfin_read32(DMA29_X_COUNT)
1332#define bfin_write_DMA29_X_COUNT(val) bfin_write32(DMA29_X_COUNT, val)
1333#define bfin_read_DMA29_X_MODIFY() bfin_read32(DMA29_X_MODIFY)
1334#define bfin_write_DMA29_X_MODIFY(val) bfin_write32(DMA29_X_MODIFY, val)
1335#define bfin_read_DMA29_Y_COUNT() bfin_read32(DMA29_Y_COUNT)
1336#define bfin_write_DMA29_Y_COUNT(val) bfin_write32(DMA29_Y_COUNT, val)
1337#define bfin_read_DMA29_Y_MODIFY() bfin_read32(DMA29_Y_MODIFY)
1338#define bfin_write_DMA29_Y_MODIFY(val) bfin_write32(DMA29_Y_MODIFY, val)
1339#define bfin_read_DMA29_CURR_DESC_PTR() bfin_read32(DMA29_CURR_DESC_PTR)
1340#define bfin_write_DMA29_CURR_DESC_PTR(val) bfin_write32(DMA29_CURR_DESC_PTR, val)
1341#define bfin_read_DMA29_PREV_DESC_PTR() bfin_read32(DMA29_PREV_DESC_PTR)
1342#define bfin_write_DMA29_PREV_DESC_PTR(val) bfin_write32(DMA29_PREV_DESC_PTR, val)
1343#define bfin_read_DMA29_CURR_ADDR() bfin_read32(DMA29_CURR_ADDR)
1344#define bfin_write_DMA29_CURR_ADDR(val) bfin_write32(DMA29_CURR_ADDR, val)
1345#define bfin_read_DMA29_IRQ_STATUS() bfin_read32(DMA29_IRQ_STATUS)
1346#define bfin_write_DMA29_IRQ_STATUS(val) bfin_write32(DMA29_IRQ_STATUS, val)
1347#define bfin_read_DMA29_CURR_X_COUNT() bfin_read32(DMA29_CURR_X_COUNT)
1348#define bfin_write_DMA29_CURR_X_COUNT(val) bfin_write32(DMA29_CURR_X_COUNT, val)
1349#define bfin_read_DMA29_CURR_Y_COUNT() bfin_read32(DMA29_CURR_Y_COUNT)
1350#define bfin_write_DMA29_CURR_Y_COUNT(val) bfin_write32(DMA29_CURR_Y_COUNT, val)
1351#define bfin_read_DMA29_BWL_COUNT() bfin_read32(DMA29_BWL_COUNT)
1352#define bfin_write_DMA29_BWL_COUNT(val) bfin_write32(DMA29_BWL_COUNT, val)
1353#define bfin_read_DMA29_CURR_BWL_COUNT() bfin_read32(DMA29_CURR_BWL_COUNT)
1354#define bfin_write_DMA29_CURR_BWL_COUNT(val) bfin_write32(DMA29_CURR_BWL_COUNT, val)
1355#define bfin_read_DMA29_BWM_COUNT() bfin_read32(DMA29_BWM_COUNT)
1356#define bfin_write_DMA29_BWM_COUNT(val) bfin_write32(DMA29_BWM_COUNT, val)
1357#define bfin_read_DMA29_CURR_BWM_COUNT() bfin_read32(DMA29_CURR_BWM_COUNT)
1358#define bfin_write_DMA29_CURR_BWM_COUNT(val) bfin_write32(DMA29_CURR_BWM_COUNT, val)
1359
1360/* DMA Channel 30 Registers */
1361
1362#define bfin_read_DMA30_NEXT_DESC_PTR() bfin_read32(DMA30_NEXT_DESC_PTR)
1363#define bfin_write_DMA30_NEXT_DESC_PTR(val) bfin_write32(DMA30_NEXT_DESC_PTR, val)
1364#define bfin_read_DMA30_START_ADDR() bfin_read32(DMA30_START_ADDR)
1365#define bfin_write_DMA30_START_ADDR(val) bfin_write32(DMA30_START_ADDR, val)
1366#define bfin_read_DMA30_CONFIG() bfin_read32(DMA30_CONFIG)
1367#define bfin_write_DMA30_CONFIG(val) bfin_write32(DMA30_CONFIG, val)
1368#define bfin_read_DMA30_X_COUNT() bfin_read32(DMA30_X_COUNT)
1369#define bfin_write_DMA30_X_COUNT(val) bfin_write32(DMA30_X_COUNT, val)
1370#define bfin_read_DMA30_X_MODIFY() bfin_read32(DMA30_X_MODIFY)
1371#define bfin_write_DMA30_X_MODIFY(val) bfin_write32(DMA30_X_MODIFY, val)
1372#define bfin_read_DMA30_Y_COUNT() bfin_read32(DMA30_Y_COUNT)
1373#define bfin_write_DMA30_Y_COUNT(val) bfin_write32(DMA30_Y_COUNT, val)
1374#define bfin_read_DMA30_Y_MODIFY() bfin_read32(DMA30_Y_MODIFY)
1375#define bfin_write_DMA30_Y_MODIFY(val) bfin_write32(DMA30_Y_MODIFY, val)
1376#define bfin_read_DMA30_CURR_DESC_PTR() bfin_read32(DMA30_CURR_DESC_PTR)
1377#define bfin_write_DMA30_CURR_DESC_PTR(val) bfin_write32(DMA30_CURR_DESC_PTR, val)
1378#define bfin_read_DMA30_PREV_DESC_PTR() bfin_read32(DMA30_PREV_DESC_PTR)
1379#define bfin_write_DMA30_PREV_DESC_PTR(val) bfin_write32(DMA30_PREV_DESC_PTR, val)
1380#define bfin_read_DMA30_CURR_ADDR() bfin_read32(DMA30_CURR_ADDR)
1381#define bfin_write_DMA30_CURR_ADDR(val) bfin_write32(DMA30_CURR_ADDR, val)
1382#define bfin_read_DMA30_IRQ_STATUS() bfin_read32(DMA30_IRQ_STATUS)
1383#define bfin_write_DMA30_IRQ_STATUS(val) bfin_write32(DMA30_IRQ_STATUS, val)
1384#define bfin_read_DMA30_CURR_X_COUNT() bfin_read32(DMA30_CURR_X_COUNT)
1385#define bfin_write_DMA30_CURR_X_COUNT(val) bfin_write32(DMA30_CURR_X_COUNT, val)
1386#define bfin_read_DMA30_CURR_Y_COUNT() bfin_read32(DMA30_CURR_Y_COUNT)
1387#define bfin_write_DMA30_CURR_Y_COUNT(val) bfin_write32(DMA30_CURR_Y_COUNT, val)
1388#define bfin_read_DMA30_BWL_COUNT() bfin_read32(DMA30_BWL_COUNT)
1389#define bfin_write_DMA30_BWL_COUNT(val) bfin_write32(DMA30_BWL_COUNT, val)
1390#define bfin_read_DMA30_CURR_BWL_COUNT() bfin_read32(DMA30_CURR_BWL_COUNT)
1391#define bfin_write_DMA30_CURR_BWL_COUNT(val) bfin_write32(DMA30_CURR_BWL_COUNT, val)
1392#define bfin_read_DMA30_BWM_COUNT() bfin_read32(DMA30_BWM_COUNT)
1393#define bfin_write_DMA30_BWM_COUNT(val) bfin_write32(DMA30_BWM_COUNT, val)
1394#define bfin_read_DMA30_CURR_BWM_COUNT() bfin_read32(DMA30_CURR_BWM_COUNT)
1395#define bfin_write_DMA30_CURR_BWM_COUNT(val) bfin_write32(DMA30_CURR_BWM_COUNT, val)
1396
1397/* DMA Channel 31 Registers */
1398
1399#define bfin_read_DMA31_NEXT_DESC_PTR() bfin_read32(DMA31_NEXT_DESC_PTR)
1400#define bfin_write_DMA31_NEXT_DESC_PTR(val) bfin_write32(DMA31_NEXT_DESC_PTR, val)
1401#define bfin_read_DMA31_START_ADDR() bfin_read32(DMA31_START_ADDR)
1402#define bfin_write_DMA31_START_ADDR(val) bfin_write32(DMA31_START_ADDR, val)
1403#define bfin_read_DMA31_CONFIG() bfin_read32(DMA31_CONFIG)
1404#define bfin_write_DMA31_CONFIG(val) bfin_write32(DMA31_CONFIG, val)
1405#define bfin_read_DMA31_X_COUNT() bfin_read32(DMA31_X_COUNT)
1406#define bfin_write_DMA31_X_COUNT(val) bfin_write32(DMA31_X_COUNT, val)
1407#define bfin_read_DMA31_X_MODIFY() bfin_read32(DMA31_X_MODIFY)
1408#define bfin_write_DMA31_X_MODIFY(val) bfin_write32(DMA31_X_MODIFY, val)
1409#define bfin_read_DMA31_Y_COUNT() bfin_read32(DMA31_Y_COUNT)
1410#define bfin_write_DMA31_Y_COUNT(val) bfin_write32(DMA31_Y_COUNT, val)
1411#define bfin_read_DMA31_Y_MODIFY() bfin_read32(DMA31_Y_MODIFY)
1412#define bfin_write_DMA31_Y_MODIFY(val) bfin_write32(DMA31_Y_MODIFY, val)
1413#define bfin_read_DMA31_CURR_DESC_PTR() bfin_read32(DMA31_CURR_DESC_PTR)
1414#define bfin_write_DMA31_CURR_DESC_PTR(val) bfin_write32(DMA31_CURR_DESC_PTR, val)
1415#define bfin_read_DMA31_PREV_DESC_PTR() bfin_read32(DMA31_PREV_DESC_PTR)
1416#define bfin_write_DMA31_PREV_DESC_PTR(val) bfin_write32(DMA31_PREV_DESC_PTR, val)
1417#define bfin_read_DMA31_CURR_ADDR() bfin_read32(DMA31_CURR_ADDR)
1418#define bfin_write_DMA31_CURR_ADDR(val) bfin_write32(DMA31_CURR_ADDR, val)
1419#define bfin_read_DMA31_IRQ_STATUS() bfin_read32(DMA31_IRQ_STATUS)
1420#define bfin_write_DMA31_IRQ_STATUS(val) bfin_write32(DMA31_IRQ_STATUS, val)
1421#define bfin_read_DMA31_CURR_X_COUNT() bfin_read32(DMA31_CURR_X_COUNT)
1422#define bfin_write_DMA31_CURR_X_COUNT(val) bfin_write32(DMA31_CURR_X_COUNT, val)
1423#define bfin_read_DMA31_CURR_Y_COUNT() bfin_read32(DMA31_CURR_Y_COUNT)
1424#define bfin_write_DMA31_CURR_Y_COUNT(val) bfin_write32(DMA31_CURR_Y_COUNT, val)
1425#define bfin_read_DMA31_BWL_COUNT() bfin_read32(DMA31_BWL_COUNT)
1426#define bfin_write_DMA31_BWL_COUNT(val) bfin_write32(DMA31_BWL_COUNT, val)
1427#define bfin_read_DMA31_CURR_BWL_COUNT() bfin_read32(DMA31_CURR_BWL_COUNT)
1428#define bfin_write_DMA31_CURR_BWL_COUNT(val) bfin_write32(DMA31_CURR_BWL_COUNT, val)
1429#define bfin_read_DMA31_BWM_COUNT() bfin_read32(DMA31_BWM_COUNT)
1430#define bfin_write_DMA31_BWM_COUNT(val) bfin_write32(DMA31_BWM_COUNT, val)
1431#define bfin_read_DMA31_CURR_BWM_COUNT() bfin_read32(DMA31_CURR_BWM_COUNT)
1432#define bfin_write_DMA31_CURR_BWM_COUNT(val) bfin_write32(DMA31_CURR_BWM_COUNT, val)
1433
1434/* DMA Channel 32 Registers */
1435
1436#define bfin_read_DMA32_NEXT_DESC_PTR() bfin_read32(DMA32_NEXT_DESC_PTR)
1437#define bfin_write_DMA32_NEXT_DESC_PTR(val) bfin_write32(DMA32_NEXT_DESC_PTR, val)
1438#define bfin_read_DMA32_START_ADDR() bfin_read32(DMA32_START_ADDR)
1439#define bfin_write_DMA32_START_ADDR(val) bfin_write32(DMA32_START_ADDR, val)
1440#define bfin_read_DMA32_CONFIG() bfin_read32(DMA32_CONFIG)
1441#define bfin_write_DMA32_CONFIG(val) bfin_write32(DMA32_CONFIG, val)
1442#define bfin_read_DMA32_X_COUNT() bfin_read32(DMA32_X_COUNT)
1443#define bfin_write_DMA32_X_COUNT(val) bfin_write32(DMA32_X_COUNT, val)
1444#define bfin_read_DMA32_X_MODIFY() bfin_read32(DMA32_X_MODIFY)
1445#define bfin_write_DMA32_X_MODIFY(val) bfin_write32(DMA32_X_MODIFY, val)
1446#define bfin_read_DMA32_Y_COUNT() bfin_read32(DMA32_Y_COUNT)
1447#define bfin_write_DMA32_Y_COUNT(val) bfin_write32(DMA32_Y_COUNT, val)
1448#define bfin_read_DMA32_Y_MODIFY() bfin_read32(DMA32_Y_MODIFY)
1449#define bfin_write_DMA32_Y_MODIFY(val) bfin_write32(DMA32_Y_MODIFY, val)
1450#define bfin_read_DMA32_CURR_DESC_PTR() bfin_read32(DMA32_CURR_DESC_PTR)
1451#define bfin_write_DMA32_CURR_DESC_PTR(val) bfin_write32(DMA32_CURR_DESC_PTR, val)
1452#define bfin_read_DMA32_PREV_DESC_PTR() bfin_read32(DMA32_PREV_DESC_PTR)
1453#define bfin_write_DMA32_PREV_DESC_PTR(val) bfin_write32(DMA32_PREV_DESC_PTR, val)
1454#define bfin_read_DMA32_CURR_ADDR() bfin_read32(DMA32_CURR_ADDR)
1455#define bfin_write_DMA32_CURR_ADDR(val) bfin_write32(DMA32_CURR_ADDR, val)
1456#define bfin_read_DMA32_IRQ_STATUS() bfin_read32(DMA32_IRQ_STATUS)
1457#define bfin_write_DMA32_IRQ_STATUS(val) bfin_write32(DMA32_IRQ_STATUS, val)
1458#define bfin_read_DMA32_CURR_X_COUNT() bfin_read32(DMA32_CURR_X_COUNT)
1459#define bfin_write_DMA32_CURR_X_COUNT(val) bfin_write32(DMA32_CURR_X_COUNT, val)
1460#define bfin_read_DMA32_CURR_Y_COUNT() bfin_read32(DMA32_CURR_Y_COUNT)
1461#define bfin_write_DMA32_CURR_Y_COUNT(val) bfin_write32(DMA32_CURR_Y_COUNT, val)
1462#define bfin_read_DMA32_BWL_COUNT() bfin_read32(DMA32_BWL_COUNT)
1463#define bfin_write_DMA32_BWL_COUNT(val) bfin_write32(DMA32_BWL_COUNT, val)
1464#define bfin_read_DMA32_CURR_BWL_COUNT() bfin_read32(DMA32_CURR_BWL_COUNT)
1465#define bfin_write_DMA32_CURR_BWL_COUNT(val) bfin_write32(DMA32_CURR_BWL_COUNT, val)
1466#define bfin_read_DMA32_BWM_COUNT() bfin_read32(DMA32_BWM_COUNT)
1467#define bfin_write_DMA32_BWM_COUNT(val) bfin_write32(DMA32_BWM_COUNT, val)
1468#define bfin_read_DMA32_CURR_BWM_COUNT() bfin_read32(DMA32_CURR_BWM_COUNT)
1469#define bfin_write_DMA32_CURR_BWM_COUNT(val) bfin_write32(DMA32_CURR_BWM_COUNT, val)
1470
1471/* DMA Channel 33 Registers */
1472
1473#define bfin_read_DMA33_NEXT_DESC_PTR() bfin_read32(DMA33_NEXT_DESC_PTR)
1474#define bfin_write_DMA33_NEXT_DESC_PTR(val) bfin_write32(DMA33_NEXT_DESC_PTR, val)
1475#define bfin_read_DMA33_START_ADDR() bfin_read32(DMA33_START_ADDR)
1476#define bfin_write_DMA33_START_ADDR(val) bfin_write32(DMA33_START_ADDR, val)
1477#define bfin_read_DMA33_CONFIG() bfin_read32(DMA33_CONFIG)
1478#define bfin_write_DMA33_CONFIG(val) bfin_write32(DMA33_CONFIG, val)
1479#define bfin_read_DMA33_X_COUNT() bfin_read32(DMA33_X_COUNT)
1480#define bfin_write_DMA33_X_COUNT(val) bfin_write32(DMA33_X_COUNT, val)
1481#define bfin_read_DMA33_X_MODIFY() bfin_read32(DMA33_X_MODIFY)
1482#define bfin_write_DMA33_X_MODIFY(val) bfin_write32(DMA33_X_MODIFY, val)
1483#define bfin_read_DMA33_Y_COUNT() bfin_read32(DMA33_Y_COUNT)
1484#define bfin_write_DMA33_Y_COUNT(val) bfin_write32(DMA33_Y_COUNT, val)
1485#define bfin_read_DMA33_Y_MODIFY() bfin_read32(DMA33_Y_MODIFY)
1486#define bfin_write_DMA33_Y_MODIFY(val) bfin_write32(DMA33_Y_MODIFY, val)
1487#define bfin_read_DMA33_CURR_DESC_PTR() bfin_read32(DMA33_CURR_DESC_PTR)
1488#define bfin_write_DMA33_CURR_DESC_PTR(val) bfin_write32(DMA33_CURR_DESC_PTR, val)
1489#define bfin_read_DMA33_PREV_DESC_PTR() bfin_read32(DMA33_PREV_DESC_PTR)
1490#define bfin_write_DMA33_PREV_DESC_PTR(val) bfin_write32(DMA33_PREV_DESC_PTR, val)
1491#define bfin_read_DMA33_CURR_ADDR() bfin_read32(DMA33_CURR_ADDR)
1492#define bfin_write_DMA33_CURR_ADDR(val) bfin_write32(DMA33_CURR_ADDR, val)
1493#define bfin_read_DMA33_IRQ_STATUS() bfin_read32(DMA33_IRQ_STATUS)
1494#define bfin_write_DMA33_IRQ_STATUS(val) bfin_write32(DMA33_IRQ_STATUS, val)
1495#define bfin_read_DMA33_CURR_X_COUNT() bfin_read32(DMA33_CURR_X_COUNT)
1496#define bfin_write_DMA33_CURR_X_COUNT(val) bfin_write32(DMA33_CURR_X_COUNT, val)
1497#define bfin_read_DMA33_CURR_Y_COUNT() bfin_read32(DMA33_CURR_Y_COUNT)
1498#define bfin_write_DMA33_CURR_Y_COUNT(val) bfin_write32(DMA33_CURR_Y_COUNT, val)
1499#define bfin_read_DMA33_BWL_COUNT() bfin_read32(DMA33_BWL_COUNT)
1500#define bfin_write_DMA33_BWL_COUNT(val) bfin_write32(DMA33_BWL_COUNT, val)
1501#define bfin_read_DMA33_CURR_BWL_COUNT() bfin_read32(DMA33_CURR_BWL_COUNT)
1502#define bfin_write_DMA33_CURR_BWL_COUNT(val) bfin_write32(DMA33_CURR_BWL_COUNT, val)
1503#define bfin_read_DMA33_BWM_COUNT() bfin_read32(DMA33_BWM_COUNT)
1504#define bfin_write_DMA33_BWM_COUNT(val) bfin_write32(DMA33_BWM_COUNT, val)
1505#define bfin_read_DMA33_CURR_BWM_COUNT() bfin_read32(DMA33_CURR_BWM_COUNT)
1506#define bfin_write_DMA33_CURR_BWM_COUNT(val) bfin_write32(DMA33_CURR_BWM_COUNT, val)
1507
1508/* DMA Channel 34 Registers */
1509
1510#define bfin_read_DMA34_NEXT_DESC_PTR() bfin_read32(DMA34_NEXT_DESC_PTR)
1511#define bfin_write_DMA34_NEXT_DESC_PTR(val) bfin_write32(DMA34_NEXT_DESC_PTR, val)
1512#define bfin_read_DMA34_START_ADDR() bfin_read32(DMA34_START_ADDR)
1513#define bfin_write_DMA34_START_ADDR(val) bfin_write32(DMA34_START_ADDR, val)
1514#define bfin_read_DMA34_CONFIG() bfin_read32(DMA34_CONFIG)
1515#define bfin_write_DMA34_CONFIG(val) bfin_write32(DMA34_CONFIG, val)
1516#define bfin_read_DMA34_X_COUNT() bfin_read32(DMA34_X_COUNT)
1517#define bfin_write_DMA34_X_COUNT(val) bfin_write32(DMA34_X_COUNT, val)
1518#define bfin_read_DMA34_X_MODIFY() bfin_read32(DMA34_X_MODIFY)
1519#define bfin_write_DMA34_X_MODIFY(val) bfin_write32(DMA34_X_MODIFY, val)
1520#define bfin_read_DMA34_Y_COUNT() bfin_read32(DMA34_Y_COUNT)
1521#define bfin_write_DMA34_Y_COUNT(val) bfin_write32(DMA34_Y_COUNT, val)
1522#define bfin_read_DMA34_Y_MODIFY() bfin_read32(DMA34_Y_MODIFY)
1523#define bfin_write_DMA34_Y_MODIFY(val) bfin_write32(DMA34_Y_MODIFY, val)
1524#define bfin_read_DMA34_CURR_DESC_PTR() bfin_read32(DMA34_CURR_DESC_PTR)
1525#define bfin_write_DMA34_CURR_DESC_PTR(val) bfin_write32(DMA34_CURR_DESC_PTR, val)
1526#define bfin_read_DMA34_PREV_DESC_PTR() bfin_read32(DMA34_PREV_DESC_PTR)
1527#define bfin_write_DMA34_PREV_DESC_PTR(val) bfin_write32(DMA34_PREV_DESC_PTR, val)
1528#define bfin_read_DMA34_CURR_ADDR() bfin_read32(DMA34_CURR_ADDR)
1529#define bfin_write_DMA34_CURR_ADDR(val) bfin_write32(DMA34_CURR_ADDR, val)
1530#define bfin_read_DMA34_IRQ_STATUS() bfin_read32(DMA34_IRQ_STATUS)
1531#define bfin_write_DMA34_IRQ_STATUS(val) bfin_write32(DMA34_IRQ_STATUS, val)
1532#define bfin_read_DMA34_CURR_X_COUNT() bfin_read32(DMA34_CURR_X_COUNT)
1533#define bfin_write_DMA34_CURR_X_COUNT(val) bfin_write32(DMA34_CURR_X_COUNT, val)
1534#define bfin_read_DMA34_CURR_Y_COUNT() bfin_read32(DMA34_CURR_Y_COUNT)
1535#define bfin_write_DMA34_CURR_Y_COUNT(val) bfin_write32(DMA34_CURR_Y_COUNT, val)
1536#define bfin_read_DMA34_BWL_COUNT() bfin_read32(DMA34_BWL_COUNT)
1537#define bfin_write_DMA34_BWL_COUNT(val) bfin_write32(DMA34_BWL_COUNT, val)
1538#define bfin_read_DMA34_CURR_BWL_COUNT() bfin_read32(DMA34_CURR_BWL_COUNT)
1539#define bfin_write_DMA34_CURR_BWL_COUNT(val) bfin_write32(DMA34_CURR_BWL_COUNT, val)
1540#define bfin_read_DMA34_BWM_COUNT() bfin_read32(DMA34_BWM_COUNT)
1541#define bfin_write_DMA34_BWM_COUNT(val) bfin_write32(DMA34_BWM_COUNT, val)
1542#define bfin_read_DMA34_CURR_BWM_COUNT() bfin_read32(DMA34_CURR_BWM_COUNT)
1543#define bfin_write_DMA34_CURR_BWM_COUNT(val) bfin_write32(DMA34_CURR_BWM_COUNT, val)
1544
1545/* DMA Channel 35 Registers */
1546
1547#define bfin_read_DMA35_NEXT_DESC_PTR() bfin_read32(DMA35_NEXT_DESC_PTR)
1548#define bfin_write_DMA35_NEXT_DESC_PTR(val) bfin_write32(DMA35_NEXT_DESC_PTR, val)
1549#define bfin_read_DMA35_START_ADDR() bfin_read32(DMA35_START_ADDR)
1550#define bfin_write_DMA35_START_ADDR(val) bfin_write32(DMA35_START_ADDR, val)
1551#define bfin_read_DMA35_CONFIG() bfin_read32(DMA35_CONFIG)
1552#define bfin_write_DMA35_CONFIG(val) bfin_write32(DMA35_CONFIG, val)
1553#define bfin_read_DMA35_X_COUNT() bfin_read32(DMA35_X_COUNT)
1554#define bfin_write_DMA35_X_COUNT(val) bfin_write32(DMA35_X_COUNT, val)
1555#define bfin_read_DMA35_X_MODIFY() bfin_read32(DMA35_X_MODIFY)
1556#define bfin_write_DMA35_X_MODIFY(val) bfin_write32(DMA35_X_MODIFY, val)
1557#define bfin_read_DMA35_Y_COUNT() bfin_read32(DMA35_Y_COUNT)
1558#define bfin_write_DMA35_Y_COUNT(val) bfin_write32(DMA35_Y_COUNT, val)
1559#define bfin_read_DMA35_Y_MODIFY() bfin_read32(DMA35_Y_MODIFY)
1560#define bfin_write_DMA35_Y_MODIFY(val) bfin_write32(DMA35_Y_MODIFY, val)
1561#define bfin_read_DMA35_CURR_DESC_PTR() bfin_read32(DMA35_CURR_DESC_PTR)
1562#define bfin_write_DMA35_CURR_DESC_PTR(val) bfin_write32(DMA35_CURR_DESC_PTR, val)
1563#define bfin_read_DMA35_PREV_DESC_PTR() bfin_read32(DMA35_PREV_DESC_PTR)
1564#define bfin_write_DMA35_PREV_DESC_PTR(val) bfin_write32(DMA35_PREV_DESC_PTR, val)
1565#define bfin_read_DMA35_CURR_ADDR() bfin_read32(DMA35_CURR_ADDR)
1566#define bfin_write_DMA35_CURR_ADDR(val) bfin_write32(DMA35_CURR_ADDR, val)
1567#define bfin_read_DMA35_IRQ_STATUS() bfin_read32(DMA35_IRQ_STATUS)
1568#define bfin_write_DMA35_IRQ_STATUS(val) bfin_write32(DMA35_IRQ_STATUS, val)
1569#define bfin_read_DMA35_CURR_X_COUNT() bfin_read32(DMA35_CURR_X_COUNT)
1570#define bfin_write_DMA35_CURR_X_COUNT(val) bfin_write32(DMA35_CURR_X_COUNT, val)
1571#define bfin_read_DMA35_CURR_Y_COUNT() bfin_read32(DMA35_CURR_Y_COUNT)
1572#define bfin_write_DMA35_CURR_Y_COUNT(val) bfin_write32(DMA35_CURR_Y_COUNT, val)
1573#define bfin_read_DMA35_BWL_COUNT() bfin_read32(DMA35_BWL_COUNT)
1574#define bfin_write_DMA35_BWL_COUNT(val) bfin_write32(DMA35_BWL_COUNT, val)
1575#define bfin_read_DMA35_CURR_BWL_COUNT() bfin_read32(DMA35_CURR_BWL_COUNT)
1576#define bfin_write_DMA35_CURR_BWL_COUNT(val) bfin_write32(DMA35_CURR_BWL_COUNT, val)
1577#define bfin_read_DMA35_BWM_COUNT() bfin_read32(DMA35_BWM_COUNT)
1578#define bfin_write_DMA35_BWM_COUNT(val) bfin_write32(DMA35_BWM_COUNT, val)
1579#define bfin_read_DMA35_CURR_BWM_COUNT() bfin_read32(DMA35_CURR_BWM_COUNT)
1580#define bfin_write_DMA35_CURR_BWM_COUNT(val) bfin_write32(DMA35_CURR_BWM_COUNT, val)
1581
1582/* DMA Channel 36 Registers */
1583
1584#define bfin_read_DMA36_NEXT_DESC_PTR() bfin_read32(DMA36_NEXT_DESC_PTR)
1585#define bfin_write_DMA36_NEXT_DESC_PTR(val) bfin_write32(DMA36_NEXT_DESC_PTR, val)
1586#define bfin_read_DMA36_START_ADDR() bfin_read32(DMA36_START_ADDR)
1587#define bfin_write_DMA36_START_ADDR(val) bfin_write32(DMA36_START_ADDR, val)
1588#define bfin_read_DMA36_CONFIG() bfin_read32(DMA36_CONFIG)
1589#define bfin_write_DMA36_CONFIG(val) bfin_write32(DMA36_CONFIG, val)
1590#define bfin_read_DMA36_X_COUNT() bfin_read32(DMA36_X_COUNT)
1591#define bfin_write_DMA36_X_COUNT(val) bfin_write32(DMA36_X_COUNT, val)
1592#define bfin_read_DMA36_X_MODIFY() bfin_read32(DMA36_X_MODIFY)
1593#define bfin_write_DMA36_X_MODIFY(val) bfin_write32(DMA36_X_MODIFY, val)
1594#define bfin_read_DMA36_Y_COUNT() bfin_read32(DMA36_Y_COUNT)
1595#define bfin_write_DMA36_Y_COUNT(val) bfin_write32(DMA36_Y_COUNT, val)
1596#define bfin_read_DMA36_Y_MODIFY() bfin_read32(DMA36_Y_MODIFY)
1597#define bfin_write_DMA36_Y_MODIFY(val) bfin_write32(DMA36_Y_MODIFY, val)
1598#define bfin_read_DMA36_CURR_DESC_PTR() bfin_read32(DMA36_CURR_DESC_PTR)
1599#define bfin_write_DMA36_CURR_DESC_PTR(val) bfin_write32(DMA36_CURR_DESC_PTR, val)
1600#define bfin_read_DMA36_PREV_DESC_PTR() bfin_read32(DMA36_PREV_DESC_PTR)
1601#define bfin_write_DMA36_PREV_DESC_PTR(val) bfin_write32(DMA36_PREV_DESC_PTR, val)
1602#define bfin_read_DMA36_CURR_ADDR() bfin_read32(DMA36_CURR_ADDR)
1603#define bfin_write_DMA36_CURR_ADDR(val) bfin_write32(DMA36_CURR_ADDR, val)
1604#define bfin_read_DMA36_IRQ_STATUS() bfin_read32(DMA36_IRQ_STATUS)
1605#define bfin_write_DMA36_IRQ_STATUS(val) bfin_write32(DMA36_IRQ_STATUS, val)
1606#define bfin_read_DMA36_CURR_X_COUNT() bfin_read32(DMA36_CURR_X_COUNT)
1607#define bfin_write_DMA36_CURR_X_COUNT(val) bfin_write32(DMA36_CURR_X_COUNT, val)
1608#define bfin_read_DMA36_CURR_Y_COUNT() bfin_read32(DMA36_CURR_Y_COUNT)
1609#define bfin_write_DMA36_CURR_Y_COUNT(val) bfin_write32(DMA36_CURR_Y_COUNT, val)
1610#define bfin_read_DMA36_BWL_COUNT() bfin_read32(DMA36_BWL_COUNT)
1611#define bfin_write_DMA36_BWL_COUNT(val) bfin_write32(DMA36_BWL_COUNT, val)
1612#define bfin_read_DMA36_CURR_BWL_COUNT() bfin_read32(DMA36_CURR_BWL_COUNT)
1613#define bfin_write_DMA36_CURR_BWL_COUNT(val) bfin_write32(DMA36_CURR_BWL_COUNT, val)
1614#define bfin_read_DMA36_BWM_COUNT() bfin_read32(DMA36_BWM_COUNT)
1615#define bfin_write_DMA36_BWM_COUNT(val) bfin_write32(DMA36_BWM_COUNT, val)
1616#define bfin_read_DMA36_CURR_BWM_COUNT() bfin_read32(DMA36_CURR_BWM_COUNT)
1617#define bfin_write_DMA36_CURR_BWM_COUNT(val) bfin_write32(DMA36_CURR_BWM_COUNT, val)
1618
1619/* DMA Channel 37 Registers */
1620
1621#define bfin_read_DMA37_NEXT_DESC_PTR() bfin_read32(DMA37_NEXT_DESC_PTR)
1622#define bfin_write_DMA37_NEXT_DESC_PTR(val) bfin_write32(DMA37_NEXT_DESC_PTR, val)
1623#define bfin_read_DMA37_START_ADDR() bfin_read32(DMA37_START_ADDR)
1624#define bfin_write_DMA37_START_ADDR(val) bfin_write32(DMA37_START_ADDR, val)
1625#define bfin_read_DMA37_CONFIG() bfin_read32(DMA37_CONFIG)
1626#define bfin_write_DMA37_CONFIG(val) bfin_write32(DMA37_CONFIG, val)
1627#define bfin_read_DMA37_X_COUNT() bfin_read32(DMA37_X_COUNT)
1628#define bfin_write_DMA37_X_COUNT(val) bfin_write32(DMA37_X_COUNT, val)
1629#define bfin_read_DMA37_X_MODIFY() bfin_read32(DMA37_X_MODIFY)
1630#define bfin_write_DMA37_X_MODIFY(val) bfin_write32(DMA37_X_MODIFY, val)
1631#define bfin_read_DMA37_Y_COUNT() bfin_read32(DMA37_Y_COUNT)
1632#define bfin_write_DMA37_Y_COUNT(val) bfin_write32(DMA37_Y_COUNT, val)
1633#define bfin_read_DMA37_Y_MODIFY() bfin_read32(DMA37_Y_MODIFY)
1634#define bfin_write_DMA37_Y_MODIFY(val) bfin_write32(DMA37_Y_MODIFY, val)
1635#define bfin_read_DMA37_CURR_DESC_PTR() bfin_read32(DMA37_CURR_DESC_PTR)
1636#define bfin_write_DMA37_CURR_DESC_PTR(val) bfin_write32(DMA37_CURR_DESC_PTR, val)
1637#define bfin_read_DMA37_PREV_DESC_PTR() bfin_read32(DMA37_PREV_DESC_PTR)
1638#define bfin_write_DMA37_PREV_DESC_PTR(val) bfin_write32(DMA37_PREV_DESC_PTR, val)
1639#define bfin_read_DMA37_CURR_ADDR() bfin_read32(DMA37_CURR_ADDR)
1640#define bfin_write_DMA37_CURR_ADDR(val) bfin_write32(DMA37_CURR_ADDR, val)
1641#define bfin_read_DMA37_IRQ_STATUS() bfin_read32(DMA37_IRQ_STATUS)
1642#define bfin_write_DMA37_IRQ_STATUS(val) bfin_write32(DMA37_IRQ_STATUS, val)
1643#define bfin_read_DMA37_CURR_X_COUNT() bfin_read32(DMA37_CURR_X_COUNT)
1644#define bfin_write_DMA37_CURR_X_COUNT(val) bfin_write32(DMA37_CURR_X_COUNT, val)
1645#define bfin_read_DMA37_CURR_Y_COUNT() bfin_read32(DMA37_CURR_Y_COUNT)
1646#define bfin_write_DMA37_CURR_Y_COUNT(val) bfin_write32(DMA37_CURR_Y_COUNT, val)
1647#define bfin_read_DMA37_BWL_COUNT() bfin_read32(DMA37_BWL_COUNT)
1648#define bfin_write_DMA37_BWL_COUNT(val) bfin_write32(DMA37_BWL_COUNT, val)
1649#define bfin_read_DMA37_CURR_BWL_COUNT() bfin_read32(DMA37_CURR_BWL_COUNT)
1650#define bfin_write_DMA37_CURR_BWL_COUNT(val) bfin_write32(DMA37_CURR_BWL_COUNT, val)
1651#define bfin_read_DMA37_BWM_COUNT() bfin_read32(DMA37_BWM_COUNT)
1652#define bfin_write_DMA37_BWM_COUNT(val) bfin_write32(DMA37_BWM_COUNT, val)
1653#define bfin_read_DMA37_CURR_BWM_COUNT() bfin_read32(DMA37_CURR_BWM_COUNT)
1654#define bfin_write_DMA37_CURR_BWM_COUNT(val) bfin_write32(DMA37_CURR_BWM_COUNT, val)
1655
1656/* DMA Channel 38 Registers */
1657
1658#define bfin_read_DMA38_NEXT_DESC_PTR() bfin_read32(DMA38_NEXT_DESC_PTR)
1659#define bfin_write_DMA38_NEXT_DESC_PTR(val) bfin_write32(DMA38_NEXT_DESC_PTR, val)
1660#define bfin_read_DMA38_START_ADDR() bfin_read32(DMA38_START_ADDR)
1661#define bfin_write_DMA38_START_ADDR(val) bfin_write32(DMA38_START_ADDR, val)
1662#define bfin_read_DMA38_CONFIG() bfin_read32(DMA38_CONFIG)
1663#define bfin_write_DMA38_CONFIG(val) bfin_write32(DMA38_CONFIG, val)
1664#define bfin_read_DMA38_X_COUNT() bfin_read32(DMA38_X_COUNT)
1665#define bfin_write_DMA38_X_COUNT(val) bfin_write32(DMA38_X_COUNT, val)
1666#define bfin_read_DMA38_X_MODIFY() bfin_read32(DMA38_X_MODIFY)
1667#define bfin_write_DMA38_X_MODIFY(val) bfin_write32(DMA38_X_MODIFY, val)
1668#define bfin_read_DMA38_Y_COUNT() bfin_read32(DMA38_Y_COUNT)
1669#define bfin_write_DMA38_Y_COUNT(val) bfin_write32(DMA38_Y_COUNT, val)
1670#define bfin_read_DMA38_Y_MODIFY() bfin_read32(DMA38_Y_MODIFY)
1671#define bfin_write_DMA38_Y_MODIFY(val) bfin_write32(DMA38_Y_MODIFY, val)
1672#define bfin_read_DMA38_CURR_DESC_PTR() bfin_read32(DMA38_CURR_DESC_PTR)
1673#define bfin_write_DMA38_CURR_DESC_PTR(val) bfin_write32(DMA38_CURR_DESC_PTR, val)
1674#define bfin_read_DMA38_PREV_DESC_PTR() bfin_read32(DMA38_PREV_DESC_PTR)
1675#define bfin_write_DMA38_PREV_DESC_PTR(val) bfin_write32(DMA38_PREV_DESC_PTR, val)
1676#define bfin_read_DMA38_CURR_ADDR() bfin_read32(DMA38_CURR_ADDR)
1677#define bfin_write_DMA38_CURR_ADDR(val) bfin_write32(DMA38_CURR_ADDR, val)
1678#define bfin_read_DMA38_IRQ_STATUS() bfin_read32(DMA38_IRQ_STATUS)
1679#define bfin_write_DMA38_IRQ_STATUS(val) bfin_write32(DMA38_IRQ_STATUS, val)
1680#define bfin_read_DMA38_CURR_X_COUNT() bfin_read32(DMA38_CURR_X_COUNT)
1681#define bfin_write_DMA38_CURR_X_COUNT(val) bfin_write32(DMA38_CURR_X_COUNT, val)
1682#define bfin_read_DMA38_CURR_Y_COUNT() bfin_read32(DMA38_CURR_Y_COUNT)
1683#define bfin_write_DMA38_CURR_Y_COUNT(val) bfin_write32(DMA38_CURR_Y_COUNT, val)
1684#define bfin_read_DMA38_BWL_COUNT() bfin_read32(DMA38_BWL_COUNT)
1685#define bfin_write_DMA38_BWL_COUNT(val) bfin_write32(DMA38_BWL_COUNT, val)
1686#define bfin_read_DMA38_CURR_BWL_COUNT() bfin_read32(DMA38_CURR_BWL_COUNT)
1687#define bfin_write_DMA38_CURR_BWL_COUNT(val) bfin_write32(DMA38_CURR_BWL_COUNT, val)
1688#define bfin_read_DMA38_BWM_COUNT() bfin_read32(DMA38_BWM_COUNT)
1689#define bfin_write_DMA38_BWM_COUNT(val) bfin_write32(DMA38_BWM_COUNT, val)
1690#define bfin_read_DMA38_CURR_BWM_COUNT() bfin_read32(DMA38_CURR_BWM_COUNT)
1691#define bfin_write_DMA38_CURR_BWM_COUNT(val) bfin_write32(DMA38_CURR_BWM_COUNT, val)
1692
1693/* DMA Channel 39 Registers */
1694
1695#define bfin_read_DMA39_NEXT_DESC_PTR() bfin_read32(DMA39_NEXT_DESC_PTR)
1696#define bfin_write_DMA39_NEXT_DESC_PTR(val) bfin_write32(DMA39_NEXT_DESC_PTR, val)
1697#define bfin_read_DMA39_START_ADDR() bfin_read32(DMA39_START_ADDR)
1698#define bfin_write_DMA39_START_ADDR(val) bfin_write32(DMA39_START_ADDR, val)
1699#define bfin_read_DMA39_CONFIG() bfin_read32(DMA39_CONFIG)
1700#define bfin_write_DMA39_CONFIG(val) bfin_write32(DMA39_CONFIG, val)
1701#define bfin_read_DMA39_X_COUNT() bfin_read32(DMA39_X_COUNT)
1702#define bfin_write_DMA39_X_COUNT(val) bfin_write32(DMA39_X_COUNT, val)
1703#define bfin_read_DMA39_X_MODIFY() bfin_read32(DMA39_X_MODIFY)
1704#define bfin_write_DMA39_X_MODIFY(val) bfin_write32(DMA39_X_MODIFY, val)
1705#define bfin_read_DMA39_Y_COUNT() bfin_read32(DMA39_Y_COUNT)
1706#define bfin_write_DMA39_Y_COUNT(val) bfin_write32(DMA39_Y_COUNT, val)
1707#define bfin_read_DMA39_Y_MODIFY() bfin_read32(DMA39_Y_MODIFY)
1708#define bfin_write_DMA39_Y_MODIFY(val) bfin_write32(DMA39_Y_MODIFY, val)
1709#define bfin_read_DMA39_CURR_DESC_PTR() bfin_read32(DMA39_CURR_DESC_PTR)
1710#define bfin_write_DMA39_CURR_DESC_PTR(val) bfin_write32(DMA39_CURR_DESC_PTR, val)
1711#define bfin_read_DMA39_PREV_DESC_PTR() bfin_read32(DMA39_PREV_DESC_PTR)
1712#define bfin_write_DMA39_PREV_DESC_PTR(val) bfin_write32(DMA39_PREV_DESC_PTR, val)
1713#define bfin_read_DMA39_CURR_ADDR() bfin_read32(DMA39_CURR_ADDR)
1714#define bfin_write_DMA39_CURR_ADDR(val) bfin_write32(DMA39_CURR_ADDR, val)
1715#define bfin_read_DMA39_IRQ_STATUS() bfin_read32(DMA39_IRQ_STATUS)
1716#define bfin_write_DMA39_IRQ_STATUS(val) bfin_write32(DMA39_IRQ_STATUS, val)
1717#define bfin_read_DMA39_CURR_X_COUNT() bfin_read32(DMA39_CURR_X_COUNT)
1718#define bfin_write_DMA39_CURR_X_COUNT(val) bfin_write32(DMA39_CURR_X_COUNT, val)
1719#define bfin_read_DMA39_CURR_Y_COUNT() bfin_read32(DMA39_CURR_Y_COUNT)
1720#define bfin_write_DMA39_CURR_Y_COUNT(val) bfin_write32(DMA39_CURR_Y_COUNT, val)
1721#define bfin_read_DMA39_BWL_COUNT() bfin_read32(DMA39_BWL_COUNT)
1722#define bfin_write_DMA39_BWL_COUNT(val) bfin_write32(DMA39_BWL_COUNT, val)
1723#define bfin_read_DMA39_CURR_BWL_COUNT() bfin_read32(DMA39_CURR_BWL_COUNT)
1724#define bfin_write_DMA39_CURR_BWL_COUNT(val) bfin_write32(DMA39_CURR_BWL_COUNT, val)
1725#define bfin_read_DMA39_BWM_COUNT() bfin_read32(DMA39_BWM_COUNT)
1726#define bfin_write_DMA39_BWM_COUNT(val) bfin_write32(DMA39_BWM_COUNT, val)
1727#define bfin_read_DMA39_CURR_BWM_COUNT() bfin_read32(DMA39_CURR_BWM_COUNT)
1728#define bfin_write_DMA39_CURR_BWM_COUNT(val) bfin_write32(DMA39_CURR_BWM_COUNT, val)
1729
1730/* DMA Channel 40 Registers */
1731
1732#define bfin_read_DMA40_NEXT_DESC_PTR() bfin_read32(DMA40_NEXT_DESC_PTR)
1733#define bfin_write_DMA40_NEXT_DESC_PTR(val) bfin_write32(DMA40_NEXT_DESC_PTR, val)
1734#define bfin_read_DMA40_START_ADDR() bfin_read32(DMA40_START_ADDR)
1735#define bfin_write_DMA40_START_ADDR(val) bfin_write32(DMA40_START_ADDR, val)
1736#define bfin_read_DMA40_CONFIG() bfin_read32(DMA40_CONFIG)
1737#define bfin_write_DMA40_CONFIG(val) bfin_write32(DMA40_CONFIG, val)
1738#define bfin_read_DMA40_X_COUNT() bfin_read32(DMA40_X_COUNT)
1739#define bfin_write_DMA40_X_COUNT(val) bfin_write32(DMA40_X_COUNT, val)
1740#define bfin_read_DMA40_X_MODIFY() bfin_read32(DMA40_X_MODIFY)
1741#define bfin_write_DMA40_X_MODIFY(val) bfin_write32(DMA40_X_MODIFY, val)
1742#define bfin_read_DMA40_Y_COUNT() bfin_read32(DMA40_Y_COUNT)
1743#define bfin_write_DMA40_Y_COUNT(val) bfin_write32(DMA40_Y_COUNT, val)
1744#define bfin_read_DMA40_Y_MODIFY() bfin_read32(DMA40_Y_MODIFY)
1745#define bfin_write_DMA40_Y_MODIFY(val) bfin_write32(DMA40_Y_MODIFY, val)
1746#define bfin_read_DMA40_CURR_DESC_PTR() bfin_read32(DMA40_CURR_DESC_PTR)
1747#define bfin_write_DMA40_CURR_DESC_PTR(val) bfin_write32(DMA40_CURR_DESC_PTR, val)
1748#define bfin_read_DMA40_PREV_DESC_PTR() bfin_read32(DMA40_PREV_DESC_PTR)
1749#define bfin_write_DMA40_PREV_DESC_PTR(val) bfin_write32(DMA40_PREV_DESC_PTR, val)
1750#define bfin_read_DMA40_CURR_ADDR() bfin_read32(DMA40_CURR_ADDR)
1751#define bfin_write_DMA40_CURR_ADDR(val) bfin_write32(DMA40_CURR_ADDR, val)
1752#define bfin_read_DMA40_IRQ_STATUS() bfin_read32(DMA40_IRQ_STATUS)
1753#define bfin_write_DMA40_IRQ_STATUS(val) bfin_write32(DMA40_IRQ_STATUS, val)
1754#define bfin_read_DMA40_CURR_X_COUNT() bfin_read32(DMA40_CURR_X_COUNT)
1755#define bfin_write_DMA40_CURR_X_COUNT(val) bfin_write32(DMA40_CURR_X_COUNT, val)
1756#define bfin_read_DMA40_CURR_Y_COUNT() bfin_read32(DMA40_CURR_Y_COUNT)
1757#define bfin_write_DMA40_CURR_Y_COUNT(val) bfin_write32(DMA40_CURR_Y_COUNT, val)
1758#define bfin_read_DMA40_BWL_COUNT() bfin_read32(DMA40_BWL_COUNT)
1759#define bfin_write_DMA40_BWL_COUNT(val) bfin_write32(DMA40_BWL_COUNT, val)
1760#define bfin_read_DMA40_CURR_BWL_COUNT() bfin_read32(DMA40_CURR_BWL_COUNT)
1761#define bfin_write_DMA40_CURR_BWL_COUNT(val) bfin_write32(DMA40_CURR_BWL_COUNT, val)
1762#define bfin_read_DMA40_BWM_COUNT() bfin_read32(DMA40_BWM_COUNT)
1763#define bfin_write_DMA40_BWM_COUNT(val) bfin_write32(DMA40_BWM_COUNT, val)
1764#define bfin_read_DMA40_CURR_BWM_COUNT() bfin_read32(DMA40_CURR_BWM_COUNT)
1765#define bfin_write_DMA40_CURR_BWM_COUNT(val) bfin_write32(DMA40_CURR_BWM_COUNT, val)
1766
1767/* DMA Channel 41 Registers */
1768
1769#define bfin_read_DMA41_NEXT_DESC_PTR() bfin_read32(DMA41_NEXT_DESC_PTR)
1770#define bfin_write_DMA41_NEXT_DESC_PTR(val) bfin_write32(DMA41_NEXT_DESC_PTR, val)
1771#define bfin_read_DMA41_START_ADDR() bfin_read32(DMA41_START_ADDR)
1772#define bfin_write_DMA41_START_ADDR(val) bfin_write32(DMA41_START_ADDR, val)
1773#define bfin_read_DMA41_CONFIG() bfin_read32(DMA41_CONFIG)
1774#define bfin_write_DMA41_CONFIG(val) bfin_write32(DMA41_CONFIG, val)
1775#define bfin_read_DMA41_X_COUNT() bfin_read32(DMA41_X_COUNT)
1776#define bfin_write_DMA41_X_COUNT(val) bfin_write32(DMA41_X_COUNT, val)
1777#define bfin_read_DMA41_X_MODIFY() bfin_read32(DMA41_X_MODIFY)
1778#define bfin_write_DMA41_X_MODIFY(val) bfin_write32(DMA41_X_MODIFY, val)
1779#define bfin_read_DMA41_Y_COUNT() bfin_read32(DMA41_Y_COUNT)
1780#define bfin_write_DMA41_Y_COUNT(val) bfin_write32(DMA41_Y_COUNT, val)
1781#define bfin_read_DMA41_Y_MODIFY() bfin_read32(DMA41_Y_MODIFY)
1782#define bfin_write_DMA41_Y_MODIFY(val) bfin_write32(DMA41_Y_MODIFY, val)
1783#define bfin_read_DMA41_CURR_DESC_PTR() bfin_read32(DMA41_CURR_DESC_PTR)
1784#define bfin_write_DMA41_CURR_DESC_PTR(val) bfin_write32(DMA41_CURR_DESC_PTR, val)
1785#define bfin_read_DMA41_PREV_DESC_PTR() bfin_read32(DMA41_PREV_DESC_PTR)
1786#define bfin_write_DMA41_PREV_DESC_PTR(val) bfin_write32(DMA41_PREV_DESC_PTR, val)
1787#define bfin_read_DMA41_CURR_ADDR() bfin_read32(DMA41_CURR_ADDR)
1788#define bfin_write_DMA41_CURR_ADDR(val) bfin_write32(DMA41_CURR_ADDR, val)
1789#define bfin_read_DMA41_IRQ_STATUS() bfin_read32(DMA41_IRQ_STATUS)
1790#define bfin_write_DMA41_IRQ_STATUS(val) bfin_write32(DMA41_IRQ_STATUS, val)
1791#define bfin_read_DMA41_CURR_X_COUNT() bfin_read32(DMA41_CURR_X_COUNT)
1792#define bfin_write_DMA41_CURR_X_COUNT(val) bfin_write32(DMA41_CURR_X_COUNT, val)
1793#define bfin_read_DMA41_CURR_Y_COUNT() bfin_read32(DMA41_CURR_Y_COUNT)
1794#define bfin_write_DMA41_CURR_Y_COUNT(val) bfin_write32(DMA41_CURR_Y_COUNT, val)
1795#define bfin_read_DMA41_BWL_COUNT() bfin_read32(DMA41_BWL_COUNT)
1796#define bfin_write_DMA41_BWL_COUNT(val) bfin_write32(DMA41_BWL_COUNT, val)
1797#define bfin_read_DMA41_CURR_BWL_COUNT() bfin_read32(DMA41_CURR_BWL_COUNT)
1798#define bfin_write_DMA41_CURR_BWL_COUNT(val) bfin_write32(DMA41_CURR_BWL_COUNT, val)
1799#define bfin_read_DMA41_BWM_COUNT() bfin_read32(DMA41_BWM_COUNT)
1800#define bfin_write_DMA41_BWM_COUNT(val) bfin_write32(DMA41_BWM_COUNT, val)
1801#define bfin_read_DMA41_CURR_BWM_COUNT() bfin_read32(DMA41_CURR_BWM_COUNT)
1802#define bfin_write_DMA41_CURR_BWM_COUNT(val) bfin_write32(DMA41_CURR_BWM_COUNT, val)
1803
1804/* DMA Channel 42 Registers */
1805
1806#define bfin_read_DMA42_NEXT_DESC_PTR() bfin_read32(DMA42_NEXT_DESC_PTR)
1807#define bfin_write_DMA42_NEXT_DESC_PTR(val) bfin_write32(DMA42_NEXT_DESC_PTR, val)
1808#define bfin_read_DMA42_START_ADDR() bfin_read32(DMA42_START_ADDR)
1809#define bfin_write_DMA42_START_ADDR(val) bfin_write32(DMA42_START_ADDR, val)
1810#define bfin_read_DMA42_CONFIG() bfin_read32(DMA42_CONFIG)
1811#define bfin_write_DMA42_CONFIG(val) bfin_write32(DMA42_CONFIG, val)
1812#define bfin_read_DMA42_X_COUNT() bfin_read32(DMA42_X_COUNT)
1813#define bfin_write_DMA42_X_COUNT(val) bfin_write32(DMA42_X_COUNT, val)
1814#define bfin_read_DMA42_X_MODIFY() bfin_read32(DMA42_X_MODIFY)
1815#define bfin_write_DMA42_X_MODIFY(val) bfin_write32(DMA42_X_MODIFY, val)
1816#define bfin_read_DMA42_Y_COUNT() bfin_read32(DMA42_Y_COUNT)
1817#define bfin_write_DMA42_Y_COUNT(val) bfin_write32(DMA42_Y_COUNT, val)
1818#define bfin_read_DMA42_Y_MODIFY() bfin_read32(DMA42_Y_MODIFY)
1819#define bfin_write_DMA42_Y_MODIFY(val) bfin_write32(DMA42_Y_MODIFY, val)
1820#define bfin_read_DMA42_CURR_DESC_PTR() bfin_read32(DMA42_CURR_DESC_PTR)
1821#define bfin_write_DMA42_CURR_DESC_PTR(val) bfin_write32(DMA42_CURR_DESC_PTR, val)
1822#define bfin_read_DMA42_PREV_DESC_PTR() bfin_read32(DMA42_PREV_DESC_PTR)
1823#define bfin_write_DMA42_PREV_DESC_PTR(val) bfin_write32(DMA42_PREV_DESC_PTR, val)
1824#define bfin_read_DMA42_CURR_ADDR() bfin_read32(DMA42_CURR_ADDR)
1825#define bfin_write_DMA42_CURR_ADDR(val) bfin_write32(DMA42_CURR_ADDR, val)
1826#define bfin_read_DMA42_IRQ_STATUS() bfin_read32(DMA42_IRQ_STATUS)
1827#define bfin_write_DMA42_IRQ_STATUS(val) bfin_write32(DMA42_IRQ_STATUS, val)
1828#define bfin_read_DMA42_CURR_X_COUNT() bfin_read32(DMA42_CURR_X_COUNT)
1829#define bfin_write_DMA42_CURR_X_COUNT(val) bfin_write32(DMA42_CURR_X_COUNT, val)
1830#define bfin_read_DMA42_CURR_Y_COUNT() bfin_read32(DMA42_CURR_Y_COUNT)
1831#define bfin_write_DMA42_CURR_Y_COUNT(val) bfin_write32(DMA42_CURR_Y_COUNT, val)
1832#define bfin_read_DMA42_BWL_COUNT() bfin_read32(DMA42_BWL_COUNT)
1833#define bfin_write_DMA42_BWL_COUNT(val) bfin_write32(DMA42_BWL_COUNT, val)
1834#define bfin_read_DMA42_CURR_BWL_COUNT() bfin_read32(DMA42_CURR_BWL_COUNT)
1835#define bfin_write_DMA42_CURR_BWL_COUNT(val) bfin_write32(DMA42_CURR_BWL_COUNT, val)
1836#define bfin_read_DMA42_BWM_COUNT() bfin_read32(DMA42_BWM_COUNT)
1837#define bfin_write_DMA42_BWM_COUNT(val) bfin_write32(DMA42_BWM_COUNT, val)
1838#define bfin_read_DMA42_CURR_BWM_COUNT() bfin_read32(DMA42_CURR_BWM_COUNT)
1839#define bfin_write_DMA42_CURR_BWM_COUNT(val) bfin_write32(DMA42_CURR_BWM_COUNT, val)
1840
1841/* DMA Channel 43 Registers */
1842
1843#define bfin_read_DMA43_NEXT_DESC_PTR() bfin_read32(DMA43_NEXT_DESC_PTR)
1844#define bfin_write_DMA43_NEXT_DESC_PTR(val) bfin_write32(DMA43_NEXT_DESC_PTR, val)
1845#define bfin_read_DMA43_START_ADDR() bfin_read32(DMA43_START_ADDR)
1846#define bfin_write_DMA43_START_ADDR(val) bfin_write32(DMA43_START_ADDR, val)
1847#define bfin_read_DMA43_CONFIG() bfin_read32(DMA43_CONFIG)
1848#define bfin_write_DMA43_CONFIG(val) bfin_write32(DMA43_CONFIG, val)
1849#define bfin_read_DMA43_X_COUNT() bfin_read32(DMA43_X_COUNT)
1850#define bfin_write_DMA43_X_COUNT(val) bfin_write32(DMA43_X_COUNT, val)
1851#define bfin_read_DMA43_X_MODIFY() bfin_read32(DMA43_X_MODIFY)
1852#define bfin_write_DMA43_X_MODIFY(val) bfin_write32(DMA43_X_MODIFY, val)
1853#define bfin_read_DMA43_Y_COUNT() bfin_read32(DMA43_Y_COUNT)
1854#define bfin_write_DMA43_Y_COUNT(val) bfin_write32(DMA43_Y_COUNT, val)
1855#define bfin_read_DMA43_Y_MODIFY() bfin_read32(DMA43_Y_MODIFY)
1856#define bfin_write_DMA43_Y_MODIFY(val) bfin_write32(DMA43_Y_MODIFY, val)
1857#define bfin_read_DMA43_CURR_DESC_PTR() bfin_read32(DMA43_CURR_DESC_PTR)
1858#define bfin_write_DMA43_CURR_DESC_PTR(val) bfin_write32(DMA43_CURR_DESC_PTR, val)
1859#define bfin_read_DMA43_PREV_DESC_PTR() bfin_read32(DMA43_PREV_DESC_PTR)
1860#define bfin_write_DMA43_PREV_DESC_PTR(val) bfin_write32(DMA43_PREV_DESC_PTR, val)
1861#define bfin_read_DMA43_CURR_ADDR() bfin_read32(DMA43_CURR_ADDR)
1862#define bfin_write_DMA43_CURR_ADDR(val) bfin_write32(DMA43_CURR_ADDR, val)
1863#define bfin_read_DMA43_IRQ_STATUS() bfin_read32(DMA43_IRQ_STATUS)
1864#define bfin_write_DMA43_IRQ_STATUS(val) bfin_write32(DMA43_IRQ_STATUS, val)
1865#define bfin_read_DMA43_CURR_X_COUNT() bfin_read32(DMA43_CURR_X_COUNT)
1866#define bfin_write_DMA43_CURR_X_COUNT(val) bfin_write32(DMA43_CURR_X_COUNT, val)
1867#define bfin_read_DMA43_CURR_Y_COUNT() bfin_read32(DMA43_CURR_Y_COUNT)
1868#define bfin_write_DMA43_CURR_Y_COUNT(val) bfin_write32(DMA43_CURR_Y_COUNT, val)
1869#define bfin_read_DMA43_BWL_COUNT() bfin_read32(DMA43_BWL_COUNT)
1870#define bfin_write_DMA43_BWL_COUNT(val) bfin_write32(DMA43_BWL_COUNT, val)
1871#define bfin_read_DMA43_CURR_BWL_COUNT() bfin_read32(DMA43_CURR_BWL_COUNT)
1872#define bfin_write_DMA43_CURR_BWL_COUNT(val) bfin_write32(DMA43_CURR_BWL_COUNT, val)
1873#define bfin_read_DMA43_BWM_COUNT() bfin_read32(DMA43_BWM_COUNT)
1874#define bfin_write_DMA43_BWM_COUNT(val) bfin_write32(DMA43_BWM_COUNT, val)
1875#define bfin_read_DMA43_CURR_BWM_COUNT() bfin_read32(DMA43_CURR_BWM_COUNT)
1876#define bfin_write_DMA43_CURR_BWM_COUNT(val) bfin_write32(DMA43_CURR_BWM_COUNT, val)
1877
1878/* DMA Channel 44 Registers */
1879
1880#define bfin_read_DMA44_NEXT_DESC_PTR() bfin_read32(DMA44_NEXT_DESC_PTR)
1881#define bfin_write_DMA44_NEXT_DESC_PTR(val) bfin_write32(DMA44_NEXT_DESC_PTR, val)
1882#define bfin_read_DMA44_START_ADDR() bfin_read32(DMA44_START_ADDR)
1883#define bfin_write_DMA44_START_ADDR(val) bfin_write32(DMA44_START_ADDR, val)
1884#define bfin_read_DMA44_CONFIG() bfin_read32(DMA44_CONFIG)
1885#define bfin_write_DMA44_CONFIG(val) bfin_write32(DMA44_CONFIG, val)
1886#define bfin_read_DMA44_X_COUNT() bfin_read32(DMA44_X_COUNT)
1887#define bfin_write_DMA44_X_COUNT(val) bfin_write32(DMA44_X_COUNT, val)
1888#define bfin_read_DMA44_X_MODIFY() bfin_read32(DMA44_X_MODIFY)
1889#define bfin_write_DMA44_X_MODIFY(val) bfin_write32(DMA44_X_MODIFY, val)
1890#define bfin_read_DMA44_Y_COUNT() bfin_read32(DMA44_Y_COUNT)
1891#define bfin_write_DMA44_Y_COUNT(val) bfin_write32(DMA44_Y_COUNT, val)
1892#define bfin_read_DMA44_Y_MODIFY() bfin_read32(DMA44_Y_MODIFY)
1893#define bfin_write_DMA44_Y_MODIFY(val) bfin_write32(DMA44_Y_MODIFY, val)
1894#define bfin_read_DMA44_CURR_DESC_PTR() bfin_read32(DMA44_CURR_DESC_PTR)
1895#define bfin_write_DMA44_CURR_DESC_PTR(val) bfin_write32(DMA44_CURR_DESC_PTR, val)
1896#define bfin_read_DMA44_PREV_DESC_PTR() bfin_read32(DMA44_PREV_DESC_PTR)
1897#define bfin_write_DMA44_PREV_DESC_PTR(val) bfin_write32(DMA44_PREV_DESC_PTR, val)
1898#define bfin_read_DMA44_CURR_ADDR() bfin_read32(DMA44_CURR_ADDR)
1899#define bfin_write_DMA44_CURR_ADDR(val) bfin_write32(DMA44_CURR_ADDR, val)
1900#define bfin_read_DMA44_IRQ_STATUS() bfin_read32(DMA44_IRQ_STATUS)
1901#define bfin_write_DMA44_IRQ_STATUS(val) bfin_write32(DMA44_IRQ_STATUS, val)
1902#define bfin_read_DMA44_CURR_X_COUNT() bfin_read32(DMA44_CURR_X_COUNT)
1903#define bfin_write_DMA44_CURR_X_COUNT(val) bfin_write32(DMA44_CURR_X_COUNT, val)
1904#define bfin_read_DMA44_CURR_Y_COUNT() bfin_read32(DMA44_CURR_Y_COUNT)
1905#define bfin_write_DMA44_CURR_Y_COUNT(val) bfin_write32(DMA44_CURR_Y_COUNT, val)
1906#define bfin_read_DMA44_BWL_COUNT() bfin_read32(DMA44_BWL_COUNT)
1907#define bfin_write_DMA44_BWL_COUNT(val) bfin_write32(DMA44_BWL_COUNT, val)
1908#define bfin_read_DMA44_CURR_BWL_COUNT() bfin_read32(DMA44_CURR_BWL_COUNT)
1909#define bfin_write_DMA44_CURR_BWL_COUNT(val) bfin_write32(DMA44_CURR_BWL_COUNT, val)
1910#define bfin_read_DMA44_BWM_COUNT() bfin_read32(DMA44_BWM_COUNT)
1911#define bfin_write_DMA44_BWM_COUNT(val) bfin_write32(DMA44_BWM_COUNT, val)
1912#define bfin_read_DMA44_CURR_BWM_COUNT() bfin_read32(DMA44_CURR_BWM_COUNT)
1913#define bfin_write_DMA44_CURR_BWM_COUNT(val) bfin_write32(DMA44_CURR_BWM_COUNT, val)
1914
1915/* DMA Channel 45 Registers */
1916
1917#define bfin_read_DMA45_NEXT_DESC_PTR() bfin_read32(DMA45_NEXT_DESC_PTR)
1918#define bfin_write_DMA45_NEXT_DESC_PTR(val) bfin_write32(DMA45_NEXT_DESC_PTR, val)
1919#define bfin_read_DMA45_START_ADDR() bfin_read32(DMA45_START_ADDR)
1920#define bfin_write_DMA45_START_ADDR(val) bfin_write32(DMA45_START_ADDR, val)
1921#define bfin_read_DMA45_CONFIG() bfin_read32(DMA45_CONFIG)
1922#define bfin_write_DMA45_CONFIG(val) bfin_write32(DMA45_CONFIG, val)
1923#define bfin_read_DMA45_X_COUNT() bfin_read32(DMA45_X_COUNT)
1924#define bfin_write_DMA45_X_COUNT(val) bfin_write32(DMA45_X_COUNT, val)
1925#define bfin_read_DMA45_X_MODIFY() bfin_read32(DMA45_X_MODIFY)
1926#define bfin_write_DMA45_X_MODIFY(val) bfin_write32(DMA45_X_MODIFY, val)
1927#define bfin_read_DMA45_Y_COUNT() bfin_read32(DMA45_Y_COUNT)
1928#define bfin_write_DMA45_Y_COUNT(val) bfin_write32(DMA45_Y_COUNT, val)
1929#define bfin_read_DMA45_Y_MODIFY() bfin_read32(DMA45_Y_MODIFY)
1930#define bfin_write_DMA45_Y_MODIFY(val) bfin_write32(DMA45_Y_MODIFY, val)
1931#define bfin_read_DMA45_CURR_DESC_PTR() bfin_read32(DMA45_CURR_DESC_PTR)
1932#define bfin_write_DMA45_CURR_DESC_PTR(val) bfin_write32(DMA45_CURR_DESC_PTR, val)
1933#define bfin_read_DMA45_PREV_DESC_PTR() bfin_read32(DMA45_PREV_DESC_PTR)
1934#define bfin_write_DMA45_PREV_DESC_PTR(val) bfin_write32(DMA45_PREV_DESC_PTR, val)
1935#define bfin_read_DMA45_CURR_ADDR() bfin_read32(DMA45_CURR_ADDR)
1936#define bfin_write_DMA45_CURR_ADDR(val) bfin_write32(DMA45_CURR_ADDR, val)
1937#define bfin_read_DMA45_IRQ_STATUS() bfin_read32(DMA45_IRQ_STATUS)
1938#define bfin_write_DMA45_IRQ_STATUS(val) bfin_write32(DMA45_IRQ_STATUS, val)
1939#define bfin_read_DMA45_CURR_X_COUNT() bfin_read32(DMA45_CURR_X_COUNT)
1940#define bfin_write_DMA45_CURR_X_COUNT(val) bfin_write32(DMA45_CURR_X_COUNT, val)
1941#define bfin_read_DMA45_CURR_Y_COUNT() bfin_read32(DMA45_CURR_Y_COUNT)
1942#define bfin_write_DMA45_CURR_Y_COUNT(val) bfin_write32(DMA45_CURR_Y_COUNT, val)
1943#define bfin_read_DMA45_BWL_COUNT() bfin_read32(DMA45_BWL_COUNT)
1944#define bfin_write_DMA45_BWL_COUNT(val) bfin_write32(DMA45_BWL_COUNT, val)
1945#define bfin_read_DMA45_CURR_BWL_COUNT() bfin_read32(DMA45_CURR_BWL_COUNT)
1946#define bfin_write_DMA45_CURR_BWL_COUNT(val) bfin_write32(DMA45_CURR_BWL_COUNT, val)
1947#define bfin_read_DMA45_BWM_COUNT() bfin_read32(DMA45_BWM_COUNT)
1948#define bfin_write_DMA45_BWM_COUNT(val) bfin_write32(DMA45_BWM_COUNT, val)
1949#define bfin_read_DMA45_CURR_BWM_COUNT() bfin_read32(DMA45_CURR_BWM_COUNT)
1950#define bfin_write_DMA45_CURR_BWM_COUNT(val) bfin_write32(DMA45_CURR_BWM_COUNT, val)
1951
1952/* DMA Channel 46 Registers */
1953
1954#define bfin_read_DMA46_NEXT_DESC_PTR() bfin_read32(DMA46_NEXT_DESC_PTR)
1955#define bfin_write_DMA46_NEXT_DESC_PTR(val) bfin_write32(DMA46_NEXT_DESC_PTR, val)
1956#define bfin_read_DMA46_START_ADDR() bfin_read32(DMA46_START_ADDR)
1957#define bfin_write_DMA46_START_ADDR(val) bfin_write32(DMA46_START_ADDR, val)
1958#define bfin_read_DMA46_CONFIG() bfin_read32(DMA46_CONFIG)
1959#define bfin_write_DMA46_CONFIG(val) bfin_write32(DMA46_CONFIG, val)
1960#define bfin_read_DMA46_X_COUNT() bfin_read32(DMA46_X_COUNT)
1961#define bfin_write_DMA46_X_COUNT(val) bfin_write32(DMA46_X_COUNT, val)
1962#define bfin_read_DMA46_X_MODIFY() bfin_read32(DMA46_X_MODIFY)
1963#define bfin_write_DMA46_X_MODIFY(val) bfin_write32(DMA46_X_MODIFY, val)
1964#define bfin_read_DMA46_Y_COUNT() bfin_read32(DMA46_Y_COUNT)
1965#define bfin_write_DMA46_Y_COUNT(val) bfin_write32(DMA46_Y_COUNT, val)
1966#define bfin_read_DMA46_Y_MODIFY() bfin_read32(DMA46_Y_MODIFY)
1967#define bfin_write_DMA46_Y_MODIFY(val) bfin_write32(DMA46_Y_MODIFY, val)
1968#define bfin_read_DMA46_CURR_DESC_PTR() bfin_read32(DMA46_CURR_DESC_PTR)
1969#define bfin_write_DMA46_CURR_DESC_PTR(val) bfin_write32(DMA46_CURR_DESC_PTR, val)
1970#define bfin_read_DMA46_PREV_DESC_PTR() bfin_read32(DMA46_PREV_DESC_PTR)
1971#define bfin_write_DMA46_PREV_DESC_PTR(val) bfin_write32(DMA46_PREV_DESC_PTR, val)
1972#define bfin_read_DMA46_CURR_ADDR() bfin_read32(DMA46_CURR_ADDR)
1973#define bfin_write_DMA46_CURR_ADDR(val) bfin_write32(DMA46_CURR_ADDR, val)
1974#define bfin_read_DMA46_IRQ_STATUS() bfin_read32(DMA46_IRQ_STATUS)
1975#define bfin_write_DMA46_IRQ_STATUS(val) bfin_write32(DMA46_IRQ_STATUS, val)
1976#define bfin_read_DMA46_CURR_X_COUNT() bfin_read32(DMA46_CURR_X_COUNT)
1977#define bfin_write_DMA46_CURR_X_COUNT(val) bfin_write32(DMA46_CURR_X_COUNT, val)
1978#define bfin_read_DMA46_CURR_Y_COUNT() bfin_read32(DMA46_CURR_Y_COUNT)
1979#define bfin_write_DMA46_CURR_Y_COUNT(val) bfin_write32(DMA46_CURR_Y_COUNT, val)
1980#define bfin_read_DMA46_BWL_COUNT() bfin_read32(DMA46_BWL_COUNT)
1981#define bfin_write_DMA46_BWL_COUNT(val) bfin_write32(DMA46_BWL_COUNT, val)
1982#define bfin_read_DMA46_CURR_BWL_COUNT() bfin_read32(DMA46_CURR_BWL_COUNT)
1983#define bfin_write_DMA46_CURR_BWL_COUNT(val) bfin_write32(DMA46_CURR_BWL_COUNT, val)
1984#define bfin_read_DMA46_BWM_COUNT() bfin_read32(DMA46_BWM_COUNT)
1985#define bfin_write_DMA46_BWM_COUNT(val) bfin_write32(DMA46_BWM_COUNT, val)
1986#define bfin_read_DMA46_CURR_BWM_COUNT() bfin_read32(DMA46_CURR_BWM_COUNT)
1987#define bfin_write_DMA46_CURR_BWM_COUNT(val) bfin_write32(DMA46_CURR_BWM_COUNT, val)
1988
1989
1990/* EPPI1 Registers */
1991
1992
1993/* Port Interrubfin_read_()t 0 Registers (32-bit) */
1994
1995#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
1996#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
1997#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
1998#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
1999#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
2000#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
2001#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
2002#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
2003#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
2004#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
2005#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
2006#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
2007#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
2008#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
2009#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
2010#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
2011#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
2012#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
2013#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
2014#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
2015
2016/* Port Interrubfin_read_()t 1 Registers (32-bit) */
2017
2018#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
2019#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
2020#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
2021#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
2022#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
2023#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
2024#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
2025#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
2026#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
2027#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
2028#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
2029#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
2030#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
2031#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
2032#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
2033#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
2034#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
2035#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
2036#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
2037#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
2038
2039/* Port Interrubfin_read_()t 2 Registers (32-bit) */
2040
2041#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
2042#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
2043#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
2044#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
2045#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
2046#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
2047#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
2048#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
2049#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
2050#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
2051#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
2052#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
2053#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
2054#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
2055#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
2056#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
2057#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
2058#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
2059#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
2060#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
2061
2062/* Port Interrubfin_read_()t 3 Registers (32-bit) */
2063
2064#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
2065#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
2066#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
2067#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
2068#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
2069#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
2070#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
2071#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
2072#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
2073#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
2074#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
2075#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
2076#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
2077#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
2078#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
2079#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
2080#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
2081#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
2082#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
2083#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
2084
2085/* Port Interrubfin_read_()t 4 Registers (32-bit) */
2086
2087#define bfin_read_PINT4_MASK_SET() bfin_read32(PINT4_MASK_SET)
2088#define bfin_write_PINT4_MASK_SET(val) bfin_write32(PINT4_MASK_SET, val)
2089#define bfin_read_PINT4_MASK_CLEAR() bfin_read32(PINT4_MASK_CLEAR)
2090#define bfin_write_PINT4_MASK_CLEAR(val) bfin_write32(PINT4_MASK_CLEAR, val)
2091#define bfin_read_PINT4_REQUEST() bfin_read32(PINT4_REQUEST)
2092#define bfin_write_PINT4_REQUEST(val) bfin_write32(PINT4_REQUEST, val)
2093#define bfin_read_PINT4_ASSIGN() bfin_read32(PINT4_ASSIGN)
2094#define bfin_write_PINT4_ASSIGN(val) bfin_write32(PINT4_ASSIGN, val)
2095#define bfin_read_PINT4_EDGE_SET() bfin_read32(PINT4_EDGE_SET)
2096#define bfin_write_PINT4_EDGE_SET(val) bfin_write32(PINT4_EDGE_SET, val)
2097#define bfin_read_PINT4_EDGE_CLEAR() bfin_read32(PINT4_EDGE_CLEAR)
2098#define bfin_write_PINT4_EDGE_CLEAR(val) bfin_write32(PINT4_EDGE_CLEAR, val)
2099#define bfin_read_PINT4_INVERT_SET() bfin_read32(PINT4_INVERT_SET)
2100#define bfin_write_PINT4_INVERT_SET(val) bfin_write32(PINT4_INVERT_SET, val)
2101#define bfin_read_PINT4_INVERT_CLEAR() bfin_read32(PINT4_INVERT_CLEAR)
2102#define bfin_write_PINT4_INVERT_CLEAR(val) bfin_write32(PINT4_INVERT_CLEAR, val)
2103#define bfin_read_PINT4_PINSTATE() bfin_read32(PINT4_PINSTATE)
2104#define bfin_write_PINT4_PINSTATE(val) bfin_write32(PINT4_PINSTATE, val)
2105#define bfin_read_PINT4_LATCH() bfin_read32(PINT4_LATCH)
2106#define bfin_write_PINT4_LATCH(val) bfin_write32(PINT4_LATCH, val)
2107
2108/* Port Interrubfin_read_()t 5 Registers (32-bit) */
2109
2110#define bfin_read_PINT5_MASK_SET() bfin_read32(PINT5_MASK_SET)
2111#define bfin_write_PINT5_MASK_SET(val) bfin_write32(PINT5_MASK_SET, val)
2112#define bfin_read_PINT5_MASK_CLEAR() bfin_read32(PINT5_MASK_CLEAR)
2113#define bfin_write_PINT5_MASK_CLEAR(val) bfin_write32(PINT5_MASK_CLEAR, val)
2114#define bfin_read_PINT5_REQUEST() bfin_read32(PINT5_REQUEST)
2115#define bfin_write_PINT5_REQUEST(val) bfin_write32(PINT5_REQUEST, val)
2116#define bfin_read_PINT5_ASSIGN() bfin_read32(PINT5_ASSIGN)
2117#define bfin_write_PINT5_ASSIGN(val) bfin_write32(PINT5_ASSIGN, val)
2118#define bfin_read_PINT5_EDGE_SET() bfin_read32(PINT5_EDGE_SET)
2119#define bfin_write_PINT5_EDGE_SET(val) bfin_write32(PINT5_EDGE_SET, val)
2120#define bfin_read_PINT5_EDGE_CLEAR() bfin_read32(PINT5_EDGE_CLEAR)
2121#define bfin_write_PINT5_EDGE_CLEAR(val) bfin_write32(PINT5_EDGE_CLEAR, val)
2122#define bfin_read_PINT5_INVERT_SET() bfin_read32(PINT5_INVERT_SET)
2123#define bfin_write_PINT5_INVERT_SET(val) bfin_write32(PINT5_INVERT_SET, val)
2124#define bfin_read_PINT5_INVERT_CLEAR() bfin_read32(PINT5_INVERT_CLEAR)
2125#define bfin_write_PINT5_INVERT_CLEAR(val) bfin_write32(PINT5_INVERT_CLEAR, val)
2126#define bfin_read_PINT5_PINSTATE() bfin_read32(PINT5_PINSTATE)
2127#define bfin_write_PINT5_PINSTATE(val) bfin_write32(PINT5_PINSTATE, val)
2128#define bfin_read_PINT5_LATCH() bfin_read32(PINT5_LATCH)
2129#define bfin_write_PINT5_LATCH(val) bfin_write32(PINT5_LATCH, val)
2130
2131/* Port A Registers */
2132
2133#define bfin_read_PORTA_FER() bfin_read32(PORTA_FER)
2134#define bfin_write_PORTA_FER(val) bfin_write32(PORTA_FER, val)
2135#define bfin_read_PORTA_FER_SET() bfin_read32(PORTA_FER_SET)
2136#define bfin_write_PORTA_FER_SET(val) bfin_write32(PORTA_FER_SET, val)
2137#define bfin_read_PORTA_FER_CLEAR() bfin_read32(PORTA_FER_CLEAR)
2138#define bfin_write_PORTA_FER_CLEAR(val) bfin_write32(PORTA_FER_CLEAR, val)
2139#define bfin_read_PORTA() bfin_read32(PORTA)
2140#define bfin_write_PORTA(val) bfin_write32(PORTA, val)
2141#define bfin_read_PORTA_SET() bfin_read32(PORTA_SET)
2142#define bfin_write_PORTA_SET(val) bfin_write32(PORTA_SET, val)
2143#define bfin_read_PORTA_CLEAR() bfin_read32(PORTA_CLEAR)
2144#define bfin_write_PORTA_CLEAR(val) bfin_write32(PORTA_CLEAR, val)
2145#define bfin_read_PORTA_DIR() bfin_read32(PORTA_DIR)
2146#define bfin_write_PORTA_DIR(val) bfin_write32(PORTA_DIR, val)
2147#define bfin_read_PORTA_DIR_SET() bfin_read32(PORTA_DIR_SET)
2148#define bfin_write_PORTA_DIR_SET(val) bfin_write32(PORTA_DIR_SET, val)
2149#define bfin_read_PORTA_DIR_CLEAR() bfin_read32(PORTA_DIR_CLEAR)
2150#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write32(PORTA_DIR_CLEAR, val)
2151#define bfin_read_PORTA_INEN() bfin_read32(PORTA_INEN)
2152#define bfin_write_PORTA_INEN(val) bfin_write32(PORTA_INEN, val)
2153#define bfin_read_PORTA_INEN_SET() bfin_read32(PORTA_INEN_SET)
2154#define bfin_write_PORTA_INEN_SET(val) bfin_write32(PORTA_INEN_SET, val)
2155#define bfin_read_PORTA_INEN_CLEAR() bfin_read32(PORTA_INEN_CLEAR)
2156#define bfin_write_PORTA_INEN_CLEAR(val) bfin_write32(PORTA_INEN_CLEAR, val)
2157#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
2158#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
2159#define bfin_read_PORTA_DATA_TGL() bfin_read32(PORTA_DATA_TGL)
2160#define bfin_write_PORTA_DATA_TGL(val) bfin_write32(PORTA_DATA_TGL, val)
2161#define bfin_read_PORTA_POL() bfin_read32(PORTA_POL)
2162#define bfin_write_PORTA_POL(val) bfin_write32(PORTA_POL, val)
2163#define bfin_read_PORTA_POL_SET() bfin_read32(PORTA_POL_SET)
2164#define bfin_write_PORTA_POL_SET(val) bfin_write32(PORTA_POL_SET, val)
2165#define bfin_read_PORTA_POL_CLEAR() bfin_read32(PORTA_POL_CLEAR)
2166#define bfin_write_PORTA_POL_CLEAR(val) bfin_write32(PORTA_POL_CLEAR, val)
2167#define bfin_read_PORTA_LOCK() bfin_read32(PORTA_LOCK)
2168#define bfin_write_PORTA_LOCK(val) bfin_write32(PORTA_LOCK, val)
2169#define bfin_read_PORTA_REVID() bfin_read32(PORTA_REVID)
2170#define bfin_write_PORTA_REVID(val) bfin_write32(PORTA_REVID, val)
2171
2172
2173
2174/* Port B Registers */
2175#define bfin_read_PORTB_FER() bfin_read32(PORTB_FER)
2176#define bfin_write_PORTB_FER(val) bfin_write32(PORTB_FER, val)
2177#define bfin_read_PORTB_FER_SET() bfin_read32(PORTB_FER_SET)
2178#define bfin_write_PORTB_FER_SET(val) bfin_write32(PORTB_FER_SET, val)
2179#define bfin_read_PORTB_FER_CLEAR() bfin_read32(PORTB_FER_CLEAR)
2180#define bfin_write_PORTB_FER_CLEAR(val) bfin_write32(PORTB_FER_CLEAR, val)
2181#define bfin_read_PORTB() bfin_read32(PORTB)
2182#define bfin_write_PORTB(val) bfin_write32(PORTB, val)
2183#define bfin_read_PORTB_SET() bfin_read32(PORTB_SET)
2184#define bfin_write_PORTB_SET(val) bfin_write32(PORTB_SET, val)
2185#define bfin_read_PORTB_CLEAR() bfin_read32(PORTB_CLEAR)
2186#define bfin_write_PORTB_CLEAR(val) bfin_write32(PORTB_CLEAR, val)
2187#define bfin_read_PORTB_DIR() bfin_read32(PORTB_DIR)
2188#define bfin_write_PORTB_DIR(val) bfin_write32(PORTB_DIR, val)
2189#define bfin_read_PORTB_DIR_SET() bfin_read32(PORTB_DIR_SET)
2190#define bfin_write_PORTB_DIR_SET(val) bfin_write32(PORTB_DIR_SET, val)
2191#define bfin_read_PORTB_DIR_CLEAR() bfin_read32(PORTB_DIR_CLEAR)
2192#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write32(PORTB_DIR_CLEAR, val)
2193#define bfin_read_PORTB_INEN() bfin_read32(PORTB_INEN)
2194#define bfin_write_PORTB_INEN(val) bfin_write32(PORTB_INEN, val)
2195#define bfin_read_PORTB_INEN_SET() bfin_read32(PORTB_INEN_SET)
2196#define bfin_write_PORTB_INEN_SET(val) bfin_write32(PORTB_INEN_SET, val)
2197#define bfin_read_PORTB_INEN_CLEAR() bfin_read32(PORTB_INEN_CLEAR)
2198#define bfin_write_PORTB_INEN_CLEAR(val) bfin_write32(PORTB_INEN_CLEAR, val)
2199#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
2200#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
2201#define bfin_read_PORTB_DATA_TGL() bfin_read32(PORTB_DATA_TGL)
2202#define bfin_write_PORTB_DATA_TGL(val) bfin_write32(PORTB_DATA_TGL, val)
2203#define bfin_read_PORTB_POL() bfin_read32(PORTB_POL)
2204#define bfin_write_PORTB_POL(val) bfin_write32(PORTB_POL, val)
2205#define bfin_read_PORTB_POL_SET() bfin_read32(PORTB_POL_SET)
2206#define bfin_write_PORTB_POL_SET(val) bfin_write32(PORTB_POL_SET, val)
2207#define bfin_read_PORTB_POL_CLEAR() bfin_read32(PORTB_POL_CLEAR)
2208#define bfin_write_PORTB_POL_CLEAR(val) bfin_write32(PORTB_POL_CLEAR, val)
2209#define bfin_read_PORTB_LOCK() bfin_read32(PORTB_LOCK)
2210#define bfin_write_PORTB_LOCK(val) bfin_write32(PORTB_LOCK, val)
2211#define bfin_read_PORTB_REVID() bfin_read32(PORTB_REVID)
2212#define bfin_write_PORTB_REVID(val) bfin_write32(PORTB_REVID, val)
2213
2214
2215/* Port C Registers */
2216#define bfin_read_PORTC_FER() bfin_read32(PORTC_FER)
2217#define bfin_write_PORTC_FER(val) bfin_write32(PORTC_FER, val)
2218#define bfin_read_PORTC_FER_SET() bfin_read32(PORTC_FER_SET)
2219#define bfin_write_PORTC_FER_SET(val) bfin_write32(PORTC_FER_SET, val)
2220#define bfin_read_PORTC_FER_CLEAR() bfin_read32(PORTC_FER_CLEAR)
2221#define bfin_write_PORTC_FER_CLEAR(val) bfin_write32(PORTC_FER_CLEAR, val)
2222#define bfin_read_PORTC() bfin_read32(PORTC)
2223#define bfin_write_PORTC(val) bfin_write32(PORTC, val)
2224#define bfin_read_PORTC_SET() bfin_read32(PORTC_SET)
2225#define bfin_write_PORTC_SET(val) bfin_write32(PORTC_SET, val)
2226#define bfin_read_PORTC_CLEAR() bfin_read32(PORTC_CLEAR)
2227#define bfin_write_PORTC_CLEAR(val) bfin_write32(PORTC_CLEAR, val)
2228#define bfin_read_PORTC_DIR() bfin_read32(PORTC_DIR)
2229#define bfin_write_PORTC_DIR(val) bfin_write32(PORTC_DIR, val)
2230#define bfin_read_PORTC_DIR_SET() bfin_read32(PORTC_DIR_SET)
2231#define bfin_write_PORTC_DIR_SET(val) bfin_write32(PORTC_DIR_SET, val)
2232#define bfin_read_PORTC_DIR_CLEAR() bfin_read32(PORTC_DIR_CLEAR)
2233#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write32(PORTC_DIR_CLEAR, val)
2234#define bfin_read_PORTC_INEN() bfin_read32(PORTC_INEN)
2235#define bfin_write_PORTC_INEN(val) bfin_write32(PORTC_INEN, val)
2236#define bfin_read_PORTC_INEN_SET() bfin_read32(PORTC_INEN_SET)
2237#define bfin_write_PORTC_INEN_SET(val) bfin_write32(PORTC_INEN_SET, val)
2238#define bfin_read_PORTC_INEN_CLEAR() bfin_read32(PORTC_INEN_CLEAR)
2239#define bfin_write_PORTC_INEN_CLEAR(val) bfin_write32(PORTC_INEN_CLEAR, val)
2240#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
2241#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
2242#define bfin_read_PORTC_DATA_TGL() bfin_read32(PORTC_DATA_TGL)
2243#define bfin_write_PORTC_DATA_TGL(val) bfin_write32(PORTC_DATA_TGL, val)
2244#define bfin_read_PORTC_POL() bfin_read32(PORTC_POL)
2245#define bfin_write_PORTC_POL(val) bfin_write32(PORTC_POL, val)
2246#define bfin_read_PORTC_POL_SET() bfin_read32(PORTC_POL_SET)
2247#define bfin_write_PORTC_POL_SET(val) bfin_write32(PORTC_POL_SET, val)
2248#define bfin_read_PORTC_POL_CLEAR() bfin_read32(PORTC_POL_CLEAR)
2249#define bfin_write_PORTC_POL_CLEAR(val) bfin_write32(PORTC_POL_CLEAR, val)
2250#define bfin_read_PORTC_LOCK() bfin_read32(PORTC_LOCK)
2251#define bfin_write_PORTC_LOCK(val) bfin_write32(PORTC_LOCK, val)
2252#define bfin_read_PORTC_REVID() bfin_read32(PORTC_REVID)
2253#define bfin_write_PORTC_REVID(val) bfin_write32(PORTC_REVID, val)
2254
2255
2256/* Port D Registers */
2257#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER)
2258#define bfin_write_PORTD_FER(val) bfin_write32(PORTD_FER, val)
2259#define bfin_read_PORTD_FER_SET() bfin_read32(PORTD_FER_SET)
2260#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val)
2261#define bfin_read_PORTD_FER_CLEAR() bfin_read32(PORTD_FER_CLEAR)
2262#define bfin_write_PORTD_FER_CLEAR(val) bfin_write32(PORTD_FER_CLEAR, val)
2263#define bfin_read_PORTD() bfin_read32(PORTD)
2264#define bfin_write_PORTD(val) bfin_write32(PORTD, val)
2265#define bfin_read_PORTD_SET() bfin_read32(PORTD_SET)
2266#define bfin_write_PORTD_SET(val) bfin_write32(PORTD_SET, val)
2267#define bfin_read_PORTD_CLEAR() bfin_read32(PORTD_CLEAR)
2268#define bfin_write_PORTD_CLEAR(val) bfin_write32(PORTD_CLEAR, val)
2269#define bfin_read_PORTD_DIR() bfin_read32(PORTD_DIR)
2270#define bfin_write_PORTD_DIR(val) bfin_write32(PORTD_DIR, val)
2271#define bfin_read_PORTD_DIR_SET() bfin_read32(PORTD_DIR_SET)
2272#define bfin_write_PORTD_DIR_SET(val) bfin_write32(PORTD_DIR_SET, val)
2273#define bfin_read_PORTD_DIR_CLEAR() bfin_read32(PORTD_DIR_CLEAR)
2274#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write32(PORTD_DIR_CLEAR, val)
2275#define bfin_read_PORTD_INEN() bfin_read32(PORTD_INEN)
2276#define bfin_write_PORTD_INEN(val) bfin_write32(PORTD_INEN, val)
2277#define bfin_read_PORTD_INEN_SET() bfin_read32(PORTD_INEN_SET)
2278#define bfin_write_PORTD_INEN_SET(val) bfin_write32(PORTD_INEN_SET, val)
2279#define bfin_read_PORTD_INEN_CLEAR() bfin_read32(PORTD_INEN_CLEAR)
2280#define bfin_write_PORTD_INEN_CLEAR(val) bfin_write32(PORTD_INEN_CLEAR, val)
2281#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
2282#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
2283#define bfin_read_PORTD_DATA_TGL() bfin_read32(PORTD_DATA_TGL)
2284#define bfin_write_PORTD_DATA_TGL(val) bfin_write32(PORTD_DATA_TGL, val)
2285#define bfin_read_PORTD_POL() bfin_read32(PORTD_POL)
2286#define bfin_write_PORTD_POL(val) bfin_write32(PORTD_POL, val)
2287#define bfin_read_PORTD_POL_SET() bfin_read32(PORTD_POL_SET)
2288#define bfin_write_PORTD_POL_SET(val) bfin_write32(PORTD_POL_SET, val)
2289#define bfin_read_PORTD_POL_CLEAR() bfin_read32(PORTD_POL_CLEAR)
2290#define bfin_write_PORTD_POL_CLEAR(val) bfin_write32(PORTD_POL_CLEAR, val)
2291#define bfin_read_PORTD_LOCK() bfin_read32(PORTD_LOCK)
2292#define bfin_write_PORTD_LOCK(val) bfin_write32(PORTD_LOCK, val)
2293#define bfin_read_PORTD_REVID() bfin_read32(PORTD_REVID)
2294#define bfin_write_PORTD_REVID(val) bfin_write32(PORTD_REVID, val)
2295
2296
2297/* Port E Registers */
2298#define bfin_read_PORTE_FER() bfin_read32(PORTE_FER)
2299#define bfin_write_PORTE_FER(val) bfin_write32(PORTE_FER, val)
2300#define bfin_read_PORTE_FER_SET() bfin_read32(PORTE_FER_SET)
2301#define bfin_write_PORTE_FER_SET(val) bfin_write32(PORTE_FER_SET, val)
2302#define bfin_read_PORTE_FER_CLEAR() bfin_read32(PORTE_FER_CLEAR)
2303#define bfin_write_PORTE_FER_CLEAR(val) bfin_write32(PORTE_FER_CLEAR, val)
2304#define bfin_read_PORTE() bfin_read32(PORTE)
2305#define bfin_write_PORTE(val) bfin_write32(PORTE, val)
2306#define bfin_read_PORTE_SET() bfin_read32(PORTE_SET)
2307#define bfin_write_PORTE_SET(val) bfin_write32(PORTE_SET, val)
2308#define bfin_read_PORTE_CLEAR() bfin_read32(PORTE_CLEAR)
2309#define bfin_write_PORTE_CLEAR(val) bfin_write32(PORTE_CLEAR, val)
2310#define bfin_read_PORTE_DIR() bfin_read32(PORTE_DIR)
2311#define bfin_write_PORTE_DIR(val) bfin_write32(PORTE_DIR, val)
2312#define bfin_read_PORTE_DIR_SET() bfin_read32(PORTE_DIR_SET)
2313#define bfin_write_PORTE_DIR_SET(val) bfin_write32(PORTE_DIR_SET, val)
2314#define bfin_read_PORTE_DIR_CLEAR() bfin_read32(PORTE_DIR_CLEAR)
2315#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write32(PORTE_DIR_CLEAR, val)
2316#define bfin_read_PORTE_INEN() bfin_read32(PORTE_INEN)
2317#define bfin_write_PORTE_INEN(val) bfin_write32(PORTE_INEN, val)
2318#define bfin_read_PORTE_INEN_SET() bfin_read32(PORTE_INEN_SET)
2319#define bfin_write_PORTE_INEN_SET(val) bfin_write32(PORTE_INEN_SET, val)
2320#define bfin_read_PORTE_INEN_CLEAR() bfin_read32(PORTE_INEN_CLEAR)
2321#define bfin_write_PORTE_INEN_CLEAR(val) bfin_write32(PORTE_INEN_CLEAR, val)
2322#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
2323#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
2324#define bfin_read_PORTE_DATA_TGL() bfin_read32(PORTE_DATA_TGL)
2325#define bfin_write_PORTE_DATA_TGL(val) bfin_write32(PORTE_DATA_TGL, val)
2326#define bfin_read_PORTE_POL() bfin_read32(PORTE_POL)
2327#define bfin_write_PORTE_POL(val) bfin_write32(PORTE_POL, val)
2328#define bfin_read_PORTE_POL_SET() bfin_read32(PORTE_POL_SET)
2329#define bfin_write_PORTE_POL_SET(val) bfin_write32(PORTE_POL_SET, val)
2330#define bfin_read_PORTE_POL_CLEAR() bfin_read32(PORTE_POL_CLEAR)
2331#define bfin_write_PORTE_POL_CLEAR(val) bfin_write32(PORTE_POL_CLEAR, val)
2332#define bfin_read_PORTE_LOCK() bfin_read32(PORTE_LOCK)
2333#define bfin_write_PORTE_LOCK(val) bfin_write32(PORTE_LOCK, val)
2334#define bfin_read_PORTE_REVID() bfin_read32(PORTE_REVID)
2335#define bfin_write_PORTE_REVID(val) bfin_write32(PORTE_REVID, val)
2336
2337
2338/* Port F Registers */
2339#define bfin_read_PORTF_FER() bfin_read32(PORTF_FER)
2340#define bfin_write_PORTF_FER(val) bfin_write32(PORTF_FER, val)
2341#define bfin_read_PORTF_FER_SET() bfin_read32(PORTF_FER_SET)
2342#define bfin_write_PORTF_FER_SET(val) bfin_write32(PORTF_FER_SET, val)
2343#define bfin_read_PORTF_FER_CLEAR() bfin_read32(PORTF_FER_CLEAR)
2344#define bfin_write_PORTF_FER_CLEAR(val) bfin_write32(PORTF_FER_CLEAR, val)
2345#define bfin_read_PORTF() bfin_read32(PORTF)
2346#define bfin_write_PORTF(val) bfin_write32(PORTF, val)
2347#define bfin_read_PORTF_SET() bfin_read32(PORTF_SET)
2348#define bfin_write_PORTF_SET(val) bfin_write32(PORTF_SET, val)
2349#define bfin_read_PORTF_CLEAR() bfin_read32(PORTF_CLEAR)
2350#define bfin_write_PORTF_CLEAR(val) bfin_write32(PORTF_CLEAR, val)
2351#define bfin_read_PORTF_DIR() bfin_read32(PORTF_DIR)
2352#define bfin_write_PORTF_DIR(val) bfin_write32(PORTF_DIR, val)
2353#define bfin_read_PORTF_DIR_SET() bfin_read32(PORTF_DIR_SET)
2354#define bfin_write_PORTF_DIR_SET(val) bfin_write32(PORTF_DIR_SET, val)
2355#define bfin_read_PORTF_DIR_CLEAR() bfin_read32(PORTF_DIR_CLEAR)
2356#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write32(PORTF_DIR_CLEAR, val)
2357#define bfin_read_PORTF_INEN() bfin_read32(PORTF_INEN)
2358#define bfin_write_PORTF_INEN(val) bfin_write32(PORTF_INEN, val)
2359#define bfin_read_PORTF_INEN_SET() bfin_read32(PORTF_INEN_SET)
2360#define bfin_write_PORTF_INEN_SET(val) bfin_write32(PORTF_INEN_SET, val)
2361#define bfin_read_PORTF_INEN_CLEAR() bfin_read32(PORTF_INEN_CLEAR)
2362#define bfin_write_PORTF_INEN_CLEAR(val) bfin_write32(PORTF_INEN_CLEAR, val)
2363#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
2364#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
2365#define bfin_read_PORTF_DATA_TGL() bfin_read32(PORTF_DATA_TGL)
2366#define bfin_write_PORTF_DATA_TGL(val) bfin_write32(PORTF_DATA_TGL, val)
2367#define bfin_read_PORTF_POL() bfin_read32(PORTF_POL)
2368#define bfin_write_PORTF_POL(val) bfin_write32(PORTF_POL, val)
2369#define bfin_read_PORTF_POL_SET() bfin_read32(PORTF_POL_SET)
2370#define bfin_write_PORTF_POL_SET(val) bfin_write32(PORTF_POL_SET, val)
2371#define bfin_read_PORTF_POL_CLEAR() bfin_read32(PORTF_POL_CLEAR)
2372#define bfin_write_PORTF_POL_CLEAR(val) bfin_write32(PORTF_POL_CLEAR, val)
2373#define bfin_read_PORTF_LOCK() bfin_read32(PORTF_LOCK)
2374#define bfin_write_PORTF_LOCK(val) bfin_write32(PORTF_LOCK, val)
2375#define bfin_read_PORTF_REVID() bfin_read32(PORTF_REVID)
2376#define bfin_write_PORTF_REVID(val) bfin_write32(PORTF_REVID, val)
2377
2378
2379/* Port G Registers */
2380#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER)
2381#define bfin_write_PORTG_FER(val) bfin_write32(PORTG_FER, val)
2382#define bfin_read_PORTG_FER_SET() bfin_read32(PORTG_FER_SET)
2383#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val)
2384#define bfin_read_PORTG_FER_CLEAR() bfin_read32(PORTG_FER_CLEAR)
2385#define bfin_write_PORTG_FER_CLEAR(val) bfin_write32(PORTG_FER_CLEAR, val)
2386#define bfin_read_PORTG() bfin_read32(PORTG)
2387#define bfin_write_PORTG(val) bfin_write32(PORTG, val)
2388#define bfin_read_PORTG_SET() bfin_read32(PORTG_SET)
2389#define bfin_write_PORTG_SET(val) bfin_write32(PORTG_SET, val)
2390#define bfin_read_PORTG_CLEAR() bfin_read32(PORTG_CLEAR)
2391#define bfin_write_PORTG_CLEAR(val) bfin_write32(PORTG_CLEAR, val)
2392#define bfin_read_PORTG_DIR() bfin_read32(PORTG_DIR)
2393#define bfin_write_PORTG_DIR(val) bfin_write32(PORTG_DIR, val)
2394#define bfin_read_PORTG_DIR_SET() bfin_read32(PORTG_DIR_SET)
2395#define bfin_write_PORTG_DIR_SET(val) bfin_write32(PORTG_DIR_SET, val)
2396#define bfin_read_PORTG_DIR_CLEAR() bfin_read32(PORTG_DIR_CLEAR)
2397#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write32(PORTG_DIR_CLEAR, val)
2398#define bfin_read_PORTG_INEN() bfin_read32(PORTG_INEN)
2399#define bfin_write_PORTG_INEN(val) bfin_write32(PORTG_INEN, val)
2400#define bfin_read_PORTG_INEN_SET() bfin_read32(PORTG_INEN_SET)
2401#define bfin_write_PORTG_INEN_SET(val) bfin_write32(PORTG_INEN_SET, val)
2402#define bfin_read_PORTG_INEN_CLEAR() bfin_read32(PORTG_INEN_CLEAR)
2403#define bfin_write_PORTG_INEN_CLEAR(val) bfin_write32(PORTG_INEN_CLEAR, val)
2404#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
2405#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
2406#define bfin_read_PORTG_DATA_TGL() bfin_read32(PORTG_DATA_TGL)
2407#define bfin_write_PORTG_DATA_TGL(val) bfin_write32(PORTG_DATA_TGL, val)
2408#define bfin_read_PORTG_POL() bfin_read32(PORTG_POL)
2409#define bfin_write_PORTG_POL(val) bfin_write32(PORTG_POL, val)
2410#define bfin_read_PORTG_POL_SET() bfin_read32(PORTG_POL_SET)
2411#define bfin_write_PORTG_POL_SET(val) bfin_write32(PORTG_POL_SET, val)
2412#define bfin_read_PORTG_POL_CLEAR() bfin_read32(PORTG_POL_CLEAR)
2413#define bfin_write_PORTG_POL_CLEAR(val) bfin_write32(PORTG_POL_CLEAR, val)
2414#define bfin_read_PORTG_LOCK() bfin_read32(PORTG_LOCK)
2415#define bfin_write_PORTG_LOCK(val) bfin_write32(PORTG_LOCK, val)
2416#define bfin_read_PORTG_REVID() bfin_read32(PORTG_REVID)
2417#define bfin_write_PORTG_REVID(val) bfin_write32(PORTG_REVID, val)
2418
2419
2420
2421
2422/* CAN Controller 0 Config 1 Registers */
2423
2424#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
2425#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
2426#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
2427#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
2428#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
2429#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
2430#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
2431#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
2432#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
2433#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
2434#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
2435#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
2436#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
2437#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
2438#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
2439#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
2440#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
2441#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
2442#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
2443#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
2444#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
2445#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
2446#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
2447#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
2448#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
2449#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
2450
2451/* CAN Controller 0 Config 2 Registers */
2452
2453#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
2454#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
2455#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
2456#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
2457#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
2458#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
2459#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
2460#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
2461#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
2462#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
2463#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
2464#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
2465#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
2466#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
2467#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
2468#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
2469#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
2470#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
2471#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
2472#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
2473#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
2474#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
2475#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
2476#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
2477#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
2478#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
2479
2480/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
2481
2482#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
2483#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
2484#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
2485#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
2486#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
2487#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
2488#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
2489#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
2490#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
2491#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
2492#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
2493#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
2494#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
2495#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
2496#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
2497#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
2498#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
2499#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
2500#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
2501#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
2502#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
2503#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
2504#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
2505#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
2506#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
2507#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
2508#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
2509#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
2510#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
2511#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
2512#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
2513#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
2514
2515/* CAN Controller 0 Accebfin_read_()tance Registers */
2516
2517#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
2518#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
2519#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
2520#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
2521#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
2522#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
2523#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
2524#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
2525#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
2526#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
2527#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
2528#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
2529#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
2530#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
2531#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
2532#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
2533#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
2534#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
2535#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
2536#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
2537#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
2538#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
2539#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
2540#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
2541#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
2542#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
2543#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
2544#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
2545#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
2546#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
2547#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
2548#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
2549#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
2550#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
2551#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
2552#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
2553#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
2554#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
2555#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
2556#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
2557#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
2558#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
2559#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
2560#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
2561#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
2562#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
2563#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
2564#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
2565#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
2566#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
2567#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
2568#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
2569#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
2570#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
2571#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
2572#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
2573#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
2574#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
2575#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
2576#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
2577#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
2578#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
2579#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
2580#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
2581
2582/* CAN Controller 0 Accebfin_read_()tance Registers */
2583
2584#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
2585#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
2586#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
2587#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
2588#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
2589#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
2590#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
2591#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
2592#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
2593#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
2594#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
2595#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
2596#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
2597#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
2598#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
2599#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
2600#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
2601#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
2602#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
2603#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
2604#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
2605#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
2606#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
2607#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
2608#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
2609#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
2610#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
2611#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
2612#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
2613#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
2614#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
2615#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
2616#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
2617#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
2618#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
2619#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
2620#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
2621#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
2622#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
2623#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
2624#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
2625#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
2626#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
2627#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
2628#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
2629#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
2630#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
2631#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
2632#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
2633#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
2634#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
2635#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
2636#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
2637#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
2638#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
2639#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
2640#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
2641#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
2642#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
2643#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
2644#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
2645#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
2646#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
2647#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
2648
2649/* CAN Controller 0 Mailbox Data Registers */
2650
2651#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
2652#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
2653#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
2654#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
2655#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
2656#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
2657#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
2658#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
2659#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
2660#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
2661#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
2662#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
2663#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
2664#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
2665#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
2666#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
2667#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
2668#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
2669#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
2670#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
2671#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
2672#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
2673#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
2674#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
2675#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
2676#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
2677#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
2678#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
2679#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
2680#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
2681#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
2682#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
2683#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
2684#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
2685#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
2686#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
2687#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
2688#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
2689#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
2690#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
2691#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
2692#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
2693#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
2694#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
2695#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
2696#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
2697#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
2698#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
2699#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
2700#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
2701#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
2702#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
2703#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
2704#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
2705#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
2706#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
2707#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
2708#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
2709#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
2710#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
2711#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
2712#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
2713#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
2714#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
2715#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
2716#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
2717#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
2718#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
2719#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
2720#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
2721#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
2722#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
2723#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
2724#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
2725#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
2726#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
2727#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
2728#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
2729#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
2730#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
2731#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
2732#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
2733#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
2734#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
2735#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
2736#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
2737#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
2738#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
2739#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
2740#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
2741#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
2742#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
2743#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
2744#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
2745#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
2746#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
2747#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
2748#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
2749#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
2750#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
2751#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
2752#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
2753#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
2754#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
2755#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
2756#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
2757#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
2758#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
2759#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
2760#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
2761#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
2762#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
2763#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
2764#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
2765#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
2766#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
2767#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
2768#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
2769#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
2770#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
2771#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
2772#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
2773#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
2774#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
2775#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
2776#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
2777#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
2778#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
2779#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
2780#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
2781#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
2782#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
2783#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
2784#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
2785#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
2786#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
2787#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
2788#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
2789#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
2790#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
2791#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
2792#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
2793#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
2794#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
2795#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
2796#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
2797#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
2798#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
2799#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
2800#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
2801#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
2802#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
2803#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
2804#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
2805#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
2806#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
2807#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
2808#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
2809#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
2810#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
2811#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
2812#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
2813#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
2814#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
2815#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
2816#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
2817#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
2818#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
2819#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
2820#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
2821#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
2822#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
2823#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
2824#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
2825#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
2826#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
2827#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
2828#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
2829#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
2830#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
2831#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
2832#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
2833#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
2834#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
2835#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
2836#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
2837#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
2838#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
2839#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
2840#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
2841#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
2842#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
2843#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
2844#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
2845#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
2846#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
2847#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
2848#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
2849#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
2850#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
2851#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
2852#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
2853#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
2854#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
2855#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
2856#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
2857#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
2858#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
2859#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
2860#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
2861#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
2862#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
2863#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
2864#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
2865#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
2866#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
2867#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
2868#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
2869#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
2870#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
2871#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
2872#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
2873#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
2874#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
2875#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
2876#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
2877#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
2878#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
2879#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
2880#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
2881#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
2882#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
2883#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
2884#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
2885#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
2886#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
2887#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
2888#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
2889#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
2890#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
2891#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
2892#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
2893#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
2894#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
2895#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
2896#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
2897#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
2898#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
2899#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
2900#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
2901#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
2902#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
2903#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
2904#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
2905#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
2906#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
2907
2908/* CAN Controller 0 Mailbox Data Registers */
2909
2910#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
2911#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
2912#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
2913#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
2914#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
2915#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
2916#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
2917#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
2918#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
2919#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
2920#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
2921#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
2922#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
2923#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
2924#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
2925#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
2926#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
2927#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
2928#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
2929#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
2930#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
2931#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
2932#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
2933#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
2934#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
2935#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
2936#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
2937#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
2938#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
2939#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
2940#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
2941#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
2942#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
2943#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
2944#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
2945#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
2946#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
2947#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
2948#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
2949#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
2950#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
2951#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
2952#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
2953#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
2954#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
2955#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
2956#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
2957#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
2958#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
2959#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
2960#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
2961#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
2962#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
2963#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
2964#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
2965#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
2966#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
2967#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
2968#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
2969#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
2970#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
2971#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
2972#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
2973#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
2974#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
2975#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
2976#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
2977#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
2978#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
2979#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
2980#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
2981#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
2982#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
2983#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
2984#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
2985#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
2986#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
2987#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
2988#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
2989#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
2990#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
2991#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
2992#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
2993#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
2994#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
2995#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
2996#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
2997#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
2998#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
2999#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
3000#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
3001#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
3002#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
3003#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
3004#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
3005#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
3006#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
3007#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
3008#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
3009#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
3010#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
3011#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
3012#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
3013#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
3014#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
3015#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
3016#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
3017#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
3018#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
3019#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
3020#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
3021#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
3022#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
3023#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
3024#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
3025#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
3026#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
3027#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
3028#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
3029#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
3030#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
3031#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
3032#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
3033#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
3034#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
3035#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
3036#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
3037#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
3038#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
3039#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
3040#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
3041#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
3042#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
3043#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
3044#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
3045#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
3046#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
3047#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
3048#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
3049#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
3050#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
3051#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
3052#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
3053#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
3054#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
3055#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
3056#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
3057#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
3058#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
3059#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
3060#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
3061#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
3062#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
3063#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
3064#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
3065#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
3066#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
3067#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
3068#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
3069#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
3070#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
3071#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
3072#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
3073#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
3074#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
3075#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
3076#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
3077#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
3078#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
3079#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
3080#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
3081#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
3082#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
3083#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
3084#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
3085#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
3086#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
3087#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
3088#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
3089#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
3090#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
3091#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
3092#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
3093#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
3094#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
3095#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
3096#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
3097#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
3098#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
3099#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
3100#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
3101#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
3102#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
3103#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
3104#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
3105#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
3106#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
3107#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
3108#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
3109#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
3110#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
3111#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
3112#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
3113#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
3114#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
3115#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
3116#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
3117#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
3118#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
3119#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
3120#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
3121#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
3122#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
3123#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
3124#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
3125#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
3126#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
3127#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
3128#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
3129#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
3130#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
3131#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
3132#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
3133#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
3134#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
3135#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
3136#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
3137#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
3138#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
3139#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
3140#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
3141#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
3142#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
3143#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
3144#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
3145#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
3146#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
3147#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
3148#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
3149#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
3150#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
3151#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
3152#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
3153#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
3154#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
3155#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
3156#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
3157#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
3158#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
3159#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
3160#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
3161#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
3162#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
3163#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
3164#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
3165#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
3166
3167/* Counter Registers */
3168
3169#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
3170#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
3171#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
3172#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
3173#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
3174#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
3175#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
3176#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
3177#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
3178#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
3179#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
3180#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
3181#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
3182#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
3183#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
3184#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
3185
3186/* RSI Register */
3187#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
3188#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
3189#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
3190#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
3191#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
3192#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
3193#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
3194#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
3195#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
3196#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
3197#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
3198#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
3199#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
3200#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
3201#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
3202#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
3203#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
3204#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
3205#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
3206#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
3207#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
3208#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
3209#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
3210#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
3211#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
3212#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
3213#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
3214#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
3215#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
3216#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
3217#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
3218#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
3219#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
3220#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
3221#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
3222#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
3223#define bfin_read_RSI_BLKSZ() bfin_read16(RSI_BLKSZ)
3224#define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val)
3225#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
3226#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
3227#define bfin_read_RSI_E_STATUS() bfin_read32(RSI_ESTAT)
3228#define bfin_write_RSI_E_STATUS(val) bfin_write32(RSI_ESTAT, val)
3229#define bfin_read_RSI_E_MASK() bfin_read32(RSI_EMASK)
3230#define bfin_write_RSI_E_MASK(val) bfin_write32(RSI_EMASK, val)
3231#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
3232#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
3233#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
3234#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
3235#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
3236#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
3237#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
3238#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
3239#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
3240#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
3241#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
3242#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
3243
3244/* usb register */
3245#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLL_OSC)
3246#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
3247#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
3248#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
3249#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
3250
3251#endif /* _CDEF_BF60X_H */
3252
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF609.h b/arch/blackfin/mach-bf609/include/mach/defBF609.h
new file mode 100644
index 000000000000..60855382762f
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/defBF609.h
@@ -0,0 +1,15 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */
6
7#ifndef _DEF_BF609_H
8#define _DEF_BF609_H
9
10/* Include defBF60x_base.h for the set of #defines that are common to all ADSP-BF60x processors */
11#include "defBF60x_base.h"
12
13/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
14
15#endif /* _DEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
new file mode 100644
index 000000000000..60ebf5ac5350
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
@@ -0,0 +1,3587 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */
6
7#ifndef _DEF_BF60X_H
8#define _DEF_BF60X_H
9
10
11/* ************************************************************** */
12/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */
13/* ************************************************************** */
14
15
16/* =========================
17 CNT Registers
18 ========================= */
19
20/* =========================
21 CNT0
22 ========================= */
23#define CNT_CONFIG 0xFFC00400 /* CNT0 Configuration Register */
24#define CNT_IMASK 0xFFC00404 /* CNT0 Interrupt Mask Register */
25#define CNT_STATUS 0xFFC00408 /* CNT0 Status Register */
26#define CNT_COMMAND 0xFFC0040C /* CNT0 Command Register */
27#define CNT_DEBOUNCE 0xFFC00410 /* CNT0 Debounce Register */
28#define CNT_COUNTER 0xFFC00414 /* CNT0 Counter Register */
29#define CNT_MAX 0xFFC00418 /* CNT0 Maximum Count Register */
30#define CNT_MIN 0xFFC0041C /* CNT0 Minimum Count Register */
31
32
33/* =========================
34 RSI Registers
35 ========================= */
36
37#define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */
38#define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */
39#define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */
40#define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */
41#define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */
42#define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */
43#define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */
44#define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */
45#define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */
46#define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */
47#define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */
48#define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */
49#define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */
50#define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */
51#define RSI_MASK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */
52#define RSI_MASK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */
53#define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */
54#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 This register contains bit to dis CCS gen */
55#define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */
56#define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Acknowledge Timeout Register */
57#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */
58#define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */
59#define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */
60#define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */
61#define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */
62#define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */
63#define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */
64#define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Identification Register */
65#define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Identification Register */
66#define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Identification Register */
67#define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Identification Register */
68
69/* =========================
70 CAN Registers
71 ========================= */
72
73/* =========================
74 CAN0
75 ========================= */
76#define CAN0_MC1 0xFFC00A00 /* CAN0 Mailbox Configuration Register 1 */
77#define CAN0_MD1 0xFFC00A04 /* CAN0 Mailbox Direction Register 1 */
78#define CAN0_TRS1 0xFFC00A08 /* CAN0 Transmission Request Set Register 1 */
79#define CAN0_TRR1 0xFFC00A0C /* CAN0 Transmission Request Reset Register 1 */
80#define CAN0_TA1 0xFFC00A10 /* CAN0 Transmission Acknowledge Register 1 */
81#define CAN0_AA1 0xFFC00A14 /* CAN0 Abort Acknowledge Register 1 */
82#define CAN0_RMP1 0xFFC00A18 /* CAN0 Receive Message Pending Register 1 */
83#define CAN0_RML1 0xFFC00A1C /* CAN0 Receive Message Lost Register 1 */
84#define CAN0_MBTIF1 0xFFC00A20 /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */
85#define CAN0_MBRIF1 0xFFC00A24 /* CAN0 Mailbox Receive Interrupt Flag Register 1 */
86#define CAN0_MBIM1 0xFFC00A28 /* CAN0 Mailbox Interrupt Mask Register 1 */
87#define CAN0_RFH1 0xFFC00A2C /* CAN0 Remote Frame Handling Register 1 */
88#define CAN0_OPSS1 0xFFC00A30 /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */
89#define CAN0_MC2 0xFFC00A40 /* CAN0 Mailbox Configuration Register 2 */
90#define CAN0_MD2 0xFFC00A44 /* CAN0 Mailbox Direction Register 2 */
91#define CAN0_TRS2 0xFFC00A48 /* CAN0 Transmission Request Set Register 2 */
92#define CAN0_TRR2 0xFFC00A4C /* CAN0 Transmission Request Reset Register 2 */
93#define CAN0_TA2 0xFFC00A50 /* CAN0 Transmission Acknowledge Register 2 */
94#define CAN0_AA2 0xFFC00A54 /* CAN0 Abort Acknowledge Register 2 */
95#define CAN0_RMP2 0xFFC00A58 /* CAN0 Receive Message Pending Register 2 */
96#define CAN0_RML2 0xFFC00A5C /* CAN0 Receive Message Lost Register 2 */
97#define CAN0_MBTIF2 0xFFC00A60 /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */
98#define CAN0_MBRIF2 0xFFC00A64 /* CAN0 Mailbox Receive Interrupt Flag Register 2 */
99#define CAN0_MBIM2 0xFFC00A68 /* CAN0 Mailbox Interrupt Mask Register 2 */
100#define CAN0_RFH2 0xFFC00A6C /* CAN0 Remote Frame Handling Register 2 */
101#define CAN0_OPSS2 0xFFC00A70 /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */
102#define CAN0_CLOCK 0xFFC00A80 /* CAN0 Clock Register */
103#define CAN0_TIMING 0xFFC00A84 /* CAN0 Timing Register */
104#define CAN0_DEBUG 0xFFC00A88 /* CAN0 Debug Register */
105#define CAN0_STATUS 0xFFC00A8C /* CAN0 Status Register */
106#define CAN0_CEC 0xFFC00A90 /* CAN0 Error Counter Register */
107#define CAN0_GIS 0xFFC00A94 /* CAN0 Global CAN Interrupt Status */
108#define CAN0_GIM 0xFFC00A98 /* CAN0 Global CAN Interrupt Mask */
109#define CAN0_GIF 0xFFC00A9C /* CAN0 Global CAN Interrupt Flag */
110#define CAN0_CONTROL 0xFFC00AA0 /* CAN0 CAN Master Control Register */
111#define CAN0_INTR 0xFFC00AA4 /* CAN0 Interrupt Pending Register */
112#define CAN0_MBTD 0xFFC00AAC /* CAN0 Temporary Mailbox Disable Register */
113#define CAN0_EWR 0xFFC00AB0 /* CAN0 Error Counter Warning Level Register */
114#define CAN0_ESR 0xFFC00AB4 /* CAN0 Error Status Register */
115#define CAN0_UCCNT 0xFFC00AC4 /* CAN0 Universal Counter Register */
116#define CAN0_UCRC 0xFFC00AC8 /* CAN0 Universal Counter Reload/Capture Register */
117#define CAN0_UCCNF 0xFFC00ACC /* CAN0 Universal Counter Configuration Mode Register */
118#define CAN0_AM00L 0xFFC00B00 /* CAN0 Acceptance Mask Register (L) */
119#define CAN0_AM01L 0xFFC00B08 /* CAN0 Acceptance Mask Register (L) */
120#define CAN0_AM02L 0xFFC00B10 /* CAN0 Acceptance Mask Register (L) */
121#define CAN0_AM03L 0xFFC00B18 /* CAN0 Acceptance Mask Register (L) */
122#define CAN0_AM04L 0xFFC00B20 /* CAN0 Acceptance Mask Register (L) */
123#define CAN0_AM05L 0xFFC00B28 /* CAN0 Acceptance Mask Register (L) */
124#define CAN0_AM06L 0xFFC00B30 /* CAN0 Acceptance Mask Register (L) */
125#define CAN0_AM07L 0xFFC00B38 /* CAN0 Acceptance Mask Register (L) */
126#define CAN0_AM08L 0xFFC00B40 /* CAN0 Acceptance Mask Register (L) */
127#define CAN0_AM09L 0xFFC00B48 /* CAN0 Acceptance Mask Register (L) */
128#define CAN0_AM10L 0xFFC00B50 /* CAN0 Acceptance Mask Register (L) */
129#define CAN0_AM11L 0xFFC00B58 /* CAN0 Acceptance Mask Register (L) */
130#define CAN0_AM12L 0xFFC00B60 /* CAN0 Acceptance Mask Register (L) */
131#define CAN0_AM13L 0xFFC00B68 /* CAN0 Acceptance Mask Register (L) */
132#define CAN0_AM14L 0xFFC00B70 /* CAN0 Acceptance Mask Register (L) */
133#define CAN0_AM15L 0xFFC00B78 /* CAN0 Acceptance Mask Register (L) */
134#define CAN0_AM16L 0xFFC00B80 /* CAN0 Acceptance Mask Register (L) */
135#define CAN0_AM17L 0xFFC00B88 /* CAN0 Acceptance Mask Register (L) */
136#define CAN0_AM18L 0xFFC00B90 /* CAN0 Acceptance Mask Register (L) */
137#define CAN0_AM19L 0xFFC00B98 /* CAN0 Acceptance Mask Register (L) */
138#define CAN0_AM20L 0xFFC00BA0 /* CAN0 Acceptance Mask Register (L) */
139#define CAN0_AM21L 0xFFC00BA8 /* CAN0 Acceptance Mask Register (L) */
140#define CAN0_AM22L 0xFFC00BB0 /* CAN0 Acceptance Mask Register (L) */
141#define CAN0_AM23L 0xFFC00BB8 /* CAN0 Acceptance Mask Register (L) */
142#define CAN0_AM24L 0xFFC00BC0 /* CAN0 Acceptance Mask Register (L) */
143#define CAN0_AM25L 0xFFC00BC8 /* CAN0 Acceptance Mask Register (L) */
144#define CAN0_AM26L 0xFFC00BD0 /* CAN0 Acceptance Mask Register (L) */
145#define CAN0_AM27L 0xFFC00BD8 /* CAN0 Acceptance Mask Register (L) */
146#define CAN0_AM28L 0xFFC00BE0 /* CAN0 Acceptance Mask Register (L) */
147#define CAN0_AM29L 0xFFC00BE8 /* CAN0 Acceptance Mask Register (L) */
148#define CAN0_AM30L 0xFFC00BF0 /* CAN0 Acceptance Mask Register (L) */
149#define CAN0_AM31L 0xFFC00BF8 /* CAN0 Acceptance Mask Register (L) */
150#define CAN0_AM00H 0xFFC00B04 /* CAN0 Acceptance Mask Register (H) */
151#define CAN0_AM01H 0xFFC00B0C /* CAN0 Acceptance Mask Register (H) */
152#define CAN0_AM02H 0xFFC00B14 /* CAN0 Acceptance Mask Register (H) */
153#define CAN0_AM03H 0xFFC00B1C /* CAN0 Acceptance Mask Register (H) */
154#define CAN0_AM04H 0xFFC00B24 /* CAN0 Acceptance Mask Register (H) */
155#define CAN0_AM05H 0xFFC00B2C /* CAN0 Acceptance Mask Register (H) */
156#define CAN0_AM06H 0xFFC00B34 /* CAN0 Acceptance Mask Register (H) */
157#define CAN0_AM07H 0xFFC00B3C /* CAN0 Acceptance Mask Register (H) */
158#define CAN0_AM08H 0xFFC00B44 /* CAN0 Acceptance Mask Register (H) */
159#define CAN0_AM09H 0xFFC00B4C /* CAN0 Acceptance Mask Register (H) */
160#define CAN0_AM10H 0xFFC00B54 /* CAN0 Acceptance Mask Register (H) */
161#define CAN0_AM11H 0xFFC00B5C /* CAN0 Acceptance Mask Register (H) */
162#define CAN0_AM12H 0xFFC00B64 /* CAN0 Acceptance Mask Register (H) */
163#define CAN0_AM13H 0xFFC00B6C /* CAN0 Acceptance Mask Register (H) */
164#define CAN0_AM14H 0xFFC00B74 /* CAN0 Acceptance Mask Register (H) */
165#define CAN0_AM15H 0xFFC00B7C /* CAN0 Acceptance Mask Register (H) */
166#define CAN0_AM16H 0xFFC00B84 /* CAN0 Acceptance Mask Register (H) */
167#define CAN0_AM17H 0xFFC00B8C /* CAN0 Acceptance Mask Register (H) */
168#define CAN0_AM18H 0xFFC00B94 /* CAN0 Acceptance Mask Register (H) */
169#define CAN0_AM19H 0xFFC00B9C /* CAN0 Acceptance Mask Register (H) */
170#define CAN0_AM20H 0xFFC00BA4 /* CAN0 Acceptance Mask Register (H) */
171#define CAN0_AM21H 0xFFC00BAC /* CAN0 Acceptance Mask Register (H) */
172#define CAN0_AM22H 0xFFC00BB4 /* CAN0 Acceptance Mask Register (H) */
173#define CAN0_AM23H 0xFFC00BBC /* CAN0 Acceptance Mask Register (H) */
174#define CAN0_AM24H 0xFFC00BC4 /* CAN0 Acceptance Mask Register (H) */
175#define CAN0_AM25H 0xFFC00BCC /* CAN0 Acceptance Mask Register (H) */
176#define CAN0_AM26H 0xFFC00BD4 /* CAN0 Acceptance Mask Register (H) */
177#define CAN0_AM27H 0xFFC00BDC /* CAN0 Acceptance Mask Register (H) */
178#define CAN0_AM28H 0xFFC00BE4 /* CAN0 Acceptance Mask Register (H) */
179#define CAN0_AM29H 0xFFC00BEC /* CAN0 Acceptance Mask Register (H) */
180#define CAN0_AM30H 0xFFC00BF4 /* CAN0 Acceptance Mask Register (H) */
181#define CAN0_AM31H 0xFFC00BFC /* CAN0 Acceptance Mask Register (H) */
182#define CAN0_MB00_DATA0 0xFFC00C00 /* CAN0 Mailbox Word 0 Register */
183#define CAN0_MB01_DATA0 0xFFC00C20 /* CAN0 Mailbox Word 0 Register */
184#define CAN0_MB02_DATA0 0xFFC00C40 /* CAN0 Mailbox Word 0 Register */
185#define CAN0_MB03_DATA0 0xFFC00C60 /* CAN0 Mailbox Word 0 Register */
186#define CAN0_MB04_DATA0 0xFFC00C80 /* CAN0 Mailbox Word 0 Register */
187#define CAN0_MB05_DATA0 0xFFC00CA0 /* CAN0 Mailbox Word 0 Register */
188#define CAN0_MB06_DATA0 0xFFC00CC0 /* CAN0 Mailbox Word 0 Register */
189#define CAN0_MB07_DATA0 0xFFC00CE0 /* CAN0 Mailbox Word 0 Register */
190#define CAN0_MB08_DATA0 0xFFC00D00 /* CAN0 Mailbox Word 0 Register */
191#define CAN0_MB09_DATA0 0xFFC00D20 /* CAN0 Mailbox Word 0 Register */
192#define CAN0_MB10_DATA0 0xFFC00D40 /* CAN0 Mailbox Word 0 Register */
193#define CAN0_MB11_DATA0 0xFFC00D60 /* CAN0 Mailbox Word 0 Register */
194#define CAN0_MB12_DATA0 0xFFC00D80 /* CAN0 Mailbox Word 0 Register */
195#define CAN0_MB13_DATA0 0xFFC00DA0 /* CAN0 Mailbox Word 0 Register */
196#define CAN0_MB14_DATA0 0xFFC00DC0 /* CAN0 Mailbox Word 0 Register */
197#define CAN0_MB15_DATA0 0xFFC00DE0 /* CAN0 Mailbox Word 0 Register */
198#define CAN0_MB16_DATA0 0xFFC00E00 /* CAN0 Mailbox Word 0 Register */
199#define CAN0_MB17_DATA0 0xFFC00E20 /* CAN0 Mailbox Word 0 Register */
200#define CAN0_MB18_DATA0 0xFFC00E40 /* CAN0 Mailbox Word 0 Register */
201#define CAN0_MB19_DATA0 0xFFC00E60 /* CAN0 Mailbox Word 0 Register */
202#define CAN0_MB20_DATA0 0xFFC00E80 /* CAN0 Mailbox Word 0 Register */
203#define CAN0_MB21_DATA0 0xFFC00EA0 /* CAN0 Mailbox Word 0 Register */
204#define CAN0_MB22_DATA0 0xFFC00EC0 /* CAN0 Mailbox Word 0 Register */
205#define CAN0_MB23_DATA0 0xFFC00EE0 /* CAN0 Mailbox Word 0 Register */
206#define CAN0_MB24_DATA0 0xFFC00F00 /* CAN0 Mailbox Word 0 Register */
207#define CAN0_MB25_DATA0 0xFFC00F20 /* CAN0 Mailbox Word 0 Register */
208#define CAN0_MB26_DATA0 0xFFC00F40 /* CAN0 Mailbox Word 0 Register */
209#define CAN0_MB27_DATA0 0xFFC00F60 /* CAN0 Mailbox Word 0 Register */
210#define CAN0_MB28_DATA0 0xFFC00F80 /* CAN0 Mailbox Word 0 Register */
211#define CAN0_MB29_DATA0 0xFFC00FA0 /* CAN0 Mailbox Word 0 Register */
212#define CAN0_MB30_DATA0 0xFFC00FC0 /* CAN0 Mailbox Word 0 Register */
213#define CAN0_MB31_DATA0 0xFFC00FE0 /* CAN0 Mailbox Word 0 Register */
214#define CAN0_MB00_DATA1 0xFFC00C04 /* CAN0 Mailbox Word 1 Register */
215#define CAN0_MB01_DATA1 0xFFC00C24 /* CAN0 Mailbox Word 1 Register */
216#define CAN0_MB02_DATA1 0xFFC00C44 /* CAN0 Mailbox Word 1 Register */
217#define CAN0_MB03_DATA1 0xFFC00C64 /* CAN0 Mailbox Word 1 Register */
218#define CAN0_MB04_DATA1 0xFFC00C84 /* CAN0 Mailbox Word 1 Register */
219#define CAN0_MB05_DATA1 0xFFC00CA4 /* CAN0 Mailbox Word 1 Register */
220#define CAN0_MB06_DATA1 0xFFC00CC4 /* CAN0 Mailbox Word 1 Register */
221#define CAN0_MB07_DATA1 0xFFC00CE4 /* CAN0 Mailbox Word 1 Register */
222#define CAN0_MB08_DATA1 0xFFC00D04 /* CAN0 Mailbox Word 1 Register */
223#define CAN0_MB09_DATA1 0xFFC00D24 /* CAN0 Mailbox Word 1 Register */
224#define CAN0_MB10_DATA1 0xFFC00D44 /* CAN0 Mailbox Word 1 Register */
225#define CAN0_MB11_DATA1 0xFFC00D64 /* CAN0 Mailbox Word 1 Register */
226#define CAN0_MB12_DATA1 0xFFC00D84 /* CAN0 Mailbox Word 1 Register */
227#define CAN0_MB13_DATA1 0xFFC00DA4 /* CAN0 Mailbox Word 1 Register */
228#define CAN0_MB14_DATA1 0xFFC00DC4 /* CAN0 Mailbox Word 1 Register */
229#define CAN0_MB15_DATA1 0xFFC00DE4 /* CAN0 Mailbox Word 1 Register */
230#define CAN0_MB16_DATA1 0xFFC00E04 /* CAN0 Mailbox Word 1 Register */
231#define CAN0_MB17_DATA1 0xFFC00E24 /* CAN0 Mailbox Word 1 Register */
232#define CAN0_MB18_DATA1 0xFFC00E44 /* CAN0 Mailbox Word 1 Register */
233#define CAN0_MB19_DATA1 0xFFC00E64 /* CAN0 Mailbox Word 1 Register */
234#define CAN0_MB20_DATA1 0xFFC00E84 /* CAN0 Mailbox Word 1 Register */
235#define CAN0_MB21_DATA1 0xFFC00EA4 /* CAN0 Mailbox Word 1 Register */
236#define CAN0_MB22_DATA1 0xFFC00EC4 /* CAN0 Mailbox Word 1 Register */
237#define CAN0_MB23_DATA1 0xFFC00EE4 /* CAN0 Mailbox Word 1 Register */
238#define CAN0_MB24_DATA1 0xFFC00F04 /* CAN0 Mailbox Word 1 Register */
239#define CAN0_MB25_DATA1 0xFFC00F24 /* CAN0 Mailbox Word 1 Register */
240#define CAN0_MB26_DATA1 0xFFC00F44 /* CAN0 Mailbox Word 1 Register */
241#define CAN0_MB27_DATA1 0xFFC00F64 /* CAN0 Mailbox Word 1 Register */
242#define CAN0_MB28_DATA1 0xFFC00F84 /* CAN0 Mailbox Word 1 Register */
243#define CAN0_MB29_DATA1 0xFFC00FA4 /* CAN0 Mailbox Word 1 Register */
244#define CAN0_MB30_DATA1 0xFFC00FC4 /* CAN0 Mailbox Word 1 Register */
245#define CAN0_MB31_DATA1 0xFFC00FE4 /* CAN0 Mailbox Word 1 Register */
246#define CAN0_MB00_DATA2 0xFFC00C08 /* CAN0 Mailbox Word 2 Register */
247#define CAN0_MB01_DATA2 0xFFC00C28 /* CAN0 Mailbox Word 2 Register */
248#define CAN0_MB02_DATA2 0xFFC00C48 /* CAN0 Mailbox Word 2 Register */
249#define CAN0_MB03_DATA2 0xFFC00C68 /* CAN0 Mailbox Word 2 Register */
250#define CAN0_MB04_DATA2 0xFFC00C88 /* CAN0 Mailbox Word 2 Register */
251#define CAN0_MB05_DATA2 0xFFC00CA8 /* CAN0 Mailbox Word 2 Register */
252#define CAN0_MB06_DATA2 0xFFC00CC8 /* CAN0 Mailbox Word 2 Register */
253#define CAN0_MB07_DATA2 0xFFC00CE8 /* CAN0 Mailbox Word 2 Register */
254#define CAN0_MB08_DATA2 0xFFC00D08 /* CAN0 Mailbox Word 2 Register */
255#define CAN0_MB09_DATA2 0xFFC00D28 /* CAN0 Mailbox Word 2 Register */
256#define CAN0_MB10_DATA2 0xFFC00D48 /* CAN0 Mailbox Word 2 Register */
257#define CAN0_MB11_DATA2 0xFFC00D68 /* CAN0 Mailbox Word 2 Register */
258#define CAN0_MB12_DATA2 0xFFC00D88 /* CAN0 Mailbox Word 2 Register */
259#define CAN0_MB13_DATA2 0xFFC00DA8 /* CAN0 Mailbox Word 2 Register */
260#define CAN0_MB14_DATA2 0xFFC00DC8 /* CAN0 Mailbox Word 2 Register */
261#define CAN0_MB15_DATA2 0xFFC00DE8 /* CAN0 Mailbox Word 2 Register */
262#define CAN0_MB16_DATA2 0xFFC00E08 /* CAN0 Mailbox Word 2 Register */
263#define CAN0_MB17_DATA2 0xFFC00E28 /* CAN0 Mailbox Word 2 Register */
264#define CAN0_MB18_DATA2 0xFFC00E48 /* CAN0 Mailbox Word 2 Register */
265#define CAN0_MB19_DATA2 0xFFC00E68 /* CAN0 Mailbox Word 2 Register */
266#define CAN0_MB20_DATA2 0xFFC00E88 /* CAN0 Mailbox Word 2 Register */
267#define CAN0_MB21_DATA2 0xFFC00EA8 /* CAN0 Mailbox Word 2 Register */
268#define CAN0_MB22_DATA2 0xFFC00EC8 /* CAN0 Mailbox Word 2 Register */
269#define CAN0_MB23_DATA2 0xFFC00EE8 /* CAN0 Mailbox Word 2 Register */
270#define CAN0_MB24_DATA2 0xFFC00F08 /* CAN0 Mailbox Word 2 Register */
271#define CAN0_MB25_DATA2 0xFFC00F28 /* CAN0 Mailbox Word 2 Register */
272#define CAN0_MB26_DATA2 0xFFC00F48 /* CAN0 Mailbox Word 2 Register */
273#define CAN0_MB27_DATA2 0xFFC00F68 /* CAN0 Mailbox Word 2 Register */
274#define CAN0_MB28_DATA2 0xFFC00F88 /* CAN0 Mailbox Word 2 Register */
275#define CAN0_MB29_DATA2 0xFFC00FA8 /* CAN0 Mailbox Word 2 Register */
276#define CAN0_MB30_DATA2 0xFFC00FC8 /* CAN0 Mailbox Word 2 Register */
277#define CAN0_MB31_DATA2 0xFFC00FE8 /* CAN0 Mailbox Word 2 Register */
278#define CAN0_MB00_DATA3 0xFFC00C0C /* CAN0 Mailbox Word 3 Register */
279#define CAN0_MB01_DATA3 0xFFC00C2C /* CAN0 Mailbox Word 3 Register */
280#define CAN0_MB02_DATA3 0xFFC00C4C /* CAN0 Mailbox Word 3 Register */
281#define CAN0_MB03_DATA3 0xFFC00C6C /* CAN0 Mailbox Word 3 Register */
282#define CAN0_MB04_DATA3 0xFFC00C8C /* CAN0 Mailbox Word 3 Register */
283#define CAN0_MB05_DATA3 0xFFC00CAC /* CAN0 Mailbox Word 3 Register */
284#define CAN0_MB06_DATA3 0xFFC00CCC /* CAN0 Mailbox Word 3 Register */
285#define CAN0_MB07_DATA3 0xFFC00CEC /* CAN0 Mailbox Word 3 Register */
286#define CAN0_MB08_DATA3 0xFFC00D0C /* CAN0 Mailbox Word 3 Register */
287#define CAN0_MB09_DATA3 0xFFC00D2C /* CAN0 Mailbox Word 3 Register */
288#define CAN0_MB10_DATA3 0xFFC00D4C /* CAN0 Mailbox Word 3 Register */
289#define CAN0_MB11_DATA3 0xFFC00D6C /* CAN0 Mailbox Word 3 Register */
290#define CAN0_MB12_DATA3 0xFFC00D8C /* CAN0 Mailbox Word 3 Register */
291#define CAN0_MB13_DATA3 0xFFC00DAC /* CAN0 Mailbox Word 3 Register */
292#define CAN0_MB14_DATA3 0xFFC00DCC /* CAN0 Mailbox Word 3 Register */
293#define CAN0_MB15_DATA3 0xFFC00DEC /* CAN0 Mailbox Word 3 Register */
294#define CAN0_MB16_DATA3 0xFFC00E0C /* CAN0 Mailbox Word 3 Register */
295#define CAN0_MB17_DATA3 0xFFC00E2C /* CAN0 Mailbox Word 3 Register */
296#define CAN0_MB18_DATA3 0xFFC00E4C /* CAN0 Mailbox Word 3 Register */
297#define CAN0_MB19_DATA3 0xFFC00E6C /* CAN0 Mailbox Word 3 Register */
298#define CAN0_MB20_DATA3 0xFFC00E8C /* CAN0 Mailbox Word 3 Register */
299#define CAN0_MB21_DATA3 0xFFC00EAC /* CAN0 Mailbox Word 3 Register */
300#define CAN0_MB22_DATA3 0xFFC00ECC /* CAN0 Mailbox Word 3 Register */
301#define CAN0_MB23_DATA3 0xFFC00EEC /* CAN0 Mailbox Word 3 Register */
302#define CAN0_MB24_DATA3 0xFFC00F0C /* CAN0 Mailbox Word 3 Register */
303#define CAN0_MB25_DATA3 0xFFC00F2C /* CAN0 Mailbox Word 3 Register */
304#define CAN0_MB26_DATA3 0xFFC00F4C /* CAN0 Mailbox Word 3 Register */
305#define CAN0_MB27_DATA3 0xFFC00F6C /* CAN0 Mailbox Word 3 Register */
306#define CAN0_MB28_DATA3 0xFFC00F8C /* CAN0 Mailbox Word 3 Register */
307#define CAN0_MB29_DATA3 0xFFC00FAC /* CAN0 Mailbox Word 3 Register */
308#define CAN0_MB30_DATA3 0xFFC00FCC /* CAN0 Mailbox Word 3 Register */
309#define CAN0_MB31_DATA3 0xFFC00FEC /* CAN0 Mailbox Word 3 Register */
310#define CAN0_MB00_LENGTH 0xFFC00C10 /* CAN0 Mailbox Word 4 Register */
311#define CAN0_MB01_LENGTH 0xFFC00C30 /* CAN0 Mailbox Word 4 Register */
312#define CAN0_MB02_LENGTH 0xFFC00C50 /* CAN0 Mailbox Word 4 Register */
313#define CAN0_MB03_LENGTH 0xFFC00C70 /* CAN0 Mailbox Word 4 Register */
314#define CAN0_MB04_LENGTH 0xFFC00C90 /* CAN0 Mailbox Word 4 Register */
315#define CAN0_MB05_LENGTH 0xFFC00CB0 /* CAN0 Mailbox Word 4 Register */
316#define CAN0_MB06_LENGTH 0xFFC00CD0 /* CAN0 Mailbox Word 4 Register */
317#define CAN0_MB07_LENGTH 0xFFC00CF0 /* CAN0 Mailbox Word 4 Register */
318#define CAN0_MB08_LENGTH 0xFFC00D10 /* CAN0 Mailbox Word 4 Register */
319#define CAN0_MB09_LENGTH 0xFFC00D30 /* CAN0 Mailbox Word 4 Register */
320#define CAN0_MB10_LENGTH 0xFFC00D50 /* CAN0 Mailbox Word 4 Register */
321#define CAN0_MB11_LENGTH 0xFFC00D70 /* CAN0 Mailbox Word 4 Register */
322#define CAN0_MB12_LENGTH 0xFFC00D90 /* CAN0 Mailbox Word 4 Register */
323#define CAN0_MB13_LENGTH 0xFFC00DB0 /* CAN0 Mailbox Word 4 Register */
324#define CAN0_MB14_LENGTH 0xFFC00DD0 /* CAN0 Mailbox Word 4 Register */
325#define CAN0_MB15_LENGTH 0xFFC00DF0 /* CAN0 Mailbox Word 4 Register */
326#define CAN0_MB16_LENGTH 0xFFC00E10 /* CAN0 Mailbox Word 4 Register */
327#define CAN0_MB17_LENGTH 0xFFC00E30 /* CAN0 Mailbox Word 4 Register */
328#define CAN0_MB18_LENGTH 0xFFC00E50 /* CAN0 Mailbox Word 4 Register */
329#define CAN0_MB19_LENGTH 0xFFC00E70 /* CAN0 Mailbox Word 4 Register */
330#define CAN0_MB20_LENGTH 0xFFC00E90 /* CAN0 Mailbox Word 4 Register */
331#define CAN0_MB21_LENGTH 0xFFC00EB0 /* CAN0 Mailbox Word 4 Register */
332#define CAN0_MB22_LENGTH 0xFFC00ED0 /* CAN0 Mailbox Word 4 Register */
333#define CAN0_MB23_LENGTH 0xFFC00EF0 /* CAN0 Mailbox Word 4 Register */
334#define CAN0_MB24_LENGTH 0xFFC00F10 /* CAN0 Mailbox Word 4 Register */
335#define CAN0_MB25_LENGTH 0xFFC00F30 /* CAN0 Mailbox Word 4 Register */
336#define CAN0_MB26_LENGTH 0xFFC00F50 /* CAN0 Mailbox Word 4 Register */
337#define CAN0_MB27_LENGTH 0xFFC00F70 /* CAN0 Mailbox Word 4 Register */
338#define CAN0_MB28_LENGTH 0xFFC00F90 /* CAN0 Mailbox Word 4 Register */
339#define CAN0_MB29_LENGTH 0xFFC00FB0 /* CAN0 Mailbox Word 4 Register */
340#define CAN0_MB30_LENGTH 0xFFC00FD0 /* CAN0 Mailbox Word 4 Register */
341#define CAN0_MB31_LENGTH 0xFFC00FF0 /* CAN0 Mailbox Word 4 Register */
342#define CAN0_MB00_TIMESTAMP 0xFFC00C14 /* CAN0 Mailbox Word 5 Register */
343#define CAN0_MB01_TIMESTAMP 0xFFC00C34 /* CAN0 Mailbox Word 5 Register */
344#define CAN0_MB02_TIMESTAMP 0xFFC00C54 /* CAN0 Mailbox Word 5 Register */
345#define CAN0_MB03_TIMESTAMP 0xFFC00C74 /* CAN0 Mailbox Word 5 Register */
346#define CAN0_MB04_TIMESTAMP 0xFFC00C94 /* CAN0 Mailbox Word 5 Register */
347#define CAN0_MB05_TIMESTAMP 0xFFC00CB4 /* CAN0 Mailbox Word 5 Register */
348#define CAN0_MB06_TIMESTAMP 0xFFC00CD4 /* CAN0 Mailbox Word 5 Register */
349#define CAN0_MB07_TIMESTAMP 0xFFC00CF4 /* CAN0 Mailbox Word 5 Register */
350#define CAN0_MB08_TIMESTAMP 0xFFC00D14 /* CAN0 Mailbox Word 5 Register */
351#define CAN0_MB09_TIMESTAMP 0xFFC00D34 /* CAN0 Mailbox Word 5 Register */
352#define CAN0_MB10_TIMESTAMP 0xFFC00D54 /* CAN0 Mailbox Word 5 Register */
353#define CAN0_MB11_TIMESTAMP 0xFFC00D74 /* CAN0 Mailbox Word 5 Register */
354#define CAN0_MB12_TIMESTAMP 0xFFC00D94 /* CAN0 Mailbox Word 5 Register */
355#define CAN0_MB13_TIMESTAMP 0xFFC00DB4 /* CAN0 Mailbox Word 5 Register */
356#define CAN0_MB14_TIMESTAMP 0xFFC00DD4 /* CAN0 Mailbox Word 5 Register */
357#define CAN0_MB15_TIMESTAMP 0xFFC00DF4 /* CAN0 Mailbox Word 5 Register */
358#define CAN0_MB16_TIMESTAMP 0xFFC00E14 /* CAN0 Mailbox Word 5 Register */
359#define CAN0_MB17_TIMESTAMP 0xFFC00E34 /* CAN0 Mailbox Word 5 Register */
360#define CAN0_MB18_TIMESTAMP 0xFFC00E54 /* CAN0 Mailbox Word 5 Register */
361#define CAN0_MB19_TIMESTAMP 0xFFC00E74 /* CAN0 Mailbox Word 5 Register */
362#define CAN0_MB20_TIMESTAMP 0xFFC00E94 /* CAN0 Mailbox Word 5 Register */
363#define CAN0_MB21_TIMESTAMP 0xFFC00EB4 /* CAN0 Mailbox Word 5 Register */
364#define CAN0_MB22_TIMESTAMP 0xFFC00ED4 /* CAN0 Mailbox Word 5 Register */
365#define CAN0_MB23_TIMESTAMP 0xFFC00EF4 /* CAN0 Mailbox Word 5 Register */
366#define CAN0_MB24_TIMESTAMP 0xFFC00F14 /* CAN0 Mailbox Word 5 Register */
367#define CAN0_MB25_TIMESTAMP 0xFFC00F34 /* CAN0 Mailbox Word 5 Register */
368#define CAN0_MB26_TIMESTAMP 0xFFC00F54 /* CAN0 Mailbox Word 5 Register */
369#define CAN0_MB27_TIMESTAMP 0xFFC00F74 /* CAN0 Mailbox Word 5 Register */
370#define CAN0_MB28_TIMESTAMP 0xFFC00F94 /* CAN0 Mailbox Word 5 Register */
371#define CAN0_MB29_TIMESTAMP 0xFFC00FB4 /* CAN0 Mailbox Word 5 Register */
372#define CAN0_MB30_TIMESTAMP 0xFFC00FD4 /* CAN0 Mailbox Word 5 Register */
373#define CAN0_MB31_TIMESTAMP 0xFFC00FF4 /* CAN0 Mailbox Word 5 Register */
374#define CAN0_MB00_ID0 0xFFC00C18 /* CAN0 Mailbox Word 6 Register */
375#define CAN0_MB01_ID0 0xFFC00C38 /* CAN0 Mailbox Word 6 Register */
376#define CAN0_MB02_ID0 0xFFC00C58 /* CAN0 Mailbox Word 6 Register */
377#define CAN0_MB03_ID0 0xFFC00C78 /* CAN0 Mailbox Word 6 Register */
378#define CAN0_MB04_ID0 0xFFC00C98 /* CAN0 Mailbox Word 6 Register */
379#define CAN0_MB05_ID0 0xFFC00CB8 /* CAN0 Mailbox Word 6 Register */
380#define CAN0_MB06_ID0 0xFFC00CD8 /* CAN0 Mailbox Word 6 Register */
381#define CAN0_MB07_ID0 0xFFC00CF8 /* CAN0 Mailbox Word 6 Register */
382#define CAN0_MB08_ID0 0xFFC00D18 /* CAN0 Mailbox Word 6 Register */
383#define CAN0_MB09_ID0 0xFFC00D38 /* CAN0 Mailbox Word 6 Register */
384#define CAN0_MB10_ID0 0xFFC00D58 /* CAN0 Mailbox Word 6 Register */
385#define CAN0_MB11_ID0 0xFFC00D78 /* CAN0 Mailbox Word 6 Register */
386#define CAN0_MB12_ID0 0xFFC00D98 /* CAN0 Mailbox Word 6 Register */
387#define CAN0_MB13_ID0 0xFFC00DB8 /* CAN0 Mailbox Word 6 Register */
388#define CAN0_MB14_ID0 0xFFC00DD8 /* CAN0 Mailbox Word 6 Register */
389#define CAN0_MB15_ID0 0xFFC00DF8 /* CAN0 Mailbox Word 6 Register */
390#define CAN0_MB16_ID0 0xFFC00E18 /* CAN0 Mailbox Word 6 Register */
391#define CAN0_MB17_ID0 0xFFC00E38 /* CAN0 Mailbox Word 6 Register */
392#define CAN0_MB18_ID0 0xFFC00E58 /* CAN0 Mailbox Word 6 Register */
393#define CAN0_MB19_ID0 0xFFC00E78 /* CAN0 Mailbox Word 6 Register */
394#define CAN0_MB20_ID0 0xFFC00E98 /* CAN0 Mailbox Word 6 Register */
395#define CAN0_MB21_ID0 0xFFC00EB8 /* CAN0 Mailbox Word 6 Register */
396#define CAN0_MB22_ID0 0xFFC00ED8 /* CAN0 Mailbox Word 6 Register */
397#define CAN0_MB23_ID0 0xFFC00EF8 /* CAN0 Mailbox Word 6 Register */
398#define CAN0_MB24_ID0 0xFFC00F18 /* CAN0 Mailbox Word 6 Register */
399#define CAN0_MB25_ID0 0xFFC00F38 /* CAN0 Mailbox Word 6 Register */
400#define CAN0_MB26_ID0 0xFFC00F58 /* CAN0 Mailbox Word 6 Register */
401#define CAN0_MB27_ID0 0xFFC00F78 /* CAN0 Mailbox Word 6 Register */
402#define CAN0_MB28_ID0 0xFFC00F98 /* CAN0 Mailbox Word 6 Register */
403#define CAN0_MB29_ID0 0xFFC00FB8 /* CAN0 Mailbox Word 6 Register */
404#define CAN0_MB30_ID0 0xFFC00FD8 /* CAN0 Mailbox Word 6 Register */
405#define CAN0_MB31_ID0 0xFFC00FF8 /* CAN0 Mailbox Word 6 Register */
406#define CAN0_MB00_ID1 0xFFC00C1C /* CAN0 Mailbox Word 7 Register */
407#define CAN0_MB01_ID1 0xFFC00C3C /* CAN0 Mailbox Word 7 Register */
408#define CAN0_MB02_ID1 0xFFC00C5C /* CAN0 Mailbox Word 7 Register */
409#define CAN0_MB03_ID1 0xFFC00C7C /* CAN0 Mailbox Word 7 Register */
410#define CAN0_MB04_ID1 0xFFC00C9C /* CAN0 Mailbox Word 7 Register */
411#define CAN0_MB05_ID1 0xFFC00CBC /* CAN0 Mailbox Word 7 Register */
412#define CAN0_MB06_ID1 0xFFC00CDC /* CAN0 Mailbox Word 7 Register */
413#define CAN0_MB07_ID1 0xFFC00CFC /* CAN0 Mailbox Word 7 Register */
414#define CAN0_MB08_ID1 0xFFC00D1C /* CAN0 Mailbox Word 7 Register */
415#define CAN0_MB09_ID1 0xFFC00D3C /* CAN0 Mailbox Word 7 Register */
416#define CAN0_MB10_ID1 0xFFC00D5C /* CAN0 Mailbox Word 7 Register */
417#define CAN0_MB11_ID1 0xFFC00D7C /* CAN0 Mailbox Word 7 Register */
418#define CAN0_MB12_ID1 0xFFC00D9C /* CAN0 Mailbox Word 7 Register */
419#define CAN0_MB13_ID1 0xFFC00DBC /* CAN0 Mailbox Word 7 Register */
420#define CAN0_MB14_ID1 0xFFC00DDC /* CAN0 Mailbox Word 7 Register */
421#define CAN0_MB15_ID1 0xFFC00DFC /* CAN0 Mailbox Word 7 Register */
422#define CAN0_MB16_ID1 0xFFC00E1C /* CAN0 Mailbox Word 7 Register */
423#define CAN0_MB17_ID1 0xFFC00E3C /* CAN0 Mailbox Word 7 Register */
424#define CAN0_MB18_ID1 0xFFC00E5C /* CAN0 Mailbox Word 7 Register */
425#define CAN0_MB19_ID1 0xFFC00E7C /* CAN0 Mailbox Word 7 Register */
426#define CAN0_MB20_ID1 0xFFC00E9C /* CAN0 Mailbox Word 7 Register */
427#define CAN0_MB21_ID1 0xFFC00EBC /* CAN0 Mailbox Word 7 Register */
428#define CAN0_MB22_ID1 0xFFC00EDC /* CAN0 Mailbox Word 7 Register */
429#define CAN0_MB23_ID1 0xFFC00EFC /* CAN0 Mailbox Word 7 Register */
430#define CAN0_MB24_ID1 0xFFC00F1C /* CAN0 Mailbox Word 7 Register */
431#define CAN0_MB25_ID1 0xFFC00F3C /* CAN0 Mailbox Word 7 Register */
432#define CAN0_MB26_ID1 0xFFC00F5C /* CAN0 Mailbox Word 7 Register */
433#define CAN0_MB27_ID1 0xFFC00F7C /* CAN0 Mailbox Word 7 Register */
434#define CAN0_MB28_ID1 0xFFC00F9C /* CAN0 Mailbox Word 7 Register */
435#define CAN0_MB29_ID1 0xFFC00FBC /* CAN0 Mailbox Word 7 Register */
436#define CAN0_MB30_ID1 0xFFC00FDC /* CAN0 Mailbox Word 7 Register */
437#define CAN0_MB31_ID1 0xFFC00FFC /* CAN0 Mailbox Word 7 Register */
438
439/* =========================
440 LINK PORT Registers
441 ========================= */
442#define LP0_CTL 0xFFC01000 /* LP0 Control Register */
443#define LP0_STAT 0xFFC01004 /* LP0 Status Register */
444#define LP0_DIV 0xFFC01008 /* LP0 Clock Divider Value */
445#define LP0_CNT 0xFFC0100C /* LP0 Current Count Value of Clock Divider */
446#define LP0_TX 0xFFC01010 /* LP0 Transmit Buffer */
447#define LP0_RX 0xFFC01014 /* LP0 Receive Buffer */
448#define LP0_TXIN_SHDW 0xFFC01018 /* LP0 Shadow Input Transmit Buffer */
449#define LP0_TXOUT_SHDW 0xFFC0101C /* LP0 Shadow Output Transmit Buffer */
450#define LP1_CTL 0xFFC01100 /* LP1 Control Register */
451#define LP1_STAT 0xFFC01104 /* LP1 Status Register */
452#define LP1_DIV 0xFFC01108 /* LP1 Clock Divider Value */
453#define LP1_CNT 0xFFC0110C /* LP1 Current Count Value of Clock Divider */
454#define LP1_TX 0xFFC01110 /* LP1 Transmit Buffer */
455#define LP1_RX 0xFFC01114 /* LP1 Receive Buffer */
456#define LP1_TXIN_SHDW 0xFFC01118 /* LP1 Shadow Input Transmit Buffer */
457#define LP1_TXOUT_SHDW 0xFFC0111C /* LP1 Shadow Output Transmit Buffer */
458#define LP2_CTL 0xFFC01200 /* LP2 Control Register */
459#define LP2_STAT 0xFFC01204 /* LP2 Status Register */
460#define LP2_DIV 0xFFC01208 /* LP2 Clock Divider Value */
461#define LP2_CNT 0xFFC0120C /* LP2 Current Count Value of Clock Divider */
462#define LP2_TX 0xFFC01210 /* LP2 Transmit Buffer */
463#define LP2_RX 0xFFC01214 /* LP2 Receive Buffer */
464#define LP2_TXIN_SHDW 0xFFC01218 /* LP2 Shadow Input Transmit Buffer */
465#define LP2_TXOUT_SHDW 0xFFC0121C /* LP2 Shadow Output Transmit Buffer */
466#define LP3_CTL 0xFFC01300 /* LP3 Control Register */
467#define LP3_STAT 0xFFC01304 /* LP3 Status Register */
468#define LP3_DIV 0xFFC01308 /* LP3 Clock Divider Value */
469#define LP3_CNT 0xFFC0130C /* LP3 Current Count Value of Clock Divider */
470#define LP3_TX 0xFFC01310 /* LP3 Transmit Buffer */
471#define LP3_RX 0xFFC01314 /* LP3 Receive Buffer */
472#define LP3_TXIN_SHDW 0xFFC01318 /* LP3 Shadow Input Transmit Buffer */
473#define LP3_TXOUT_SHDW 0xFFC0131C /* LP3 Shadow Output Transmit Buffer */
474
475/* =========================
476 TIMER Registers
477 ========================= */
478#define TIMER_REVID 0xFFC01400 /* GPTIMER Timer IP Version ID */
479#define TIMER_RUN 0xFFC01404 /* GPTIMER Timer Run Register */
480#define TIMER_RUN_SET 0xFFC01408 /* GPTIMER Run Register Alias to Set */
481#define TIMER_RUN_CLR 0xFFC0140C /* GPTIMER Run Register Alias to Clear */
482#define TIMER_STOP_CFG 0xFFC01410 /* GPTIMER Stop Config Register */
483#define TIMER_STOP_CFG_SET 0xFFC01414 /* GPTIMER Stop Config Alias to Set */
484#define TIMER_STOP_CFG_CLR 0xFFC01418 /* GPTIMER Stop Config Alias to Clear */
485#define TIMER_DATA_IMSK 0xFFC0141C /* GPTIMER Data Interrupt Mask register */
486#define TIMER_STAT_IMSK 0xFFC01420 /* GPTIMER Status Interrupt Mask register */
487#define TIMER_TRG_MSK 0xFFC01424 /* GPTIMER Output Trigger Mask register */
488#define TIMER_TRG_IE 0xFFC01428 /* GPTIMER Slave Trigger Enable register */
489#define TIMER_DATA_ILAT 0xFFC0142C /* GPTIMER Data Interrupt Register */
490#define TIMER_STAT_ILAT 0xFFC01430 /* GPTIMER Status (Error) Interrupt Register */
491#define TIMER_ERR_TYPE 0xFFC01434 /* GPTIMER Register Indicating Type of Error */
492#define TIMER_BCAST_PER 0xFFC01438 /* GPTIMER Broadcast Period */
493#define TIMER_BCAST_WID 0xFFC0143C /* GPTIMER Broadcast Width */
494#define TIMER_BCAST_DLY 0xFFC01440 /* GPTIMER Broadcast Delay */
495
496/* =========================
497 TIMER0~7
498 ========================= */
499#define TIMER0_CONFIG 0xFFC01460 /* TIMER0 Per Timer Config Register */
500#define TIMER0_COUNTER 0xFFC01464 /* TIMER0 Per Timer Counter Register */
501#define TIMER0_PERIOD 0xFFC01468 /* TIMER0 Per Timer Period Register */
502#define TIMER0_WIDTH 0xFFC0146C /* TIMER0 Per Timer Width Register */
503#define TIMER0_DELAY 0xFFC01470 /* TIMER0 Per Timer Delay Register */
504
505#define TIMER1_CONFIG 0xFFC01480 /* TIMER1 Per Timer Config Register */
506#define TIMER1_COUNTER 0xFFC01484 /* TIMER1 Per Timer Counter Register */
507#define TIMER1_PERIOD 0xFFC01488 /* TIMER1 Per Timer Period Register */
508#define TIMER1_WIDTH 0xFFC0148C /* TIMER1 Per Timer Width Register */
509#define TIMER1_DELAY 0xFFC01490 /* TIMER1 Per Timer Delay Register */
510
511#define TIMER2_CONFIG 0xFFC014A0 /* TIMER2 Per Timer Config Register */
512#define TIMER2_COUNTER 0xFFC014A4 /* TIMER2 Per Timer Counter Register */
513#define TIMER2_PERIOD 0xFFC014A8 /* TIMER2 Per Timer Period Register */
514#define TIMER2_WIDTH 0xFFC014AC /* TIMER2 Per Timer Width Register */
515#define TIMER2_DELAY 0xFFC014B0 /* TIMER2 Per Timer Delay Register */
516
517#define TIMER3_CONFIG 0xFFC014C0 /* TIMER3 Per Timer Config Register */
518#define TIMER3_COUNTER 0xFFC014C4 /* TIMER3 Per Timer Counter Register */
519#define TIMER3_PERIOD 0xFFC014C8 /* TIMER3 Per Timer Period Register */
520#define TIMER3_WIDTH 0xFFC014CC /* TIMER3 Per Timer Width Register */
521#define TIMER3_DELAY 0xFFC014D0 /* TIMER3 Per Timer Delay Register */
522
523#define TIMER4_CONFIG 0xFFC014E0 /* TIMER4 Per Timer Config Register */
524#define TIMER4_COUNTER 0xFFC014E4 /* TIMER4 Per Timer Counter Register */
525#define TIMER4_PERIOD 0xFFC014E8 /* TIMER4 Per Timer Period Register */
526#define TIMER4_WIDTH 0xFFC014EC /* TIMER4 Per Timer Width Register */
527#define TIMER4_DELAY 0xFFC014F0 /* TIMER4 Per Timer Delay Register */
528
529#define TIMER5_CONFIG 0xFFC01500 /* TIMER5 Per Timer Config Register */
530#define TIMER5_COUNTER 0xFFC01504 /* TIMER5 Per Timer Counter Register */
531#define TIMER5_PERIOD 0xFFC01508 /* TIMER5 Per Timer Period Register */
532#define TIMER5_WIDTH 0xFFC0150C /* TIMER5 Per Timer Width Register */
533#define TIMER5_DELAY 0xFFC01510 /* TIMER5 Per Timer Delay Register */
534
535#define TIMER6_CONFIG 0xFFC01520 /* TIMER6 Per Timer Config Register */
536#define TIMER6_COUNTER 0xFFC01524 /* TIMER6 Per Timer Counter Register */
537#define TIMER6_PERIOD 0xFFC01528 /* TIMER6 Per Timer Period Register */
538#define TIMER6_WIDTH 0xFFC0152C /* TIMER6 Per Timer Width Register */
539#define TIMER6_DELAY 0xFFC01530 /* TIMER6 Per Timer Delay Register */
540
541#define TIMER7_CONFIG 0xFFC01540 /* TIMER7 Per Timer Config Register */
542#define TIMER7_COUNTER 0xFFC01544 /* TIMER7 Per Timer Counter Register */
543#define TIMER7_PERIOD 0xFFC01548 /* TIMER7 Per Timer Period Register */
544#define TIMER7_WIDTH 0xFFC0154C /* TIMER7 Per Timer Width Register */
545#define TIMER7_DELAY 0xFFC01550 /* TIMER7 Per Timer Delay Register */
546
547/* =========================
548 CRC Registers
549 ========================= */
550
551/* =========================
552 CRC0
553 ========================= */
554#define REG_CRC0_CTL 0xFFC01C00 /* CRC0 Control Register */
555#define REG_CRC0_DCNT 0xFFC01C04 /* CRC0 Data Word Count Register */
556#define REG_CRC0_DCNTRLD 0xFFC01C08 /* CRC0 Data Word Count Reload Register */
557#define REG_CRC0_COMP 0xFFC01C14 /* CRC0 DATA Compare Register */
558#define REG_CRC0_FILLVAL 0xFFC01C18 /* CRC0 Fill Value Register */
559#define REG_CRC0_DFIFO 0xFFC01C1C /* CRC0 DATA FIFO Register */
560#define REG_CRC0_INEN 0xFFC01C20 /* CRC0 Interrupt Enable Register */
561#define REG_CRC0_INEN_SET 0xFFC01C24 /* CRC0 Interrupt Enable Set Register */
562#define REG_CRC0_INEN_CLR 0xFFC01C28 /* CRC0 Interrupt Enable Clear Register */
563#define REG_CRC0_POLY 0xFFC01C2C /* CRC0 Polynomial Register */
564#define REG_CRC0_STAT 0xFFC01C40 /* CRC0 Status Register */
565#define REG_CRC0_DCNTCAP 0xFFC01C44 /* CRC0 DATA Count Capture Register */
566#define REG_CRC0_RESULT_FIN 0xFFC01C4C /* CRC0 Final CRC Result Register */
567#define REG_CRC0_RESULT_CUR 0xFFC01C50 /* CRC0 Current CRC Result Register */
568#define REG_CRC0_REVID 0xFFC01C60 /* CRC0 Revision ID Register */
569
570/* =========================
571 CRC1
572 ========================= */
573#define REG_CRC1_CTL 0xFFC01D00 /* CRC1 Control Register */
574#define REG_CRC1_DCNT 0xFFC01D04 /* CRC1 Data Word Count Register */
575#define REG_CRC1_DCNTRLD 0xFFC01D08 /* CRC1 Data Word Count Reload Register */
576#define REG_CRC1_COMP 0xFFC01D14 /* CRC1 DATA Compare Register */
577#define REG_CRC1_FILLVAL 0xFFC01D18 /* CRC1 Fill Value Register */
578#define REG_CRC1_DFIFO 0xFFC01D1C /* CRC1 DATA FIFO Register */
579#define REG_CRC1_INEN 0xFFC01D20 /* CRC1 Interrupt Enable Register */
580#define REG_CRC1_INEN_SET 0xFFC01D24 /* CRC1 Interrupt Enable Set Register */
581#define REG_CRC1_INEN_CLR 0xFFC01D28 /* CRC1 Interrupt Enable Clear Register */
582#define REG_CRC1_POLY 0xFFC01D2C /* CRC1 Polynomial Register */
583#define REG_CRC1_STAT 0xFFC01D40 /* CRC1 Status Register */
584#define REG_CRC1_DCNTCAP 0xFFC01D44 /* CRC1 DATA Count Capture Register */
585#define REG_CRC1_RESULT_FIN 0xFFC01D4C /* CRC1 Final CRC Result Register */
586#define REG_CRC1_RESULT_CUR 0xFFC01D50 /* CRC1 Current CRC Result Register */
587#define REG_CRC1_REVID 0xFFC01D60 /* CRC1 Revision ID Register */
588
589/* =========================
590 TWI Registers
591 ========================= */
592
593/* =========================
594 TWI0
595 ========================= */
596#define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */
597#define TWI0_CONTROL 0xFFC01E04 /* TWI0 Control Register */
598#define TWI0_SLAVE_CTL 0xFFC01E08 /* TWI0 Slave Mode Control Register */
599#define TWI0_SLAVE_STAT 0xFFC01E0C /* TWI0 Slave Mode Status Register */
600#define TWI0_SLAVE_ADDR 0xFFC01E10 /* TWI0 Slave Mode Address Register */
601#define TWI0_MASTER_CTL 0xFFC01E14 /* TWI0 Master Mode Control Registers */
602#define TWI0_MASTER_STAT 0xFFC01E18 /* TWI0 Master Mode Status Register */
603#define TWI0_MASTER_ADDR 0xFFC01E1C /* TWI0 Master Mode Address Register */
604#define TWI0_INT_STAT 0xFFC01E20 /* TWI0 Interrupt Status Register */
605#define TWI0_INT_MASK 0xFFC01E24 /* TWI0 Interrupt Mask Register */
606#define TWI0_FIFO_CTL 0xFFC01E28 /* TWI0 FIFO Control Register */
607#define TWI0_FIFO_STAT 0xFFC01E2C /* TWI0 FIFO Status Register */
608#define TWI0_XMT_DATA8 0xFFC01E80 /* TWI0 FIFO Transmit Data Single-Byte Register */
609#define TWI0_XMT_DATA16 0xFFC01E84 /* TWI0 FIFO Transmit Data Double-Byte Register */
610#define TWI0_RCV_DATA8 0xFFC01E88 /* TWI0 FIFO Transmit Data Single-Byte Register */
611#define TWI0_RCV_DATA16 0xFFC01E8C /* TWI0 FIFO Transmit Data Double-Byte Register */
612
613/* =========================
614 TWI1
615 ========================= */
616#define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */
617#define TWI1_CONTROL 0xFFC01F04 /* TWI1 Control Register */
618#define TWI1_SLAVE_CTL 0xFFC01F08 /* TWI1 Slave Mode Control Register */
619#define TWI1_SLAVE_STAT 0xFFC01F0C /* TWI1 Slave Mode Status Register */
620#define TWI1_SLAVE_ADDR 0xFFC01F10 /* TWI1 Slave Mode Address Register */
621#define TWI1_MASTER_CTL 0xFFC01F14 /* TWI1 Master Mode Control Registers */
622#define TWI1_MASTER_STAT 0xFFC01F18 /* TWI1 Master Mode Status Register */
623#define TWI1_MASTER_ADDR 0xFFC01F1C /* TWI1 Master Mode Address Register */
624#define TWI1_INT_STAT 0xFFC01F20 /* TWI1 Interrupt Status Register */
625#define TWI1_INT_MASK 0xFFC01F24 /* TWI1 Interrupt Mask Register */
626#define TWI1_FIFO_CTL 0xFFC01F28 /* TWI1 FIFO Control Register */
627#define TWI1_FIFO_STAT 0xFFC01F2C /* TWI1 FIFO Status Register */
628#define TWI1_XMT_DATA8 0xFFC01F80 /* TWI1 FIFO Transmit Data Single-Byte Register */
629#define TWI1_XMT_DATA16 0xFFC01F84 /* TWI1 FIFO Transmit Data Double-Byte Register */
630#define TWI1_RCV_DATA8 0xFFC01F88 /* TWI1 FIFO Transmit Data Single-Byte Register */
631#define TWI1_RCV_DATA16 0xFFC01F8C /* TWI1 FIFO Transmit Data Double-Byte Register */
632
633
634/* =========================
635 UART Registers
636 ========================= */
637
638/* =========================
639 UART0
640 ========================= */
641#define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */
642#define UART0_CTL 0xFFC02004 /* UART0 Control Register */
643#define UART0_STAT 0xFFC02008 /* UART0 Status Register */
644#define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */
645#define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */
646#define UART0_IER 0xFFC02014 /* UART0 Interrupt Mask Register */
647#define UART0_IER_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */
648#define UART0_IER_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */
649#define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */
650#define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */
651#define UART0_TAIP 0xFFC02028 /* UART0 Transmit Address/Insert Pulse Register */
652#define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */
653#define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */
654#define UART0_TXDIV 0xFFC02034 /* UART0 Transmit Clock Devider Register */
655#define UART0_RXDIV 0xFFC02038 /* UART0 Receive Clock Devider Register */
656
657/* =========================
658 UART1
659 ========================= */
660#define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */
661#define UART1_CTL 0xFFC02404 /* UART1 Control Register */
662#define UART1_STAT 0xFFC02408 /* UART1 Status Register */
663#define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */
664#define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */
665#define UART1_IER 0xFFC02414 /* UART1 Interrupt Mask Register */
666#define UART1_IER_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */
667#define UART1_IER_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */
668#define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */
669#define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */
670#define UART1_TAIP 0xFFC02428 /* UART1 Transmit Address/Insert Pulse Register */
671#define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */
672#define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */
673#define UART1_TXDIV 0xFFC02434 /* UART1 Transmit Clock Devider Register */
674#define UART1_RXDIV 0xFFC02438 /* UART1 Receive Clock Devider Register */
675
676
677/* =========================
678 PORT Registers
679 ========================= */
680
681/* =========================
682 PORTA
683 ========================= */
684#define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable Register */
685#define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set Register */
686#define PORTA_FER_CLEAR 0xFFC03008 /* PORTA Port x Function Enable Clear Register */
687#define PORTA_DATA 0xFFC0300C /* PORTA Port x GPIO Data Register */
688#define PORTA_DATA_SET 0xFFC03010 /* PORTA Port x GPIO Data Set Register */
689#define PORTA_DATA_CLEAR 0xFFC03014 /* PORTA Port x GPIO Data Clear Register */
690#define PORTA_DIR 0xFFC03018 /* PORTA Port x GPIO Direction Register */
691#define PORTA_DIR_SET 0xFFC0301C /* PORTA Port x GPIO Direction Set Register */
692#define PORTA_DIR_CLEAR 0xFFC03020 /* PORTA Port x GPIO Direction Clear Register */
693#define PORTA_INEN 0xFFC03024 /* PORTA Port x GPIO Input Enable Register */
694#define PORTA_INEN_SET 0xFFC03028 /* PORTA Port x GPIO Input Enable Set Register */
695#define PORTA_INEN_CLEAR 0xFFC0302C /* PORTA Port x GPIO Input Enable Clear Register */
696#define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control Register */
697#define PORTA_DATA_TGL 0xFFC03034 /* PORTA Port x GPIO Input Enable Toggle Register */
698#define PORTA_POL 0xFFC03038 /* PORTA Port x GPIO Programming Inversion Register */
699#define PORTA_POL_SET 0xFFC0303C /* PORTA Port x GPIO Programming Inversion Set Register */
700#define PORTA_POL_CLEAR 0xFFC03040 /* PORTA Port x GPIO Programming Inversion Clear Register */
701#define PORTA_LOCK 0xFFC03044 /* PORTA Port x GPIO Lock Register */
702#define PORTA_REVID 0xFFC0307C /* PORTA Port x GPIO Revision ID */
703
704/* =========================
705 PORTB
706 ========================= */
707#define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable Register */
708#define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set Register */
709#define PORTB_FER_CLEAR 0xFFC03088 /* PORTB Port x Function Enable Clear Register */
710#define PORTB_DATA 0xFFC0308C /* PORTB Port x GPIO Data Register */
711#define PORTB_DATA_SET 0xFFC03090 /* PORTB Port x GPIO Data Set Register */
712#define PORTB_DATA_CLEAR 0xFFC03094 /* PORTB Port x GPIO Data Clear Register */
713#define PORTB_DIR 0xFFC03098 /* PORTB Port x GPIO Direction Register */
714#define PORTB_DIR_SET 0xFFC0309C /* PORTB Port x GPIO Direction Set Register */
715#define PORTB_DIR_CLEAR 0xFFC030A0 /* PORTB Port x GPIO Direction Clear Register */
716#define PORTB_INEN 0xFFC030A4 /* PORTB Port x GPIO Input Enable Register */
717#define PORTB_INEN_SET 0xFFC030A8 /* PORTB Port x GPIO Input Enable Set Register */
718#define PORTB_INEN_CLEAR 0xFFC030AC /* PORTB Port x GPIO Input Enable Clear Register */
719#define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control Register */
720#define PORTB_DATA_TGL 0xFFC030B4 /* PORTB Port x GPIO Input Enable Toggle Register */
721#define PORTB_POL 0xFFC030B8 /* PORTB Port x GPIO Programming Inversion Register */
722#define PORTB_POL_SET 0xFFC030BC /* PORTB Port x GPIO Programming Inversion Set Register */
723#define PORTB_POL_CLEAR 0xFFC030C0 /* PORTB Port x GPIO Programming Inversion Clear Register */
724#define PORTB_LOCK 0xFFC030C4 /* PORTB Port x GPIO Lock Register */
725#define PORTB_REVID 0xFFC030FC /* PORTB Port x GPIO Revision ID */
726
727/* =========================
728 PORTC
729 ========================= */
730#define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable Register */
731#define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set Register */
732#define PORTC_FER_CLEAR 0xFFC03108 /* PORTC Port x Function Enable Clear Register */
733#define PORTC_DATA 0xFFC0310C /* PORTC Port x GPIO Data Register */
734#define PORTC_DATA_SET 0xFFC03110 /* PORTC Port x GPIO Data Set Register */
735#define PORTC_DATA_CLEAR 0xFFC03114 /* PORTC Port x GPIO Data Clear Register */
736#define PORTC_DIR 0xFFC03118 /* PORTC Port x GPIO Direction Register */
737#define PORTC_DIR_SET 0xFFC0311C /* PORTC Port x GPIO Direction Set Register */
738#define PORTC_DIR_CLEAR 0xFFC03120 /* PORTC Port x GPIO Direction Clear Register */
739#define PORTC_INEN 0xFFC03124 /* PORTC Port x GPIO Input Enable Register */
740#define PORTC_INEN_SET 0xFFC03128 /* PORTC Port x GPIO Input Enable Set Register */
741#define PORTC_INEN_CLEAR 0xFFC0312C /* PORTC Port x GPIO Input Enable Clear Register */
742#define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control Register */
743#define PORTC_DATA_TGL 0xFFC03134 /* PORTC Port x GPIO Input Enable Toggle Register */
744#define PORTC_POL 0xFFC03138 /* PORTC Port x GPIO Programming Inversion Register */
745#define PORTC_POL_SET 0xFFC0313C /* PORTC Port x GPIO Programming Inversion Set Register */
746#define PORTC_POL_CLEAR 0xFFC03140 /* PORTC Port x GPIO Programming Inversion Clear Register */
747#define PORTC_LOCK 0xFFC03144 /* PORTC Port x GPIO Lock Register */
748#define PORTC_REVID 0xFFC0317C /* PORTC Port x GPIO Revision ID */
749
750/* =========================
751 PORTD
752 ========================= */
753#define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable Register */
754#define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set Register */
755#define PORTD_FER_CLEAR 0xFFC03188 /* PORTD Port x Function Enable Clear Register */
756#define PORTD_DATA 0xFFC0318C /* PORTD Port x GPIO Data Register */
757#define PORTD_DATA_SET 0xFFC03190 /* PORTD Port x GPIO Data Set Register */
758#define PORTD_DATA_CLEAR 0xFFC03194 /* PORTD Port x GPIO Data Clear Register */
759#define PORTD_DIR 0xFFC03198 /* PORTD Port x GPIO Direction Register */
760#define PORTD_DIR_SET 0xFFC0319C /* PORTD Port x GPIO Direction Set Register */
761#define PORTD_DIR_CLEAR 0xFFC031A0 /* PORTD Port x GPIO Direction Clear Register */
762#define PORTD_INEN 0xFFC031A4 /* PORTD Port x GPIO Input Enable Register */
763#define PORTD_INEN_SET 0xFFC031A8 /* PORTD Port x GPIO Input Enable Set Register */
764#define PORTD_INEN_CLEAR 0xFFC031AC /* PORTD Port x GPIO Input Enable Clear Register */
765#define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control Register */
766#define PORTD_DATA_TGL 0xFFC031B4 /* PORTD Port x GPIO Input Enable Toggle Register */
767#define PORTD_POL 0xFFC031B8 /* PORTD Port x GPIO Programming Inversion Register */
768#define PORTD_POL_SET 0xFFC031BC /* PORTD Port x GPIO Programming Inversion Set Register */
769#define PORTD_POL_CLEAR 0xFFC031C0 /* PORTD Port x GPIO Programming Inversion Clear Register */
770#define PORTD_LOCK 0xFFC031C4 /* PORTD Port x GPIO Lock Register */
771#define PORTD_REVID 0xFFC031FC /* PORTD Port x GPIO Revision ID */
772
773/* =========================
774 PORTE
775 ========================= */
776#define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable Register */
777#define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set Register */
778#define PORTE_FER_CLEAR 0xFFC03208 /* PORTE Port x Function Enable Clear Register */
779#define PORTE_DATA 0xFFC0320C /* PORTE Port x GPIO Data Register */
780#define PORTE_DATA_SET 0xFFC03210 /* PORTE Port x GPIO Data Set Register */
781#define PORTE_DATA_CLEAR 0xFFC03214 /* PORTE Port x GPIO Data Clear Register */
782#define PORTE_DIR 0xFFC03218 /* PORTE Port x GPIO Direction Register */
783#define PORTE_DIR_SET 0xFFC0321C /* PORTE Port x GPIO Direction Set Register */
784#define PORTE_DIR_CLEAR 0xFFC03220 /* PORTE Port x GPIO Direction Clear Register */
785#define PORTE_INEN 0xFFC03224 /* PORTE Port x GPIO Input Enable Register */
786#define PORTE_INEN_SET 0xFFC03228 /* PORTE Port x GPIO Input Enable Set Register */
787#define PORTE_INEN_CLEAR 0xFFC0322C /* PORTE Port x GPIO Input Enable Clear Register */
788#define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control Register */
789#define PORTE_DATA_TGL 0xFFC03234 /* PORTE Port x GPIO Input Enable Toggle Register */
790#define PORTE_POL 0xFFC03238 /* PORTE Port x GPIO Programming Inversion Register */
791#define PORTE_POL_SET 0xFFC0323C /* PORTE Port x GPIO Programming Inversion Set Register */
792#define PORTE_POL_CLEAR 0xFFC03240 /* PORTE Port x GPIO Programming Inversion Clear Register */
793#define PORTE_LOCK 0xFFC03244 /* PORTE Port x GPIO Lock Register */
794#define PORTE_REVID 0xFFC0327C /* PORTE Port x GPIO Revision ID */
795
796/* =========================
797 PORTF
798 ========================= */
799#define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable Register */
800#define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set Register */
801#define PORTF_FER_CLEAR 0xFFC03288 /* PORTF Port x Function Enable Clear Register */
802#define PORTF_DATA 0xFFC0328C /* PORTF Port x GPIO Data Register */
803#define PORTF_DATA_SET 0xFFC03290 /* PORTF Port x GPIO Data Set Register */
804#define PORTF_DATA_CLEAR 0xFFC03294 /* PORTF Port x GPIO Data Clear Register */
805#define PORTF_DIR 0xFFC03298 /* PORTF Port x GPIO Direction Register */
806#define PORTF_DIR_SET 0xFFC0329C /* PORTF Port x GPIO Direction Set Register */
807#define PORTF_DIR_CLEAR 0xFFC032A0 /* PORTF Port x GPIO Direction Clear Register */
808#define PORTF_INEN 0xFFC032A4 /* PORTF Port x GPIO Input Enable Register */
809#define PORTF_INEN_SET 0xFFC032A8 /* PORTF Port x GPIO Input Enable Set Register */
810#define PORTF_INEN_CLEAR 0xFFC032AC /* PORTF Port x GPIO Input Enable Clear Register */
811#define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control Register */
812#define PORTF_DATA_TGL 0xFFC032B4 /* PORTF Port x GPIO Input Enable Toggle Register */
813#define PORTF_POL 0xFFC032B8 /* PORTF Port x GPIO Programming Inversion Register */
814#define PORTF_POL_SET 0xFFC032BC /* PORTF Port x GPIO Programming Inversion Set Register */
815#define PORTF_POL_CLEAR 0xFFC032C0 /* PORTF Port x GPIO Programming Inversion Clear Register */
816#define PORTF_LOCK 0xFFC032C4 /* PORTF Port x GPIO Lock Register */
817#define PORTF_REVID 0xFFC032FC /* PORTF Port x GPIO Revision ID */
818
819/* =========================
820 PORTG
821 ========================= */
822#define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable Register */
823#define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set Register */
824#define PORTG_FER_CLEAR 0xFFC03308 /* PORTG Port x Function Enable Clear Register */
825#define PORTG_DATA 0xFFC0330C /* PORTG Port x GPIO Data Register */
826#define PORTG_DATA_SET 0xFFC03310 /* PORTG Port x GPIO Data Set Register */
827#define PORTG_DATA_CLEAR 0xFFC03314 /* PORTG Port x GPIO Data Clear Register */
828#define PORTG_DIR 0xFFC03318 /* PORTG Port x GPIO Direction Register */
829#define PORTG_DIR_SET 0xFFC0331C /* PORTG Port x GPIO Direction Set Register */
830#define PORTG_DIR_CLEAR 0xFFC03320 /* PORTG Port x GPIO Direction Clear Register */
831#define PORTG_INEN 0xFFC03324 /* PORTG Port x GPIO Input Enable Register */
832#define PORTG_INEN_SET 0xFFC03328 /* PORTG Port x GPIO Input Enable Set Register */
833#define PORTG_INEN_CLEAR 0xFFC0332C /* PORTG Port x GPIO Input Enable Clear Register */
834#define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control Register */
835#define PORTG_DATA_TGL 0xFFC03334 /* PORTG Port x GPIO Input Enable Toggle Register */
836#define PORTG_POL 0xFFC03338 /* PORTG Port x GPIO Programming Inversion Register */
837#define PORTG_POL_SET 0xFFC0333C /* PORTG Port x GPIO Programming Inversion Set Register */
838#define PORTG_POL_CLEAR 0xFFC03340 /* PORTG Port x GPIO Programming Inversion Clear Register */
839#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */
840#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */
841
842
843/* =========================
844 PINT Registers
845 ========================= */
846
847/* =========================
848 PINT0
849 ========================= */
850#define PINT0_MASK_SET 0xFFC04000 /* PINT0 Pint Mask Set Register */
851#define PINT0_MASK_CLEAR 0xFFC04004 /* PINT0 Pint Mask Clear Register */
852#define PINT0_REQUEST 0xFFC04008 /* PINT0 Pint Request Register */
853#define PINT0_ASSIGN 0xFFC0400C /* PINT0 Pint Assign Register */
854#define PINT0_EDGE_SET 0xFFC04010 /* PINT0 Pint Edge Set Register */
855#define PINT0_EDGE_CLEAR 0xFFC04014 /* PINT0 Pint Edge Clear Register */
856#define PINT0_INVERT_SET 0xFFC04018 /* PINT0 Pint Invert Set Register */
857#define PINT0_INVERT_CLEAR 0xFFC0401C /* PINT0 Pint Invert Clear Register */
858#define PINT0_PINSTATE 0xFFC04020 /* PINT0 Pint Pinstate Register */
859#define PINT0_LATCH 0xFFC04024 /* PINT0 Pint Latch Register */
860
861/* =========================
862 PINT1
863 ========================= */
864#define PINT1_MASK_SET 0xFFC04100 /* PINT1 Pint Mask Set Register */
865#define PINT1_MASK_CLEAR 0xFFC04104 /* PINT1 Pint Mask Clear Register */
866#define PINT1_REQUEST 0xFFC04108 /* PINT1 Pint Request Register */
867#define PINT1_ASSIGN 0xFFC0410C /* PINT1 Pint Assign Register */
868#define PINT1_EDGE_SET 0xFFC04110 /* PINT1 Pint Edge Set Register */
869#define PINT1_EDGE_CLEAR 0xFFC04114 /* PINT1 Pint Edge Clear Register */
870#define PINT1_INVERT_SET 0xFFC04118 /* PINT1 Pint Invert Set Register */
871#define PINT1_INVERT_CLEAR 0xFFC0411C /* PINT1 Pint Invert Clear Register */
872#define PINT1_PINSTATE 0xFFC04120 /* PINT1 Pint Pinstate Register */
873#define PINT1_LATCH 0xFFC04124 /* PINT1 Pint Latch Register */
874
875/* =========================
876 PINT2
877 ========================= */
878#define PINT2_MASK_SET 0xFFC04200 /* PINT2 Pint Mask Set Register */
879#define PINT2_MASK_CLEAR 0xFFC04204 /* PINT2 Pint Mask Clear Register */
880#define PINT2_REQUEST 0xFFC04208 /* PINT2 Pint Request Register */
881#define PINT2_ASSIGN 0xFFC0420C /* PINT2 Pint Assign Register */
882#define PINT2_EDGE_SET 0xFFC04210 /* PINT2 Pint Edge Set Register */
883#define PINT2_EDGE_CLEAR 0xFFC04214 /* PINT2 Pint Edge Clear Register */
884#define PINT2_INVERT_SET 0xFFC04218 /* PINT2 Pint Invert Set Register */
885#define PINT2_INVERT_CLEAR 0xFFC0421C /* PINT2 Pint Invert Clear Register */
886#define PINT2_PINSTATE 0xFFC04220 /* PINT2 Pint Pinstate Register */
887#define PINT2_LATCH 0xFFC04224 /* PINT2 Pint Latch Register */
888
889/* =========================
890 PINT3
891 ========================= */
892#define PINT3_MASK_SET 0xFFC04300 /* PINT3 Pint Mask Set Register */
893#define PINT3_MASK_CLEAR 0xFFC04304 /* PINT3 Pint Mask Clear Register */
894#define PINT3_REQUEST 0xFFC04308 /* PINT3 Pint Request Register */
895#define PINT3_ASSIGN 0xFFC0430C /* PINT3 Pint Assign Register */
896#define PINT3_EDGE_SET 0xFFC04310 /* PINT3 Pint Edge Set Register */
897#define PINT3_EDGE_CLEAR 0xFFC04314 /* PINT3 Pint Edge Clear Register */
898#define PINT3_INVERT_SET 0xFFC04318 /* PINT3 Pint Invert Set Register */
899#define PINT3_INVERT_CLEAR 0xFFC0431C /* PINT3 Pint Invert Clear Register */
900#define PINT3_PINSTATE 0xFFC04320 /* PINT3 Pint Pinstate Register */
901#define PINT3_LATCH 0xFFC04324 /* PINT3 Pint Latch Register */
902
903/* =========================
904 PINT4
905 ========================= */
906#define PINT4_MASK_SET 0xFFC04400 /* PINT4 Pint Mask Set Register */
907#define PINT4_MASK_CLEAR 0xFFC04404 /* PINT4 Pint Mask Clear Register */
908#define PINT4_REQUEST 0xFFC04408 /* PINT4 Pint Request Register */
909#define PINT4_ASSIGN 0xFFC0440C /* PINT4 Pint Assign Register */
910#define PINT4_EDGE_SET 0xFFC04410 /* PINT4 Pint Edge Set Register */
911#define PINT4_EDGE_CLEAR 0xFFC04414 /* PINT4 Pint Edge Clear Register */
912#define PINT4_INVERT_SET 0xFFC04418 /* PINT4 Pint Invert Set Register */
913#define PINT4_INVERT_CLEAR 0xFFC0441C /* PINT4 Pint Invert Clear Register */
914#define PINT4_PINSTATE 0xFFC04420 /* PINT4 Pint Pinstate Register */
915#define PINT4_LATCH 0xFFC04424 /* PINT4 Pint Latch Register */
916
917/* =========================
918 PINT5
919 ========================= */
920#define PINT5_MASK_SET 0xFFC04500 /* PINT5 Pint Mask Set Register */
921#define PINT5_MASK_CLEAR 0xFFC04504 /* PINT5 Pint Mask Clear Register */
922#define PINT5_REQUEST 0xFFC04508 /* PINT5 Pint Request Register */
923#define PINT5_ASSIGN 0xFFC0450C /* PINT5 Pint Assign Register */
924#define PINT5_EDGE_SET 0xFFC04510 /* PINT5 Pint Edge Set Register */
925#define PINT5_EDGE_CLEAR 0xFFC04514 /* PINT5 Pint Edge Clear Register */
926#define PINT5_INVERT_SET 0xFFC04518 /* PINT5 Pint Invert Set Register */
927#define PINT5_INVERT_CLEAR 0xFFC0451C /* PINT5 Pint Invert Clear Register */
928#define PINT5_PINSTATE 0xFFC04520 /* PINT5 Pint Pinstate Register */
929#define PINT5_LATCH 0xFFC04524 /* PINT5 Pint Latch Register */
930
931
932/* =========================
933 SMC Registers
934 ========================= */
935
936/* =========================
937 SMC0
938 ========================= */
939#define SMC_GCTL 0xFFC16004 /* SMC0 SMC Control Register */
940#define SMC_GSTAT 0xFFC16008 /* SMC0 SMC Status Register */
941#define SMC_B0CTL 0xFFC1600C /* SMC0 SMC Bank0 Control Register */
942#define SMC_B0TIM 0xFFC16010 /* SMC0 SMC Bank0 Timing Register */
943#define SMC_B0ETIM 0xFFC16014 /* SMC0 SMC Bank0 Extended Timing Register */
944#define SMC_B1CTL 0xFFC1601C /* SMC0 SMC BANK1 Control Register */
945#define SMC_B1TIM 0xFFC16020 /* SMC0 SMC BANK1 Timing Register */
946#define SMC_B1ETIM 0xFFC16024 /* SMC0 SMC BANK1 Extended Timing Register */
947#define SMC_B2CTL 0xFFC1602C /* SMC0 SMC BANK2 Control Register */
948#define SMC_B2TIM 0xFFC16030 /* SMC0 SMC BANK2 Timing Register */
949#define SMC_B2ETIM 0xFFC16034 /* SMC0 SMC BANK2 Extended Timing Register */
950#define SMC_B3CTL 0xFFC1603C /* SMC0 SMC BANK3 Control Register */
951#define SMC_B3TIM 0xFFC16040 /* SMC0 SMC BANK3 Timing Register */
952#define SMC_B3ETIM 0xFFC16044 /* SMC0 SMC BANK3 Extended Timing Register */
953
954
955/* =========================
956 WDOG Registers
957 ========================= */
958
959/* =========================
960 WDOG0
961 ========================= */
962#define WDOG0_CTL 0xFFC17000 /* WDOG0 Control Register */
963#define WDOG0_CNT 0xFFC17004 /* WDOG0 Count Register */
964#define WDOG0_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */
965#define WDOG_CTL WDOG0_CTL
966#define WDOG_CNT WDOG0_CNT
967#define WDOG_STAT WDOG0_STAT
968
969/* =========================
970 WDOG1
971 ========================= */
972#define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */
973#define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */
974#define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
975
976
977/* =========================
978 SDU Registers
979 ========================= */
980
981/* =========================
982 SDU0
983 ========================= */
984#define SDU0_IDCODE 0xFFC1F020 /* SDU0 ID Code Register */
985#define SDU0_CTL 0xFFC1F050 /* SDU0 Control Register */
986#define SDU0_STAT 0xFFC1F054 /* SDU0 Status Register */
987#define SDU0_MACCTL 0xFFC1F058 /* SDU0 Memory Access Control Register */
988#define SDU0_MACADDR 0xFFC1F05C /* SDU0 Memory Access Address Register */
989#define SDU0_MACDATA 0xFFC1F060 /* SDU0 Memory Access Data Register */
990#define SDU0_DMARD 0xFFC1F064 /* SDU0 DMA Read Data Register */
991#define SDU0_DMAWD 0xFFC1F068 /* SDU0 DMA Write Data Register */
992#define SDU0_MSG 0xFFC1F080 /* SDU0 Message Register */
993#define SDU0_MSG_SET 0xFFC1F084 /* SDU0 Message Set Register */
994#define SDU0_MSG_CLR 0xFFC1F088 /* SDU0 Message Clear Register */
995#define SDU0_GHLT 0xFFC1F08C /* SDU0 Group Halt Register */
996
997
998/* =========================
999 EMAC Registers
1000 ========================= */
1001/* =========================
1002 EMAC0
1003 ========================= */
1004#define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */
1005#define EMAC0_MACFRMFILT 0xFFC20004 /* EMAC0 Filter Register for filtering Received Frames */
1006#define EMAC0_HASHTBL_HI 0xFFC20008 /* EMAC0 Contains the Upper 32 bits of the hash table */
1007#define EMAC0_HASHTBL_LO 0xFFC2000C /* EMAC0 Contains the lower 32 bits of the hash table */
1008#define EMAC0_GMII_ADDR 0xFFC20010 /* EMAC0 Management Address Register */
1009#define EMAC0_GMII_DATA 0xFFC20014 /* EMAC0 Management Data Register */
1010#define EMAC0_FLOWCTL 0xFFC20018 /* EMAC0 MAC FLow Control Register */
1011#define EMAC0_VLANTAG 0xFFC2001C /* EMAC0 VLAN Tag Register */
1012#define EMAC0_VER 0xFFC20020 /* EMAC0 EMAC Version Register */
1013#define EMAC0_DBG 0xFFC20024 /* EMAC0 EMAC Debug Register */
1014#define EMAC0_RMTWKUP 0xFFC20028 /* EMAC0 Remote wake up frame register */
1015#define EMAC0_PMT_CTLSTAT 0xFFC2002C /* EMAC0 PMT Control and Status Register */
1016#define EMAC0_ISTAT 0xFFC20038 /* EMAC0 EMAC Interrupt Status Register */
1017#define EMAC0_IMSK 0xFFC2003C /* EMAC0 EMAC Interrupt Mask Register */
1018#define EMAC0_ADDR0_HI 0xFFC20040 /* EMAC0 EMAC Address0 High Register */
1019#define EMAC0_ADDR0_LO 0xFFC20044 /* EMAC0 EMAC Address0 Low Register */
1020#define EMAC0_MMC_CTL 0xFFC20100 /* EMAC0 MMC Control Register */
1021#define EMAC0_MMC_RXINT 0xFFC20104 /* EMAC0 MMC RX Interrupt Register */
1022#define EMAC0_MMC_TXINT 0xFFC20108 /* EMAC0 MMC TX Interrupt Register */
1023#define EMAC0_MMC_RXIMSK 0xFFC2010C /* EMAC0 MMC RX Interrupt Mask Register */
1024#define EMAC0_MMC_TXIMSK 0xFFC20110 /* EMAC0 MMC TX Interrupt Mask Register */
1025#define EMAC0_TXOCTCNT_GB 0xFFC20114 /* EMAC0 Num bytes transmitted exclusive of preamble */
1026#define EMAC0_TXFRMCNT_GB 0xFFC20118 /* EMAC0 Num frames transmitted exclusive of retired */
1027#define EMAC0_TXBCASTFRM_G 0xFFC2011C /* EMAC0 Number of good broadcast frames transmitted. */
1028#define EMAC0_TXMCASTFRM_G 0xFFC20120 /* EMAC0 Number of good multicast frames transmitted. */
1029#define EMAC0_TX64_GB 0xFFC20124 /* EMAC0 Number of 64 byte length frames */
1030#define EMAC0_TX65TO127_GB 0xFFC20128 /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */
1031#define EMAC0_TX128TO255_GB 0xFFC2012C /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */
1032#define EMAC0_TX256TO511_GB 0xFFC20130 /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */
1033#define EMAC0_TX512TO1023_GB 0xFFC20134 /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */
1034#define EMAC0_TX1024TOMAX_GB 0xFFC20138 /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */
1035#define EMAC0_TXUCASTFRM_GB 0xFFC2013C /* EMAC0 Number of good and bad unicast frames transmitted */
1036#define EMAC0_TXMCASTFRM_GB 0xFFC20140 /* EMAC0 Number of good and bad multicast frames transmitted */
1037#define EMAC0_TXBCASTFRM_GB 0xFFC20144 /* EMAC0 Number of good and bad broadcast frames transmitted */
1038#define EMAC0_TXUNDR_ERR 0xFFC20148 /* EMAC0 Number of frames aborted due to frame underflow error */
1039#define EMAC0_TXSNGCOL_G 0xFFC2014C /* EMAC0 Number of transmitted frames after single collision */
1040#define EMAC0_TXMULTCOL_G 0xFFC20150 /* EMAC0 Number of transmitted frames with more than one collision */
1041#define EMAC0_TXDEFERRED 0xFFC20154 /* EMAC0 Number of transmitted frames after deferral */
1042#define EMAC0_TXLATECOL 0xFFC20158 /* EMAC0 Number of frames aborted due to late collision error */
1043#define EMAC0_TXEXCESSCOL 0xFFC2015C /* EMAC0 Number of aborted frames due to excessive collisions */
1044#define EMAC0_TXCARR_ERR 0xFFC20160 /* EMAC0 Number of aborted frames due to carrier sense error */
1045#define EMAC0_TXOCTCNT_G 0xFFC20164 /* EMAC0 Number of bytes transmitted in good frames only */
1046#define EMAC0_TXFRMCNT_G 0xFFC20168 /* EMAC0 Number of good frames transmitted. */
1047#define EMAC0_TXEXCESSDEF 0xFFC2016C /* EMAC0 Number of frames aborted due to excessive deferral */
1048#define EMAC0_TXPAUSEFRM 0xFFC20170 /* EMAC0 Number of good PAUSE frames transmitted. */
1049#define EMAC0_TXVLANFRM_G 0xFFC20174 /* EMAC0 Number of VLAN frames transmitted */
1050#define EMAC0_RXFRMCNT_GB 0xFFC20180 /* EMAC0 Number of good and bad frames received. */
1051#define EMAC0_RXOCTCNT_GB 0xFFC20184 /* EMAC0 Number of bytes received in good and bad frames */
1052#define EMAC0_RXOCTCNT_G 0xFFC20188 /* EMAC0 Number of bytes received only in good frames */
1053#define EMAC0_RXBCASTFRM_G 0xFFC2018C /* EMAC0 Number of good broadcast frames received. */
1054#define EMAC0_RXMCASTFRM_G 0xFFC20190 /* EMAC0 Number of good multicast frames received */
1055#define EMAC0_RXCRC_ERR 0xFFC20194 /* EMAC0 Number of frames received with CRC error */
1056#define EMAC0_RXALIGN_ERR 0xFFC20198 /* EMAC0 Number of frames with alignment error */
1057#define EMAC0_RXRUNT_ERR 0xFFC2019C /* EMAC0 Number of frames received with runt error. */
1058#define EMAC0_RXJAB_ERR 0xFFC201A0 /* EMAC0 Number of frames received with length greater than 1518 */
1059#define EMAC0_RXUSIZE_G 0xFFC201A4 /* EMAC0 Number of frames received with length 64 */
1060#define EMAC0_RXOSIZE_G 0xFFC201A8 /* EMAC0 Number of frames received with length greater than maxium */
1061#define EMAC0_RX64_GB 0xFFC201AC /* EMAC0 Number of good and bad frames of lengh 64 bytes */
1062#define EMAC0_RX65TO127_GB 0xFFC201B0 /* EMAC0 Number of good and bad frame between 64-127(inclusive) */
1063#define EMAC0_RX128TO255_GB 0xFFC201B4 /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
1064#define EMAC0_RX256TO511_GB 0xFFC201B8 /* EMAC0 Number of good and bad frames between 256-511(inclusive) */
1065#define EMAC0_RX512TO1023_GB 0xFFC201BC /* EMAC0 Number of good and bad frames received between 512-1023 */
1066#define EMAC0_RX1024TOMAX_GB 0xFFC201C0 /* EMAC0 Number of frames received between 1024 and maxsize */
1067#define EMAC0_RXUCASTFRM_G 0xFFC201C4 /* EMAC0 Number of good unicast frames received. */
1068#define EMAC0_RXLEN_ERR 0xFFC201C8 /* EMAC0 Number of frames received with length error */
1069#define EMAC0_RXOORTYPE 0xFFC201CC /* EMAC0 Number of frames with length not equal to valid frame size */
1070#define EMAC0_RXPAUSEFRM 0xFFC201D0 /* EMAC0 Number of good and valid PAUSE frames received. */
1071#define EMAC0_RXFIFO_OVF 0xFFC201D4 /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
1072#define EMAC0_RXVLANFRM_GB 0xFFC201D8 /* EMAC0 Number of good and bad VLAN frames received. */
1073#define EMAC0_RXWDOG_ERR 0xFFC201DC /* EMAC0 Frames received with error due to watchdog timeout */
1074#define EMAC0_IPC_RXIMSK 0xFFC20200 /* EMAC0 MMC IPC RX Interrupt Mask Register */
1075#define EMAC0_IPC_RXINT 0xFFC20208 /* EMAC0 MMC IPC RX Interrupt Register */
1076#define EMAC0_RXIPV4_GD_FRM 0xFFC20210 /* EMAC0 Number of good IPv4 datagrams */
1077#define EMAC0_RXIPV4_HDR_ERR_FRM 0xFFC20214 /* EMAC0 Number of IPv4 datagrams with header errors */
1078#define EMAC0_RXIPV4_NOPAY_FRM 0xFFC20218 /* EMAC0 Number of IPv4 datagrams without checksum */
1079#define EMAC0_RXIPV4_FRAG_FRM 0xFFC2021C /* EMAC0 Number of good IPv4 datagrams with fragmentation */
1080#define EMAC0_RXIPV4_UDSBL_FRM 0xFFC20220 /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */
1081#define EMAC0_RXIPV6_GD_FRM 0xFFC20224 /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
1082#define EMAC0_RXIPV6_HDR_ERR_FRM 0xFFC20228 /* EMAC0 Number of IPv6 datagrams with header errors */
1083#define EMAC0_RXIPV6_NOPAY_FRM 0xFFC2022C /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
1084#define EMAC0_RXUDP_GD_FRM 0xFFC20230 /* EMAC0 Number of good IP datagrames with good UDP payload */
1085#define EMAC0_RXUDP_ERR_FRM 0xFFC20234 /* EMAC0 Number of good IP datagrams with UDP checksum errors */
1086#define EMAC0_RXTCP_GD_FRM 0xFFC20238 /* EMAC0 Number of good IP datagrams with a good TCP payload */
1087#define EMAC0_RXTCP_ERR_FRM 0xFFC2023C /* EMAC0 Number of good IP datagrams with TCP checksum errors */
1088#define EMAC0_RXICMP_GD_FRM 0xFFC20240 /* EMAC0 Number of good IP datagrams with a good ICMP payload */
1089#define EMAC0_RXICMP_ERR_FRM 0xFFC20244 /* EMAC0 Number of good IP datagrams with ICMP checksum errors */
1090#define EMAC0_RXIPV4_GD_OCT 0xFFC20250 /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */
1091#define EMAC0_RXIPV4_HDR_ERR_OCT 0xFFC20254 /* EMAC0 Bytes received in IPv4 datagrams with header errors */
1092#define EMAC0_RXIPV4_NOPAY_OCT 0xFFC20258 /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
1093#define EMAC0_RXIPV4_FRAG_OCT 0xFFC2025C /* EMAC0 Bytes received in fragmented IPv4 datagrams */
1094#define EMAC0_RXIPV4_UDSBL_OCT 0xFFC20260 /* EMAC0 Bytes received in UDP segment with checksum disabled */
1095#define EMAC0_RXIPV6_GD_OCT 0xFFC20264 /* EMAC0 Bytes received in good IPv6 including tcp,udp or icmp load */
1096#define EMAC0_RXIPV6_HDR_ERR_OCT 0xFFC20268 /* EMAC0 Number of bytes received in IPv6 with header errors */
1097#define EMAC0_RXIPV6_NOPAY_OCT 0xFFC2026C /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */
1098#define EMAC0_RXUDP_GD_OCT 0xFFC20270 /* EMAC0 Number of bytes received in good UDP segments */
1099#define EMAC0_RXUDP_ERR_OCT 0xFFC20274 /* EMAC0 Number of bytes received in UDP segment with checksum err */
1100#define EMAC0_RXTCP_GD_OCT 0xFFC20278 /* EMAC0 Number of bytes received in a good TCP segment */
1101#define EMAC0_RXTCP_ERR_OCT 0xFFC2027C /* EMAC0 Number of bytes received in TCP segment with checksum err */
1102#define EMAC0_RXICMP_GD_OCT 0xFFC20280 /* EMAC0 Number of bytes received in a good ICMP segment */
1103#define EMAC0_RXICMP_ERR_OCT 0xFFC20284 /* EMAC0 Bytes received in an ICMP segment with checksum errors */
1104#define EMAC0_TM_CTL 0xFFC20700 /* EMAC0 EMAC Time Stamp Control Register */
1105#define EMAC0_TM_SUBSEC 0xFFC20704 /* EMAC0 EMAC Time Stamp Sub Second Increment */
1106#define EMAC0_TM_SEC 0xFFC20708 /* EMAC0 EMAC Time Stamp Second Register */
1107#define EMAC0_TM_NSEC 0xFFC2070C /* EMAC0 EMAC Time Stamp Nano Second Register */
1108#define EMAC0_TM_SECUPDT 0xFFC20710 /* EMAC0 EMAC Time Stamp Seconds Update */
1109#define EMAC0_TM_NSECUPDT 0xFFC20714 /* EMAC0 EMAC Time Stamp Nano Seconds Update */
1110#define EMAC0_TM_ADDEND 0xFFC20718 /* EMAC0 EMAC Time Stamp Addend Register */
1111#define EMAC0_TM_TGTM 0xFFC2071C /* EMAC0 EMAC Time Stamp Target Time Sec. */
1112#define EMAC0_TM_NTGTM 0xFFC20720 /* EMAC0 EMAC Time Stamp Target Time Nanosec. */
1113#define EMAC0_TM_HISEC 0xFFC20724 /* EMAC0 EMAC Time Stamp High Second Register */
1114#define EMAC0_TM_STMPSTAT 0xFFC20728 /* EMAC0 EMAC Time Stamp Status Register */
1115#define EMAC0_TM_PPSCTL 0xFFC2072C /* EMAC0 EMAC PPS Control Register */
1116#define EMAC0_TM_AUXSTMP_NSEC 0xFFC20730 /* EMAC0 EMAC Auxillary Time Stamp Nano Register */
1117#define EMAC0_TM_AUXSTMP_SEC 0xFFC20734 /* EMAC0 EMAC Auxillary Time Stamp Sec Register */
1118#define EMAC0_DMA_BUSMODE 0xFFC21000 /* EMAC0 Bus Operating Modes for EMAC DMA */
1119#define EMAC0_DMA_TXPOLL 0xFFC21004 /* EMAC0 TX DMA Poll demand register */
1120#define EMAC0_DMA_RXPOLL 0xFFC21008 /* EMAC0 RX DMA Poll demand register */
1121#define EMAC0_DMA_RXDSC_ADDR 0xFFC2100C /* EMAC0 RX Descriptor List Address */
1122#define EMAC0_DMA_TXDSC_ADDR 0xFFC21010 /* EMAC0 TX Descriptor List Address */
1123#define EMAC0_DMA_STAT 0xFFC21014 /* EMAC0 DMA Status Register */
1124#define EMAC0_DMA_OPMODE 0xFFC21018 /* EMAC0 DMA Operation Mode Register */
1125#define EMAC0_DMA_IEN 0xFFC2101C /* EMAC0 DMA Interrupt Enable Register */
1126#define EMAC0_DMA_MISS_FRM 0xFFC21020 /* EMAC0 DMA missed frame and buffer overflow counter */
1127#define EMAC0_DMA_RXIWDOG 0xFFC21024 /* EMAC0 DMA RX Interrupt Watch Dog timer */
1128#define EMAC0_DMA_BMMODE 0xFFC21028 /* EMAC0 AXI Bus Mode Register */
1129#define EMAC0_DMA_BMSTAT 0xFFC2102C /* EMAC0 AXI Status Register */
1130#define EMAC0_DMA_TXDSC_CUR 0xFFC21048 /* EMAC0 TX current descriptor register */
1131#define EMAC0_DMA_RXDSC_CUR 0xFFC2104C /* EMAC0 RX current descriptor register */
1132#define EMAC0_DMA_TXBUF_CUR 0xFFC21050 /* EMAC0 TX current buffer pointer register */
1133#define EMAC0_DMA_RXBUF_CUR 0xFFC21054 /* EMAC0 RX current buffer pointer register */
1134#define EMAC0_HWFEAT 0xFFC21058 /* EMAC0 Hardware Feature Register */
1135
1136/* =========================
1137 EMAC1
1138 ========================= */
1139#define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */
1140#define EMAC1_MACFRMFILT 0xFFC22004 /* EMAC1 Filter Register for filtering Received Frames */
1141#define EMAC1_HASHTBL_HI 0xFFC22008 /* EMAC1 Contains the Upper 32 bits of the hash table */
1142#define EMAC1_HASHTBL_LO 0xFFC2200C /* EMAC1 Contains the lower 32 bits of the hash table */
1143#define EMAC1_GMII_ADDR 0xFFC22010 /* EMAC1 Management Address Register */
1144#define EMAC1_GMII_DATA 0xFFC22014 /* EMAC1 Management Data Register */
1145#define EMAC1_FLOWCTL 0xFFC22018 /* EMAC1 MAC FLow Control Register */
1146#define EMAC1_VLANTAG 0xFFC2201C /* EMAC1 VLAN Tag Register */
1147#define EMAC1_VER 0xFFC22020 /* EMAC1 EMAC Version Register */
1148#define EMAC1_DBG 0xFFC22024 /* EMAC1 EMAC Debug Register */
1149#define EMAC1_RMTWKUP 0xFFC22028 /* EMAC1 Remote wake up frame register */
1150#define EMAC1_PMT_CTLSTAT 0xFFC2202C /* EMAC1 PMT Control and Status Register */
1151#define EMAC1_ISTAT 0xFFC22038 /* EMAC1 EMAC Interrupt Status Register */
1152#define EMAC1_IMSK 0xFFC2203C /* EMAC1 EMAC Interrupt Mask Register */
1153#define EMAC1_ADDR0_HI 0xFFC22040 /* EMAC1 EMAC Address0 High Register */
1154#define EMAC1_ADDR0_LO 0xFFC22044 /* EMAC1 EMAC Address0 Low Register */
1155#define EMAC1_MMC_CTL 0xFFC22100 /* EMAC1 MMC Control Register */
1156#define EMAC1_MMC_RXINT 0xFFC22104 /* EMAC1 MMC RX Interrupt Register */
1157#define EMAC1_MMC_TXINT 0xFFC22108 /* EMAC1 MMC TX Interrupt Register */
1158#define EMAC1_MMC_RXIMSK 0xFFC2210C /* EMAC1 MMC RX Interrupt Mask Register */
1159#define EMAC1_MMC_TXIMSK 0xFFC22110 /* EMAC1 MMC TX Interrupt Mask Register */
1160#define EMAC1_TXOCTCNT_GB 0xFFC22114 /* EMAC1 Num bytes transmitted exclusive of preamble */
1161#define EMAC1_TXFRMCNT_GB 0xFFC22118 /* EMAC1 Num frames transmitted exclusive of retired */
1162#define EMAC1_TXBCASTFRM_G 0xFFC2211C /* EMAC1 Number of good broadcast frames transmitted. */
1163#define EMAC1_TXMCASTFRM_G 0xFFC22120 /* EMAC1 Number of good multicast frames transmitted. */
1164#define EMAC1_TX64_GB 0xFFC22124 /* EMAC1 Number of 64 byte length frames */
1165#define EMAC1_TX65TO127_GB 0xFFC22128 /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */
1166#define EMAC1_TX128TO255_GB 0xFFC2212C /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */
1167#define EMAC1_TX256TO511_GB 0xFFC22130 /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */
1168#define EMAC1_TX512TO1023_GB 0xFFC22134 /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */
1169#define EMAC1_TX1024TOMAX_GB 0xFFC22138 /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */
1170#define EMAC1_TXUCASTFRM_GB 0xFFC2213C /* EMAC1 Number of good and bad unicast frames transmitted */
1171#define EMAC1_TXMCASTFRM_GB 0xFFC22140 /* EMAC1 Number of good and bad multicast frames transmitted */
1172#define EMAC1_TXBCASTFRM_GB 0xFFC22144 /* EMAC1 Number of good and bad broadcast frames transmitted */
1173#define EMAC1_TXUNDR_ERR 0xFFC22148 /* EMAC1 Number of frames aborted due to frame underflow error */
1174#define EMAC1_TXSNGCOL_G 0xFFC2214C /* EMAC1 Number of transmitted frames after single collision */
1175#define EMAC1_TXMULTCOL_G 0xFFC22150 /* EMAC1 Number of transmitted frames with more than one collision */
1176#define EMAC1_TXDEFERRED 0xFFC22154 /* EMAC1 Number of transmitted frames after deferral */
1177#define EMAC1_TXLATECOL 0xFFC22158 /* EMAC1 Number of frames aborted due to late collision error */
1178#define EMAC1_TXEXCESSCOL 0xFFC2215C /* EMAC1 Number of aborted frames due to excessive collisions */
1179#define EMAC1_TXCARR_ERR 0xFFC22160 /* EMAC1 Number of aborted frames due to carrier sense error */
1180#define EMAC1_TXOCTCNT_G 0xFFC22164 /* EMAC1 Number of bytes transmitted in good frames only */
1181#define EMAC1_TXFRMCNT_G 0xFFC22168 /* EMAC1 Number of good frames transmitted. */
1182#define EMAC1_TXEXCESSDEF 0xFFC2216C /* EMAC1 Number of frames aborted due to excessive deferral */
1183#define EMAC1_TXPAUSEFRM 0xFFC22170 /* EMAC1 Number of good PAUSE frames transmitted. */
1184#define EMAC1_TXVLANFRM_G 0xFFC22174 /* EMAC1 Number of VLAN frames transmitted */
1185#define EMAC1_RXFRMCNT_GB 0xFFC22180 /* EMAC1 Number of good and bad frames received. */
1186#define EMAC1_RXOCTCNT_GB 0xFFC22184 /* EMAC1 Number of bytes received in good and bad frames */
1187#define EMAC1_RXOCTCNT_G 0xFFC22188 /* EMAC1 Number of bytes received only in good frames */
1188#define EMAC1_RXBCASTFRM_G 0xFFC2218C /* EMAC1 Number of good broadcast frames received. */
1189#define EMAC1_RXMCASTFRM_G 0xFFC22190 /* EMAC1 Number of good multicast frames received */
1190#define EMAC1_RXCRC_ERR 0xFFC22194 /* EMAC1 Number of frames received with CRC error */
1191#define EMAC1_RXALIGN_ERR 0xFFC22198 /* EMAC1 Number of frames with alignment error */
1192#define EMAC1_RXRUNT_ERR 0xFFC2219C /* EMAC1 Number of frames received with runt error. */
1193#define EMAC1_RXJAB_ERR 0xFFC221A0 /* EMAC1 Number of frames received with length greater than 1518 */
1194#define EMAC1_RXUSIZE_G 0xFFC221A4 /* EMAC1 Number of frames received with length 64 */
1195#define EMAC1_RXOSIZE_G 0xFFC221A8 /* EMAC1 Number of frames received with length greater than maxium */
1196#define EMAC1_RX64_GB 0xFFC221AC /* EMAC1 Number of good and bad frames of lengh 64 bytes */
1197#define EMAC1_RX65TO127_GB 0xFFC221B0 /* EMAC1 Number of good and bad frame between 64-127(inclusive) */
1198#define EMAC1_RX128TO255_GB 0xFFC221B4 /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
1199#define EMAC1_RX256TO511_GB 0xFFC221B8 /* EMAC1 Number of good and bad frames between 256-511(inclusive) */
1200#define EMAC1_RX512TO1023_GB 0xFFC221BC /* EMAC1 Number of good and bad frames received between 512-1023 */
1201#define EMAC1_RX1024TOMAX_GB 0xFFC221C0 /* EMAC1 Number of frames received between 1024 and maxsize */
1202#define EMAC1_RXUCASTFRM_G 0xFFC221C4 /* EMAC1 Number of good unicast frames received. */
1203#define EMAC1_RXLEN_ERR 0xFFC221C8 /* EMAC1 Number of frames received with length error */
1204#define EMAC1_RXOORTYPE 0xFFC221CC /* EMAC1 Number of frames with length not equal to valid frame size */
1205#define EMAC1_RXPAUSEFRM 0xFFC221D0 /* EMAC1 Number of good and valid PAUSE frames received. */
1206#define EMAC1_RXFIFO_OVF 0xFFC221D4 /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
1207#define EMAC1_RXVLANFRM_GB 0xFFC221D8 /* EMAC1 Number of good and bad VLAN frames received. */
1208#define EMAC1_RXWDOG_ERR 0xFFC221DC /* EMAC1 Frames received with error due to watchdog timeout */
1209#define EMAC1_IPC_RXIMSK 0xFFC22200 /* EMAC1 MMC IPC RX Interrupt Mask Register */
1210#define EMAC1_IPC_RXINT 0xFFC22208 /* EMAC1 MMC IPC RX Interrupt Register */
1211#define EMAC1_RXIPV4_GD_FRM 0xFFC22210 /* EMAC1 Number of good IPv4 datagrams */
1212#define EMAC1_RXIPV4_HDR_ERR_FRM 0xFFC22214 /* EMAC1 Number of IPv4 datagrams with header errors */
1213#define EMAC1_RXIPV4_NOPAY_FRM 0xFFC22218 /* EMAC1 Number of IPv4 datagrams without checksum */
1214#define EMAC1_RXIPV4_FRAG_FRM 0xFFC2221C /* EMAC1 Number of good IPv4 datagrams with fragmentation */
1215#define EMAC1_RXIPV4_UDSBL_FRM 0xFFC22220 /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */
1216#define EMAC1_RXIPV6_GD_FRM 0xFFC22224 /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
1217#define EMAC1_RXIPV6_HDR_ERR_FRM 0xFFC22228 /* EMAC1 Number of IPv6 datagrams with header errors */
1218#define EMAC1_RXIPV6_NOPAY_FRM 0xFFC2222C /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
1219#define EMAC1_RXUDP_GD_FRM 0xFFC22230 /* EMAC1 Number of good IP datagrames with good UDP payload */
1220#define EMAC1_RXUDP_ERR_FRM 0xFFC22234 /* EMAC1 Number of good IP datagrams with UDP checksum errors */
1221#define EMAC1_RXTCP_GD_FRM 0xFFC22238 /* EMAC1 Number of good IP datagrams with a good TCP payload */
1222#define EMAC1_RXTCP_ERR_FRM 0xFFC2223C /* EMAC1 Number of good IP datagrams with TCP checksum errors */
1223#define EMAC1_RXICMP_GD_FRM 0xFFC22240 /* EMAC1 Number of good IP datagrams with a good ICMP payload */
1224#define EMAC1_RXICMP_ERR_FRM 0xFFC22244 /* EMAC1 Number of good IP datagrams with ICMP checksum errors */
1225#define EMAC1_RXIPV4_GD_OCT 0xFFC22250 /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */
1226#define EMAC1_RXIPV4_HDR_ERR_OCT 0xFFC22254 /* EMAC1 Bytes received in IPv4 datagrams with header errors */
1227#define EMAC1_RXIPV4_NOPAY_OCT 0xFFC22258 /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
1228#define EMAC1_RXIPV4_FRAG_OCT 0xFFC2225C /* EMAC1 Bytes received in fragmented IPv4 datagrams */
1229#define EMAC1_RXIPV4_UDSBL_OCT 0xFFC22260 /* EMAC1 Bytes received in UDP segment with checksum disabled */
1230#define EMAC1_RXIPV6_GD_OCT 0xFFC22264 /* EMAC1 Bytes received in good IPv6 including tcp,udp or icmp load */
1231#define EMAC1_RXIPV6_HDR_ERR_OCT 0xFFC22268 /* EMAC1 Number of bytes received in IPv6 with header errors */
1232#define EMAC1_RXIPV6_NOPAY_OCT 0xFFC2226C /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */
1233#define EMAC1_RXUDP_GD_OCT 0xFFC22270 /* EMAC1 Number of bytes received in good UDP segments */
1234#define EMAC1_RXUDP_ERR_OCT 0xFFC22274 /* EMAC1 Number of bytes received in UDP segment with checksum err */
1235#define EMAC1_RXTCP_GD_OCT 0xFFC22278 /* EMAC1 Number of bytes received in a good TCP segment */
1236#define EMAC1_RXTCP_ERR_OCT 0xFFC2227C /* EMAC1 Number of bytes received in TCP segment with checksum err */
1237#define EMAC1_RXICMP_GD_OCT 0xFFC22280 /* EMAC1 Number of bytes received in a good ICMP segment */
1238#define EMAC1_RXICMP_ERR_OCT 0xFFC22284 /* EMAC1 Bytes received in an ICMP segment with checksum errors */
1239#define EMAC1_TM_CTL 0xFFC22700 /* EMAC1 EMAC Time Stamp Control Register */
1240#define EMAC1_TM_SUBSEC 0xFFC22704 /* EMAC1 EMAC Time Stamp Sub Second Increment */
1241#define EMAC1_TM_SEC 0xFFC22708 /* EMAC1 EMAC Time Stamp Second Register */
1242#define EMAC1_TM_NSEC 0xFFC2270C /* EMAC1 EMAC Time Stamp Nano Second Register */
1243#define EMAC1_TM_SECUPDT 0xFFC22710 /* EMAC1 EMAC Time Stamp Seconds Update */
1244#define EMAC1_TM_NSECUPDT 0xFFC22714 /* EMAC1 EMAC Time Stamp Nano Seconds Update */
1245#define EMAC1_TM_ADDEND 0xFFC22718 /* EMAC1 EMAC Time Stamp Addend Register */
1246#define EMAC1_TM_TGTM 0xFFC2271C /* EMAC1 EMAC Time Stamp Target Time Sec. */
1247#define EMAC1_TM_NTGTM 0xFFC22720 /* EMAC1 EMAC Time Stamp Target Time Nanosec. */
1248#define EMAC1_TM_HISEC 0xFFC22724 /* EMAC1 EMAC Time Stamp High Second Register */
1249#define EMAC1_TM_STMPSTAT 0xFFC22728 /* EMAC1 EMAC Time Stamp Status Register */
1250#define EMAC1_TM_PPSCTL 0xFFC2272C /* EMAC1 EMAC PPS Control Register */
1251#define EMAC1_TM_AUXSTMP_NSEC 0xFFC22730 /* EMAC1 EMAC Auxillary Time Stamp Nano Register */
1252#define EMAC1_TM_AUXSTMP_SEC 0xFFC22734 /* EMAC1 EMAC Auxillary Time Stamp Sec Register */
1253#define EMAC1_DMA_BUSMODE 0xFFC23000 /* EMAC1 Bus Operating Modes for EMAC DMA */
1254#define EMAC1_DMA_TXPOLL 0xFFC23004 /* EMAC1 TX DMA Poll demand register */
1255#define EMAC1_DMA_RXPOLL 0xFFC23008 /* EMAC1 RX DMA Poll demand register */
1256#define EMAC1_DMA_RXDSC_ADDR 0xFFC2300C /* EMAC1 RX Descriptor List Address */
1257#define EMAC1_DMA_TXDSC_ADDR 0xFFC23010 /* EMAC1 TX Descriptor List Address */
1258#define EMAC1_DMA_STAT 0xFFC23014 /* EMAC1 DMA Status Register */
1259#define EMAC1_DMA_OPMODE 0xFFC23018 /* EMAC1 DMA Operation Mode Register */
1260#define EMAC1_DMA_IEN 0xFFC2301C /* EMAC1 DMA Interrupt Enable Register */
1261#define EMAC1_DMA_MISS_FRM 0xFFC23020 /* EMAC1 DMA missed frame and buffer overflow counter */
1262#define EMAC1_DMA_RXIWDOG 0xFFC23024 /* EMAC1 DMA RX Interrupt Watch Dog timer */
1263#define EMAC1_DMA_BMMODE 0xFFC23028 /* EMAC1 AXI Bus Mode Register */
1264#define EMAC1_DMA_BMSTAT 0xFFC2302C /* EMAC1 AXI Status Register */
1265#define EMAC1_DMA_TXDSC_CUR 0xFFC23048 /* EMAC1 TX current descriptor register */
1266#define EMAC1_DMA_RXDSC_CUR 0xFFC2304C /* EMAC1 RX current descriptor register */
1267#define EMAC1_DMA_TXBUF_CUR 0xFFC23050 /* EMAC1 TX current buffer pointer register */
1268#define EMAC1_DMA_RXBUF_CUR 0xFFC23054 /* EMAC1 RX current buffer pointer register */
1269#define EMAC1_HWFEAT 0xFFC23058 /* EMAC1 Hardware Feature Register */
1270
1271
1272/* =========================
1273 SPI Registers
1274 ========================= */
1275
1276/* =========================
1277 SPI0
1278 ========================= */
1279#define SPI0_REGBASE 0xFFC40400
1280#define SPI0_CTL 0xFFC40404 /* SPI0 Control Register */
1281#define SPI0_RXCTL 0xFFC40408 /* SPI0 RX Control Register */
1282#define SPI0_TXCTL 0xFFC4040C /* SPI0 TX Control Register */
1283#define SPI0_CLK 0xFFC40410 /* SPI0 Clock Rate Register */
1284#define SPI0_DLY 0xFFC40414 /* SPI0 Delay Register */
1285#define SPI0_SLVSEL 0xFFC40418 /* SPI0 Slave Select Register */
1286#define SPI0_RWC 0xFFC4041C /* SPI0 Received Word-Count Register */
1287#define SPI0_RWCR 0xFFC40420 /* SPI0 Received Word-Count Reload Register */
1288#define SPI0_TWC 0xFFC40424 /* SPI0 Transmitted Word-Count Register */
1289#define SPI0_TWCR 0xFFC40428 /* SPI0 Transmitted Word-Count Reload Register */
1290#define SPI0_IMSK 0xFFC40430 /* SPI0 Interrupt Mask Register */
1291#define SPI0_IMSK_CLR 0xFFC40434 /* SPI0 Interrupt Mask Clear Register */
1292#define SPI0_IMSK_SET 0xFFC40438 /* SPI0 Interrupt Mask Set Register */
1293#define SPI0_STAT 0xFFC40440 /* SPI0 Status Register */
1294#define SPI0_ILAT 0xFFC40444 /* SPI0 Masked Interrupt Condition Register */
1295#define SPI0_ILAT_CLR 0xFFC40448 /* SPI0 Masked Interrupt Clear Register */
1296#define SPI0_RFIFO 0xFFC40450 /* SPI0 Receive FIFO Data Register */
1297#define SPI0_TFIFO 0xFFC40458 /* SPI0 Transmit FIFO Data Register */
1298
1299/* =========================
1300 SPI1
1301 ========================= */
1302#define SPI1_REGBASE 0xFFC40500
1303#define SPI1_CTL 0xFFC40504 /* SPI1 Control Register */
1304#define SPI1_RXCTL 0xFFC40508 /* SPI1 RX Control Register */
1305#define SPI1_TXCTL 0xFFC4050C /* SPI1 TX Control Register */
1306#define SPI1_CLK 0xFFC40510 /* SPI1 Clock Rate Register */
1307#define SPI1_DLY 0xFFC40514 /* SPI1 Delay Register */
1308#define SPI1_SLVSEL 0xFFC40518 /* SPI1 Slave Select Register */
1309#define SPI1_RWC 0xFFC4051C /* SPI1 Received Word-Count Register */
1310#define SPI1_RWCR 0xFFC40520 /* SPI1 Received Word-Count Reload Register */
1311#define SPI1_TWC 0xFFC40524 /* SPI1 Transmitted Word-Count Register */
1312#define SPI1_TWCR 0xFFC40528 /* SPI1 Transmitted Word-Count Reload Register */
1313#define SPI1_IMSK 0xFFC40530 /* SPI1 Interrupt Mask Register */
1314#define SPI1_IMSK_CLR 0xFFC40534 /* SPI1 Interrupt Mask Clear Register */
1315#define SPI1_IMSK_SET 0xFFC40538 /* SPI1 Interrupt Mask Set Register */
1316#define SPI1_STAT 0xFFC40540 /* SPI1 Status Register */
1317#define SPI1_ILAT 0xFFC40544 /* SPI1 Masked Interrupt Condition Register */
1318#define SPI1_ILAT_CLR 0xFFC40548 /* SPI1 Masked Interrupt Clear Register */
1319#define SPI1_RFIFO 0xFFC40550 /* SPI1 Receive FIFO Data Register */
1320#define SPI1_TFIFO 0xFFC40558 /* SPI1 Transmit FIFO Data Register */
1321
1322/* =========================
1323 SPORT Registers
1324 ========================= */
1325
1326/* =========================
1327 SPORT0
1328 ========================= */
1329#define SPORT0_CTL_A 0xFFC40000 /* SPORT0 'A' Control Register */
1330#define SPORT0_DIV_A 0xFFC40004 /* SPORT0 'A' Clock and FS Divide Register */
1331#define SPORT0_MCTL_A 0xFFC40008 /* SPORT0 'A' Multichannel Control Register */
1332#define SPORT0_CS0_A 0xFFC4000C /* SPORT0 'A' Multichannel Select Register (Channels 0-31) */
1333#define SPORT0_CS1_A 0xFFC40010 /* SPORT0 'A' Multichannel Select Register (Channels 32-63) */
1334#define SPORT0_CS2_A 0xFFC40014 /* SPORT0 'A' Multichannel Select Register (Channels 64-95) */
1335#define SPORT0_CS3_A 0xFFC40018 /* SPORT0 'A' Multichannel Select Register (Channels 96-127) */
1336#define SPORT0_CNT_A 0xFFC4001C /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */
1337#define SPORT0_ERR_A 0xFFC40020 /* SPORT0 'A' Error Register */
1338#define SPORT0_MSTAT_A 0xFFC40024 /* SPORT0 'A' Multichannel Mode Status Register */
1339#define SPORT0_CTL2_A 0xFFC40028 /* SPORT0 'A' Control Register 2 */
1340#define SPORT0_TXPRI_A 0xFFC40040 /* SPORT0 'A' Primary Channel Transmit Buffer Register */
1341#define SPORT0_RXPRI_A 0xFFC40044 /* SPORT0 'A' Primary Channel Receive Buffer Register */
1342#define SPORT0_TXSEC_A 0xFFC40048 /* SPORT0 'A' Secondary Channel Transmit Buffer Register */
1343#define SPORT0_RXSEC_A 0xFFC4004C /* SPORT0 'A' Secondary Channel Receive Buffer Register */
1344#define SPORT0_CTL_B 0xFFC40080 /* SPORT0 'B' Control Register */
1345#define SPORT0_DIV_B 0xFFC40084 /* SPORT0 'B' Clock and FS Divide Register */
1346#define SPORT0_MCTL_B 0xFFC40088 /* SPORT0 'B' Multichannel Control Register */
1347#define SPORT0_CS0_B 0xFFC4008C /* SPORT0 'B' Multichannel Select Register (Channels 0-31) */
1348#define SPORT0_CS1_B 0xFFC40090 /* SPORT0 'B' Multichannel Select Register (Channels 32-63) */
1349#define SPORT0_CS2_B 0xFFC40094 /* SPORT0 'B' Multichannel Select Register (Channels 64-95) */
1350#define SPORT0_CS3_B 0xFFC40098 /* SPORT0 'B' Multichannel Select Register (Channels 96-127) */
1351#define SPORT0_CNT_B 0xFFC4009C /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */
1352#define SPORT0_ERR_B 0xFFC400A0 /* SPORT0 'B' Error Register */
1353#define SPORT0_MSTAT_B 0xFFC400A4 /* SPORT0 'B' Multichannel Mode Status Register */
1354#define SPORT0_CTL2_B 0xFFC400A8 /* SPORT0 'B' Control Register 2 */
1355#define SPORT0_TXPRI_B 0xFFC400C0 /* SPORT0 'B' Primary Channel Transmit Buffer Register */
1356#define SPORT0_RXPRI_B 0xFFC400C4 /* SPORT0 'B' Primary Channel Receive Buffer Register */
1357#define SPORT0_TXSEC_B 0xFFC400C8 /* SPORT0 'B' Secondary Channel Transmit Buffer Register */
1358#define SPORT0_RXSEC_B 0xFFC400CC /* SPORT0 'B' Secondary Channel Receive Buffer Register */
1359
1360/* =========================
1361 SPORT1
1362 ========================= */
1363#define SPORT1_CTL_A 0xFFC40100 /* SPORT1 'A' Control Register */
1364#define SPORT1_DIV_A 0xFFC40104 /* SPORT1 'A' Clock and FS Divide Register */
1365#define SPORT1_MCTL_A 0xFFC40108 /* SPORT1 'A' Multichannel Control Register */
1366#define SPORT1_CS0_A 0xFFC4010C /* SPORT1 'A' Multichannel Select Register (Channels 0-31) */
1367#define SPORT1_CS1_A 0xFFC40110 /* SPORT1 'A' Multichannel Select Register (Channels 32-63) */
1368#define SPORT1_CS2_A 0xFFC40114 /* SPORT1 'A' Multichannel Select Register (Channels 64-95) */
1369#define SPORT1_CS3_A 0xFFC40118 /* SPORT1 'A' Multichannel Select Register (Channels 96-127) */
1370#define SPORT1_CNT_A 0xFFC4011C /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */
1371#define SPORT1_ERR_A 0xFFC40120 /* SPORT1 'A' Error Register */
1372#define SPORT1_MSTAT_A 0xFFC40124 /* SPORT1 'A' Multichannel Mode Status Register */
1373#define SPORT1_CTL2_A 0xFFC40128 /* SPORT1 'A' Control Register 2 */
1374#define SPORT1_TXPRI_A 0xFFC40140 /* SPORT1 'A' Primary Channel Transmit Buffer Register */
1375#define SPORT1_RXPRI_A 0xFFC40144 /* SPORT1 'A' Primary Channel Receive Buffer Register */
1376#define SPORT1_TXSEC_A 0xFFC40148 /* SPORT1 'A' Secondary Channel Transmit Buffer Register */
1377#define SPORT1_RXSEC_A 0xFFC4014C /* SPORT1 'A' Secondary Channel Receive Buffer Register */
1378#define SPORT1_CTL_B 0xFFC40180 /* SPORT1 'B' Control Register */
1379#define SPORT1_DIV_B 0xFFC40184 /* SPORT1 'B' Clock and FS Divide Register */
1380#define SPORT1_MCTL_B 0xFFC40188 /* SPORT1 'B' Multichannel Control Register */
1381#define SPORT1_CS0_B 0xFFC4018C /* SPORT1 'B' Multichannel Select Register (Channels 0-31) */
1382#define SPORT1_CS1_B 0xFFC40190 /* SPORT1 'B' Multichannel Select Register (Channels 32-63) */
1383#define SPORT1_CS2_B 0xFFC40194 /* SPORT1 'B' Multichannel Select Register (Channels 64-95) */
1384#define SPORT1_CS3_B 0xFFC40198 /* SPORT1 'B' Multichannel Select Register (Channels 96-127) */
1385#define SPORT1_CNT_B 0xFFC4019C /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */
1386#define SPORT1_ERR_B 0xFFC401A0 /* SPORT1 'B' Error Register */
1387#define SPORT1_MSTAT_B 0xFFC401A4 /* SPORT1 'B' Multichannel Mode Status Register */
1388#define SPORT1_CTL2_B 0xFFC401A8 /* SPORT1 'B' Control Register 2 */
1389#define SPORT1_TXPRI_B 0xFFC401C0 /* SPORT1 'B' Primary Channel Transmit Buffer Register */
1390#define SPORT1_RXPRI_B 0xFFC401C4 /* SPORT1 'B' Primary Channel Receive Buffer Register */
1391#define SPORT1_TXSEC_B 0xFFC401C8 /* SPORT1 'B' Secondary Channel Transmit Buffer Register */
1392#define SPORT1_RXSEC_B 0xFFC401CC /* SPORT1 'B' Secondary Channel Receive Buffer Register */
1393
1394/* =========================
1395 SPORT2
1396 ========================= */
1397#define SPORT2_CTL_A 0xFFC40200 /* SPORT2 'A' Control Register */
1398#define SPORT2_DIV_A 0xFFC40204 /* SPORT2 'A' Clock and FS Divide Register */
1399#define SPORT2_MCTL_A 0xFFC40208 /* SPORT2 'A' Multichannel Control Register */
1400#define SPORT2_CS0_A 0xFFC4020C /* SPORT2 'A' Multichannel Select Register (Channels 0-31) */
1401#define SPORT2_CS1_A 0xFFC40210 /* SPORT2 'A' Multichannel Select Register (Channels 32-63) */
1402#define SPORT2_CS2_A 0xFFC40214 /* SPORT2 'A' Multichannel Select Register (Channels 64-95) */
1403#define SPORT2_CS3_A 0xFFC40218 /* SPORT2 'A' Multichannel Select Register (Channels 96-127) */
1404#define SPORT2_CNT_A 0xFFC4021C /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */
1405#define SPORT2_ERR_A 0xFFC40220 /* SPORT2 'A' Error Register */
1406#define SPORT2_MSTAT_A 0xFFC40224 /* SPORT2 'A' Multichannel Mode Status Register */
1407#define SPORT2_CTL2_A 0xFFC40228 /* SPORT2 'A' Control Register 2 */
1408#define SPORT2_TXPRI_A 0xFFC40240 /* SPORT2 'A' Primary Channel Transmit Buffer Register */
1409#define SPORT2_RXPRI_A 0xFFC40244 /* SPORT2 'A' Primary Channel Receive Buffer Register */
1410#define SPORT2_TXSEC_A 0xFFC40248 /* SPORT2 'A' Secondary Channel Transmit Buffer Register */
1411#define SPORT2_RXSEC_A 0xFFC4024C /* SPORT2 'A' Secondary Channel Receive Buffer Register */
1412#define SPORT2_CTL_B 0xFFC40280 /* SPORT2 'B' Control Register */
1413#define SPORT2_DIV_B 0xFFC40284 /* SPORT2 'B' Clock and FS Divide Register */
1414#define SPORT2_MCTL_B 0xFFC40288 /* SPORT2 'B' Multichannel Control Register */
1415#define SPORT2_CS0_B 0xFFC4028C /* SPORT2 'B' Multichannel Select Register (Channels 0-31) */
1416#define SPORT2_CS1_B 0xFFC40290 /* SPORT2 'B' Multichannel Select Register (Channels 32-63) */
1417#define SPORT2_CS2_B 0xFFC40294 /* SPORT2 'B' Multichannel Select Register (Channels 64-95) */
1418#define SPORT2_CS3_B 0xFFC40298 /* SPORT2 'B' Multichannel Select Register (Channels 96-127) */
1419#define SPORT2_CNT_B 0xFFC4029C /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */
1420#define SPORT2_ERR_B 0xFFC402A0 /* SPORT2 'B' Error Register */
1421#define SPORT2_MSTAT_B 0xFFC402A4 /* SPORT2 'B' Multichannel Mode Status Register */
1422#define SPORT2_CTL2_B 0xFFC402A8 /* SPORT2 'B' Control Register 2 */
1423#define SPORT2_TXPRI_B 0xFFC402C0 /* SPORT2 'B' Primary Channel Transmit Buffer Register */
1424#define SPORT2_RXPRI_B 0xFFC402C4 /* SPORT2 'B' Primary Channel Receive Buffer Register */
1425#define SPORT2_TXSEC_B 0xFFC402C8 /* SPORT2 'B' Secondary Channel Transmit Buffer Register */
1426#define SPORT2_RXSEC_B 0xFFC402CC /* SPORT2 'B' Secondary Channel Receive Buffer Register */
1427
1428/* =========================
1429 EPPI Registers
1430 ========================= */
1431
1432/* =========================
1433 EPPI0
1434 ========================= */
1435#define EPPI0_STAT 0xFFC18000 /* EPPI0 Status Register */
1436#define EPPI0_HCNT 0xFFC18004 /* EPPI0 Horizontal Transfer Count Register */
1437#define EPPI0_HDLY 0xFFC18008 /* EPPI0 Horizontal Delay Count Register */
1438#define EPPI0_VCNT 0xFFC1800C /* EPPI0 Vertical Transfer Count Register */
1439#define EPPI0_VDLY 0xFFC18010 /* EPPI0 Vertical Delay Count Register */
1440#define EPPI0_FRAME 0xFFC18014 /* EPPI0 Lines Per Frame Register */
1441#define EPPI0_LINE 0xFFC18018 /* EPPI0 Samples Per Line Register */
1442#define EPPI0_CLKDIV 0xFFC1801C /* EPPI0 Clock Divide Register */
1443#define EPPI0_CTL 0xFFC18020 /* EPPI0 Control Register */
1444#define EPPI0_FS1_WLHB 0xFFC18024 /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
1445#define EPPI0_FS1_PASPL 0xFFC18028 /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
1446#define EPPI0_FS2_WLVB 0xFFC1802C /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
1447#define EPPI0_FS2_PALPF 0xFFC18030 /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
1448#define EPPI0_IMSK 0xFFC18034 /* EPPI0 Interrupt Mask Register */
1449#define EPPI0_ODDCLIP 0xFFC1803C /* EPPI0 Clipping Register for ODD (Chroma) Data */
1450#define EPPI0_EVENCLIP 0xFFC18040 /* EPPI0 Clipping Register for EVEN (Luma) Data */
1451#define EPPI0_FS1_DLY 0xFFC18044 /* EPPI0 Frame Sync 1 Delay Value */
1452#define EPPI0_FS2_DLY 0xFFC18048 /* EPPI0 Frame Sync 2 Delay Value */
1453#define EPPI0_CTL2 0xFFC1804C /* EPPI0 Control Register 2 */
1454
1455/* =========================
1456 EPPI1
1457 ========================= */
1458#define EPPI1_STAT 0xFFC18400 /* EPPI1 Status Register */
1459#define EPPI1_HCNT 0xFFC18404 /* EPPI1 Horizontal Transfer Count Register */
1460#define EPPI1_HDLY 0xFFC18408 /* EPPI1 Horizontal Delay Count Register */
1461#define EPPI1_VCNT 0xFFC1840C /* EPPI1 Vertical Transfer Count Register */
1462#define EPPI1_VDLY 0xFFC18410 /* EPPI1 Vertical Delay Count Register */
1463#define EPPI1_FRAME 0xFFC18414 /* EPPI1 Lines Per Frame Register */
1464#define EPPI1_LINE 0xFFC18418 /* EPPI1 Samples Per Line Register */
1465#define EPPI1_CLKDIV 0xFFC1841C /* EPPI1 Clock Divide Register */
1466#define EPPI1_CTL 0xFFC18420 /* EPPI1 Control Register */
1467#define EPPI1_FS1_WLHB 0xFFC18424 /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
1468#define EPPI1_FS1_PASPL 0xFFC18428 /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
1469#define EPPI1_FS2_WLVB 0xFFC1842C /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
1470#define EPPI1_FS2_PALPF 0xFFC18430 /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
1471#define EPPI1_IMSK 0xFFC18434 /* EPPI1 Interrupt Mask Register */
1472#define EPPI1_ODDCLIP 0xFFC1843C /* EPPI1 Clipping Register for ODD (Chroma) Data */
1473#define EPPI1_EVENCLIP 0xFFC18440 /* EPPI1 Clipping Register for EVEN (Luma) Data */
1474#define EPPI1_FS1_DLY 0xFFC18444 /* EPPI1 Frame Sync 1 Delay Value */
1475#define EPPI1_FS2_DLY 0xFFC18448 /* EPPI1 Frame Sync 2 Delay Value */
1476#define EPPI1_CTL2 0xFFC1844C /* EPPI1 Control Register 2 */
1477
1478/* =========================
1479 EPPI2
1480 ========================= */
1481#define EPPI2_STAT 0xFFC18800 /* EPPI2 Status Register */
1482#define EPPI2_HCNT 0xFFC18804 /* EPPI2 Horizontal Transfer Count Register */
1483#define EPPI2_HDLY 0xFFC18808 /* EPPI2 Horizontal Delay Count Register */
1484#define EPPI2_VCNT 0xFFC1880C /* EPPI2 Vertical Transfer Count Register */
1485#define EPPI2_VDLY 0xFFC18810 /* EPPI2 Vertical Delay Count Register */
1486#define EPPI2_FRAME 0xFFC18814 /* EPPI2 Lines Per Frame Register */
1487#define EPPI2_LINE 0xFFC18818 /* EPPI2 Samples Per Line Register */
1488#define EPPI2_CLKDIV 0xFFC1881C /* EPPI2 Clock Divide Register */
1489#define EPPI2_CTL 0xFFC18820 /* EPPI2 Control Register */
1490#define EPPI2_FS1_WLHB 0xFFC18824 /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
1491#define EPPI2_FS1_PASPL 0xFFC18828 /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
1492#define EPPI2_FS2_WLVB 0xFFC1882C /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
1493#define EPPI2_FS2_PALPF 0xFFC18830 /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
1494#define EPPI2_IMSK 0xFFC18834 /* EPPI2 Interrupt Mask Register */
1495#define EPPI2_ODDCLIP 0xFFC1883C /* EPPI2 Clipping Register for ODD (Chroma) Data */
1496#define EPPI2_EVENCLIP 0xFFC18840 /* EPPI2 Clipping Register for EVEN (Luma) Data */
1497#define EPPI2_FS1_DLY 0xFFC18844 /* EPPI2 Frame Sync 1 Delay Value */
1498#define EPPI2_FS2_DLY 0xFFC18848 /* EPPI2 Frame Sync 2 Delay Value */
1499#define EPPI2_CTL2 0xFFC1884C /* EPPI2 Control Register 2 */
1500
1501
1502
1503/* =========================
1504 DDE Registers
1505 ========================= */
1506
1507/* =========================
1508 DMA0
1509 ========================= */
1510#define DMA0_NEXT_DESC_PTR 0xFFC41000 /* DMA0 Pointer to Next Initial Descriptor */
1511#define DMA0_START_ADDR 0xFFC41004 /* DMA0 Start Address of Current Buffer */
1512#define DMA0_CONFIG 0xFFC41008 /* DMA0 Configuration Register */
1513#define DMA0_X_COUNT 0xFFC4100C /* DMA0 Inner Loop Count Start Value */
1514#define DMA0_X_MODIFY 0xFFC41010 /* DMA0 Inner Loop Address Increment */
1515#define DMA0_Y_COUNT 0xFFC41014 /* DMA0 Outer Loop Count Start Value (2D only) */
1516#define DMA0_Y_MODIFY 0xFFC41018 /* DMA0 Outer Loop Address Increment (2D only) */
1517#define DMA0_CURR_DESC_PTR 0xFFC41024 /* DMA0 Current Descriptor Pointer */
1518#define DMA0_PREV_DESC_PTR 0xFFC41028 /* DMA0 Previous Initial Descriptor Pointer */
1519#define DMA0_CURR_ADDR 0xFFC4102C /* DMA0 Current Address */
1520#define DMA0_IRQ_STATUS 0xFFC41030 /* DMA0 Status Register */
1521#define DMA0_CURR_X_COUNT 0xFFC41034 /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
1522#define DMA0_CURR_Y_COUNT 0xFFC41038 /* DMA0 Current Row Count (2D only) */
1523#define DMA0_BWL_COUNT 0xFFC41040 /* DMA0 Bandwidth Limit Count */
1524#define DMA0_CURR_BWL_COUNT 0xFFC41044 /* DMA0 Bandwidth Limit Count Current */
1525#define DMA0_BWM_COUNT 0xFFC41048 /* DMA0 Bandwidth Monitor Count */
1526#define DMA0_CURR_BWM_COUNT 0xFFC4104C /* DMA0 Bandwidth Monitor Count Current */
1527
1528/* =========================
1529 DMA1
1530 ========================= */
1531#define DMA1_NEXT_DESC_PTR 0xFFC41080 /* DMA1 Pointer to Next Initial Descriptor */
1532#define DMA1_START_ADDR 0xFFC41084 /* DMA1 Start Address of Current Buffer */
1533#define DMA1_CONFIG 0xFFC41088 /* DMA1 Configuration Register */
1534#define DMA1_X_COUNT 0xFFC4108C /* DMA1 Inner Loop Count Start Value */
1535#define DMA1_X_MODIFY 0xFFC41090 /* DMA1 Inner Loop Address Increment */
1536#define DMA1_Y_COUNT 0xFFC41094 /* DMA1 Outer Loop Count Start Value (2D only) */
1537#define DMA1_Y_MODIFY 0xFFC41098 /* DMA1 Outer Loop Address Increment (2D only) */
1538#define DMA1_CURR_DESC_PTR 0xFFC410A4 /* DMA1 Current Descriptor Pointer */
1539#define DMA1_PREV_DESC_PTR 0xFFC410A8 /* DMA1 Previous Initial Descriptor Pointer */
1540#define DMA1_CURR_ADDR 0xFFC410AC /* DMA1 Current Address */
1541#define DMA1_IRQ_STATUS 0xFFC410B0 /* DMA1 Status Register */
1542#define DMA1_CURR_X_COUNT 0xFFC410B4 /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
1543#define DMA1_CURR_Y_COUNT 0xFFC410B8 /* DMA1 Current Row Count (2D only) */
1544#define DMA1_BWL_COUNT 0xFFC410C0 /* DMA1 Bandwidth Limit Count */
1545#define DMA1_CURR_BWL_COUNT 0xFFC410C4 /* DMA1 Bandwidth Limit Count Current */
1546#define DMA1_BWM_COUNT 0xFFC410C8 /* DMA1 Bandwidth Monitor Count */
1547#define DMA1_CURR_BWM_COUNT 0xFFC410CC /* DMA1 Bandwidth Monitor Count Current */
1548
1549/* =========================
1550 DMA2
1551 ========================= */
1552#define DMA2_NEXT_DESC_PTR 0xFFC41100 /* DMA2 Pointer to Next Initial Descriptor */
1553#define DMA2_START_ADDR 0xFFC41104 /* DMA2 Start Address of Current Buffer */
1554#define DMA2_CONFIG 0xFFC41108 /* DMA2 Configuration Register */
1555#define DMA2_X_COUNT 0xFFC4110C /* DMA2 Inner Loop Count Start Value */
1556#define DMA2_X_MODIFY 0xFFC41110 /* DMA2 Inner Loop Address Increment */
1557#define DMA2_Y_COUNT 0xFFC41114 /* DMA2 Outer Loop Count Start Value (2D only) */
1558#define DMA2_Y_MODIFY 0xFFC41118 /* DMA2 Outer Loop Address Increment (2D only) */
1559#define DMA2_CURR_DESC_PTR 0xFFC41124 /* DMA2 Current Descriptor Pointer */
1560#define DMA2_PREV_DESC_PTR 0xFFC41128 /* DMA2 Previous Initial Descriptor Pointer */
1561#define DMA2_CURR_ADDR 0xFFC4112C /* DMA2 Current Address */
1562#define DMA2_IRQ_STATUS 0xFFC41130 /* DMA2 Status Register */
1563#define DMA2_CURR_X_COUNT 0xFFC41134 /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
1564#define DMA2_CURR_Y_COUNT 0xFFC41138 /* DMA2 Current Row Count (2D only) */
1565#define DMA2_BWL_COUNT 0xFFC41140 /* DMA2 Bandwidth Limit Count */
1566#define DMA2_CURR_BWL_COUNT 0xFFC41144 /* DMA2 Bandwidth Limit Count Current */
1567#define DMA2_BWM_COUNT 0xFFC41148 /* DMA2 Bandwidth Monitor Count */
1568#define DMA2_CURR_BWM_COUNT 0xFFC4114C /* DMA2 Bandwidth Monitor Count Current */
1569
1570/* =========================
1571 DMA3
1572 ========================= */
1573#define DMA3_NEXT_DESC_PTR 0xFFC41180 /* DMA3 Pointer to Next Initial Descriptor */
1574#define DMA3_START_ADDR 0xFFC41184 /* DMA3 Start Address of Current Buffer */
1575#define DMA3_CONFIG 0xFFC41188 /* DMA3 Configuration Register */
1576#define DMA3_X_COUNT 0xFFC4118C /* DMA3 Inner Loop Count Start Value */
1577#define DMA3_X_MODIFY 0xFFC41190 /* DMA3 Inner Loop Address Increment */
1578#define DMA3_Y_COUNT 0xFFC41194 /* DMA3 Outer Loop Count Start Value (2D only) */
1579#define DMA3_Y_MODIFY 0xFFC41198 /* DMA3 Outer Loop Address Increment (2D only) */
1580#define DMA3_CURR_DESC_PTR 0xFFC411A4 /* DMA3 Current Descriptor Pointer */
1581#define DMA3_PREV_DESC_PTR 0xFFC411A8 /* DMA3 Previous Initial Descriptor Pointer */
1582#define DMA3_CURR_ADDR 0xFFC411AC /* DMA3 Current Address */
1583#define DMA3_IRQ_STATUS 0xFFC411B0 /* DMA3 Status Register */
1584#define DMA3_CURR_X_COUNT 0xFFC411B4 /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
1585#define DMA3_CURR_Y_COUNT 0xFFC411B8 /* DMA3 Current Row Count (2D only) */
1586#define DMA3_BWL_COUNT 0xFFC411C0 /* DMA3 Bandwidth Limit Count */
1587#define DMA3_CURR_BWL_COUNT 0xFFC411C4 /* DMA3 Bandwidth Limit Count Current */
1588#define DMA3_BWM_COUNT 0xFFC411C8 /* DMA3 Bandwidth Monitor Count */
1589#define DMA3_CURR_BWM_COUNT 0xFFC411CC /* DMA3 Bandwidth Monitor Count Current */
1590
1591/* =========================
1592 DMA4
1593 ========================= */
1594#define DMA4_NEXT_DESC_PTR 0xFFC41200 /* DMA4 Pointer to Next Initial Descriptor */
1595#define DMA4_START_ADDR 0xFFC41204 /* DMA4 Start Address of Current Buffer */
1596#define DMA4_CONFIG 0xFFC41208 /* DMA4 Configuration Register */
1597#define DMA4_X_COUNT 0xFFC4120C /* DMA4 Inner Loop Count Start Value */
1598#define DMA4_X_MODIFY 0xFFC41210 /* DMA4 Inner Loop Address Increment */
1599#define DMA4_Y_COUNT 0xFFC41214 /* DMA4 Outer Loop Count Start Value (2D only) */
1600#define DMA4_Y_MODIFY 0xFFC41218 /* DMA4 Outer Loop Address Increment (2D only) */
1601#define DMA4_CURR_DESC_PTR 0xFFC41224 /* DMA4 Current Descriptor Pointer */
1602#define DMA4_PREV_DESC_PTR 0xFFC41228 /* DMA4 Previous Initial Descriptor Pointer */
1603#define DMA4_CURR_ADDR 0xFFC4122C /* DMA4 Current Address */
1604#define DMA4_IRQ_STATUS 0xFFC41230 /* DMA4 Status Register */
1605#define DMA4_CURR_X_COUNT 0xFFC41234 /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
1606#define DMA4_CURR_Y_COUNT 0xFFC41238 /* DMA4 Current Row Count (2D only) */
1607#define DMA4_BWL_COUNT 0xFFC41240 /* DMA4 Bandwidth Limit Count */
1608#define DMA4_CURR_BWL_COUNT 0xFFC41244 /* DMA4 Bandwidth Limit Count Current */
1609#define DMA4_BWM_COUNT 0xFFC41248 /* DMA4 Bandwidth Monitor Count */
1610#define DMA4_CURR_BWM_COUNT 0xFFC4124C /* DMA4 Bandwidth Monitor Count Current */
1611
1612/* =========================
1613 DMA5
1614 ========================= */
1615#define DMA5_NEXT_DESC_PTR 0xFFC41280 /* DMA5 Pointer to Next Initial Descriptor */
1616#define DMA5_START_ADDR 0xFFC41284 /* DMA5 Start Address of Current Buffer */
1617#define DMA5_CONFIG 0xFFC41288 /* DMA5 Configuration Register */
1618#define DMA5_X_COUNT 0xFFC4128C /* DMA5 Inner Loop Count Start Value */
1619#define DMA5_X_MODIFY 0xFFC41290 /* DMA5 Inner Loop Address Increment */
1620#define DMA5_Y_COUNT 0xFFC41294 /* DMA5 Outer Loop Count Start Value (2D only) */
1621#define DMA5_Y_MODIFY 0xFFC41298 /* DMA5 Outer Loop Address Increment (2D only) */
1622#define DMA5_CURR_DESC_PTR 0xFFC412A4 /* DMA5 Current Descriptor Pointer */
1623#define DMA5_PREV_DESC_PTR 0xFFC412A8 /* DMA5 Previous Initial Descriptor Pointer */
1624#define DMA5_CURR_ADDR 0xFFC412AC /* DMA5 Current Address */
1625#define DMA5_IRQ_STATUS 0xFFC412B0 /* DMA5 Status Register */
1626#define DMA5_CURR_X_COUNT 0xFFC412B4 /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
1627#define DMA5_CURR_Y_COUNT 0xFFC412B8 /* DMA5 Current Row Count (2D only) */
1628#define DMA5_BWL_COUNT 0xFFC412C0 /* DMA5 Bandwidth Limit Count */
1629#define DMA5_CURR_BWL_COUNT 0xFFC412C4 /* DMA5 Bandwidth Limit Count Current */
1630#define DMA5_BWM_COUNT 0xFFC412C8 /* DMA5 Bandwidth Monitor Count */
1631#define DMA5_CURR_BWM_COUNT 0xFFC412CC /* DMA5 Bandwidth Monitor Count Current */
1632
1633/* =========================
1634 DMA6
1635 ========================= */
1636#define DMA6_NEXT_DESC_PTR 0xFFC41300 /* DMA6 Pointer to Next Initial Descriptor */
1637#define DMA6_START_ADDR 0xFFC41304 /* DMA6 Start Address of Current Buffer */
1638#define DMA6_CONFIG 0xFFC41308 /* DMA6 Configuration Register */
1639#define DMA6_X_COUNT 0xFFC4130C /* DMA6 Inner Loop Count Start Value */
1640#define DMA6_X_MODIFY 0xFFC41310 /* DMA6 Inner Loop Address Increment */
1641#define DMA6_Y_COUNT 0xFFC41314 /* DMA6 Outer Loop Count Start Value (2D only) */
1642#define DMA6_Y_MODIFY 0xFFC41318 /* DMA6 Outer Loop Address Increment (2D only) */
1643#define DMA6_CURR_DESC_PTR 0xFFC41324 /* DMA6 Current Descriptor Pointer */
1644#define DMA6_PREV_DESC_PTR 0xFFC41328 /* DMA6 Previous Initial Descriptor Pointer */
1645#define DMA6_CURR_ADDR 0xFFC4132C /* DMA6 Current Address */
1646#define DMA6_IRQ_STATUS 0xFFC41330 /* DMA6 Status Register */
1647#define DMA6_CURR_X_COUNT 0xFFC41334 /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
1648#define DMA6_CURR_Y_COUNT 0xFFC41338 /* DMA6 Current Row Count (2D only) */
1649#define DMA6_BWL_COUNT 0xFFC41340 /* DMA6 Bandwidth Limit Count */
1650#define DMA6_CURR_BWL_COUNT 0xFFC41344 /* DMA6 Bandwidth Limit Count Current */
1651#define DMA6_BWM_COUNT 0xFFC41348 /* DMA6 Bandwidth Monitor Count */
1652#define DMA6_CURR_BWM_COUNT 0xFFC4134C /* DMA6 Bandwidth Monitor Count Current */
1653
1654/* =========================
1655 DMA7
1656 ========================= */
1657#define DMA7_NEXT_DESC_PTR 0xFFC41380 /* DMA7 Pointer to Next Initial Descriptor */
1658#define DMA7_START_ADDR 0xFFC41384 /* DMA7 Start Address of Current Buffer */
1659#define DMA7_CONFIG 0xFFC41388 /* DMA7 Configuration Register */
1660#define DMA7_X_COUNT 0xFFC4138C /* DMA7 Inner Loop Count Start Value */
1661#define DMA7_X_MODIFY 0xFFC41390 /* DMA7 Inner Loop Address Increment */
1662#define DMA7_Y_COUNT 0xFFC41394 /* DMA7 Outer Loop Count Start Value (2D only) */
1663#define DMA7_Y_MODIFY 0xFFC41398 /* DMA7 Outer Loop Address Increment (2D only) */
1664#define DMA7_CURR_DESC_PTR 0xFFC413A4 /* DMA7 Current Descriptor Pointer */
1665#define DMA7_PREV_DESC_PTR 0xFFC413A8 /* DMA7 Previous Initial Descriptor Pointer */
1666#define DMA7_CURR_ADDR 0xFFC413AC /* DMA7 Current Address */
1667#define DMA7_IRQ_STATUS 0xFFC413B0 /* DMA7 Status Register */
1668#define DMA7_CURR_X_COUNT 0xFFC413B4 /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
1669#define DMA7_CURR_Y_COUNT 0xFFC413B8 /* DMA7 Current Row Count (2D only) */
1670#define DMA7_BWL_COUNT 0xFFC413C0 /* DMA7 Bandwidth Limit Count */
1671#define DMA7_CURR_BWL_COUNT 0xFFC413C4 /* DMA7 Bandwidth Limit Count Current */
1672#define DMA7_BWM_COUNT 0xFFC413C8 /* DMA7 Bandwidth Monitor Count */
1673#define DMA7_CURR_BWM_COUNT 0xFFC413CC /* DMA7 Bandwidth Monitor Count Current */
1674
1675/* =========================
1676 DMA8
1677 ========================= */
1678#define DMA8_NEXT_DESC_PTR 0xFFC41400 /* DMA8 Pointer to Next Initial Descriptor */
1679#define DMA8_START_ADDR 0xFFC41404 /* DMA8 Start Address of Current Buffer */
1680#define DMA8_CONFIG 0xFFC41408 /* DMA8 Configuration Register */
1681#define DMA8_X_COUNT 0xFFC4140C /* DMA8 Inner Loop Count Start Value */
1682#define DMA8_X_MODIFY 0xFFC41410 /* DMA8 Inner Loop Address Increment */
1683#define DMA8_Y_COUNT 0xFFC41414 /* DMA8 Outer Loop Count Start Value (2D only) */
1684#define DMA8_Y_MODIFY 0xFFC41418 /* DMA8 Outer Loop Address Increment (2D only) */
1685#define DMA8_CURR_DESC_PTR 0xFFC41424 /* DMA8 Current Descriptor Pointer */
1686#define DMA8_PREV_DESC_PTR 0xFFC41428 /* DMA8 Previous Initial Descriptor Pointer */
1687#define DMA8_CURR_ADDR 0xFFC4142C /* DMA8 Current Address */
1688#define DMA8_IRQ_STATUS 0xFFC41430 /* DMA8 Status Register */
1689#define DMA8_CURR_X_COUNT 0xFFC41434 /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
1690#define DMA8_CURR_Y_COUNT 0xFFC41438 /* DMA8 Current Row Count (2D only) */
1691#define DMA8_BWL_COUNT 0xFFC41440 /* DMA8 Bandwidth Limit Count */
1692#define DMA8_CURR_BWL_COUNT 0xFFC41444 /* DMA8 Bandwidth Limit Count Current */
1693#define DMA8_BWM_COUNT 0xFFC41448 /* DMA8 Bandwidth Monitor Count */
1694#define DMA8_CURR_BWM_COUNT 0xFFC4144C /* DMA8 Bandwidth Monitor Count Current */
1695
1696/* =========================
1697 DMA9
1698 ========================= */
1699#define DMA9_NEXT_DESC_PTR 0xFFC41480 /* DMA9 Pointer to Next Initial Descriptor */
1700#define DMA9_START_ADDR 0xFFC41484 /* DMA9 Start Address of Current Buffer */
1701#define DMA9_CONFIG 0xFFC41488 /* DMA9 Configuration Register */
1702#define DMA9_X_COUNT 0xFFC4148C /* DMA9 Inner Loop Count Start Value */
1703#define DMA9_X_MODIFY 0xFFC41490 /* DMA9 Inner Loop Address Increment */
1704#define DMA9_Y_COUNT 0xFFC41494 /* DMA9 Outer Loop Count Start Value (2D only) */
1705#define DMA9_Y_MODIFY 0xFFC41498 /* DMA9 Outer Loop Address Increment (2D only) */
1706#define DMA9_CURR_DESC_PTR 0xFFC414A4 /* DMA9 Current Descriptor Pointer */
1707#define DMA9_PREV_DESC_PTR 0xFFC414A8 /* DMA9 Previous Initial Descriptor Pointer */
1708#define DMA9_CURR_ADDR 0xFFC414AC /* DMA9 Current Address */
1709#define DMA9_IRQ_STATUS 0xFFC414B0 /* DMA9 Status Register */
1710#define DMA9_CURR_X_COUNT 0xFFC414B4 /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
1711#define DMA9_CURR_Y_COUNT 0xFFC414B8 /* DMA9 Current Row Count (2D only) */
1712#define DMA9_BWL_COUNT 0xFFC414C0 /* DMA9 Bandwidth Limit Count */
1713#define DMA9_CURR_BWL_COUNT 0xFFC414C4 /* DMA9 Bandwidth Limit Count Current */
1714#define DMA9_BWM_COUNT 0xFFC414C8 /* DMA9 Bandwidth Monitor Count */
1715#define DMA9_CURR_BWM_COUNT 0xFFC414CC /* DMA9 Bandwidth Monitor Count Current */
1716
1717/* =========================
1718 DMA10
1719 ========================= */
1720#define DMA10_NEXT_DESC_PTR 0xFFC05000 /* DMA10 Pointer to Next Initial Descriptor */
1721#define DMA10_START_ADDR 0xFFC05004 /* DMA10 Start Address of Current Buffer */
1722#define DMA10_CONFIG 0xFFC05008 /* DMA10 Configuration Register */
1723#define DMA10_X_COUNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */
1724#define DMA10_X_MODIFY 0xFFC05010 /* DMA10 Inner Loop Address Increment */
1725#define DMA10_Y_COUNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value (2D only) */
1726#define DMA10_Y_MODIFY 0xFFC05018 /* DMA10 Outer Loop Address Increment (2D only) */
1727#define DMA10_CURR_DESC_PTR 0xFFC05024 /* DMA10 Current Descriptor Pointer */
1728#define DMA10_PREV_DESC_PTR 0xFFC05028 /* DMA10 Previous Initial Descriptor Pointer */
1729#define DMA10_CURR_ADDR 0xFFC0502C /* DMA10 Current Address */
1730#define DMA10_IRQ_STATUS 0xFFC05030 /* DMA10 Status Register */
1731#define DMA10_CURR_X_COUNT 0xFFC05034 /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
1732#define DMA10_CURR_Y_COUNT 0xFFC05038 /* DMA10 Current Row Count (2D only) */
1733#define DMA10_BWL_COUNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */
1734#define DMA10_CURR_BWL_COUNT 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
1735#define DMA10_BWM_COUNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */
1736#define DMA10_CURR_BWM_COUNT 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current */
1737
1738/* =========================
1739 DMA11
1740 ========================= */
1741#define DMA11_NEXT_DESC_PTR 0xFFC05080 /* DMA11 Pointer to Next Initial Descriptor */
1742#define DMA11_START_ADDR 0xFFC05084 /* DMA11 Start Address of Current Buffer */
1743#define DMA11_CONFIG 0xFFC05088 /* DMA11 Configuration Register */
1744#define DMA11_X_COUNT 0xFFC0508C /* DMA11 Inner Loop Count Start Value */
1745#define DMA11_X_MODIFY 0xFFC05090 /* DMA11 Inner Loop Address Increment */
1746#define DMA11_Y_COUNT 0xFFC05094 /* DMA11 Outer Loop Count Start Value (2D only) */
1747#define DMA11_Y_MODIFY 0xFFC05098 /* DMA11 Outer Loop Address Increment (2D only) */
1748#define DMA11_CURR_DESC_PTR 0xFFC050A4 /* DMA11 Current Descriptor Pointer */
1749#define DMA11_PREV_DESC_PTR 0xFFC050A8 /* DMA11 Previous Initial Descriptor Pointer */
1750#define DMA11_CURR_ADDR 0xFFC050AC /* DMA11 Current Address */
1751#define DMA11_IRQ_STATUS 0xFFC050B0 /* DMA11 Status Register */
1752#define DMA11_CURR_X_COUNT 0xFFC050B4 /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
1753#define DMA11_CURR_Y_COUNT 0xFFC050B8 /* DMA11 Current Row Count (2D only) */
1754#define DMA11_BWL_COUNT 0xFFC050C0 /* DMA11 Bandwidth Limit Count */
1755#define DMA11_CURR_BWL_COUNT 0xFFC050C4 /* DMA11 Bandwidth Limit Count Current */
1756#define DMA11_BWM_COUNT 0xFFC050C8 /* DMA11 Bandwidth Monitor Count */
1757#define DMA11_CURR_BWM_COUNT 0xFFC050CC /* DMA11 Bandwidth Monitor Count Current */
1758
1759/* =========================
1760 DMA12
1761 ========================= */
1762#define DMA12_NEXT_DESC_PTR 0xFFC05100 /* DMA12 Pointer to Next Initial Descriptor */
1763#define DMA12_START_ADDR 0xFFC05104 /* DMA12 Start Address of Current Buffer */
1764#define DMA12_CONFIG 0xFFC05108 /* DMA12 Configuration Register */
1765#define DMA12_X_COUNT 0xFFC0510C /* DMA12 Inner Loop Count Start Value */
1766#define DMA12_X_MODIFY 0xFFC05110 /* DMA12 Inner Loop Address Increment */
1767#define DMA12_Y_COUNT 0xFFC05114 /* DMA12 Outer Loop Count Start Value (2D only) */
1768#define DMA12_Y_MODIFY 0xFFC05118 /* DMA12 Outer Loop Address Increment (2D only) */
1769#define DMA12_CURR_DESC_PTR 0xFFC05124 /* DMA12 Current Descriptor Pointer */
1770#define DMA12_PREV_DESC_PTR 0xFFC05128 /* DMA12 Previous Initial Descriptor Pointer */
1771#define DMA12_CURR_ADDR 0xFFC0512C /* DMA12 Current Address */
1772#define DMA12_IRQ_STATUS 0xFFC05130 /* DMA12 Status Register */
1773#define DMA12_CURR_X_COUNT 0xFFC05134 /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
1774#define DMA12_CURR_Y_COUNT 0xFFC05138 /* DMA12 Current Row Count (2D only) */
1775#define DMA12_BWL_COUNT 0xFFC05140 /* DMA12 Bandwidth Limit Count */
1776#define DMA12_CURR_BWL_COUNT 0xFFC05144 /* DMA12 Bandwidth Limit Count Current */
1777#define DMA12_BWM_COUNT 0xFFC05148 /* DMA12 Bandwidth Monitor Count */
1778#define DMA12_CURR_BWM_COUNT 0xFFC0514C /* DMA12 Bandwidth Monitor Count Current */
1779
1780/* =========================
1781 DMA13
1782 ========================= */
1783#define DMA13_NEXT_DESC_PTR 0xFFC07000 /* DMA13 Pointer to Next Initial Descriptor */
1784#define DMA13_START_ADDR 0xFFC07004 /* DMA13 Start Address of Current Buffer */
1785#define DMA13_CONFIG 0xFFC07008 /* DMA13 Configuration Register */
1786#define DMA13_X_COUNT 0xFFC0700C /* DMA13 Inner Loop Count Start Value */
1787#define DMA13_X_MODIFY 0xFFC07010 /* DMA13 Inner Loop Address Increment */
1788#define DMA13_Y_COUNT 0xFFC07014 /* DMA13 Outer Loop Count Start Value (2D only) */
1789#define DMA13_Y_MODIFY 0xFFC07018 /* DMA13 Outer Loop Address Increment (2D only) */
1790#define DMA13_CURR_DESC_PTR 0xFFC07024 /* DMA13 Current Descriptor Pointer */
1791#define DMA13_PREV_DESC_PTR 0xFFC07028 /* DMA13 Previous Initial Descriptor Pointer */
1792#define DMA13_CURR_ADDR 0xFFC0702C /* DMA13 Current Address */
1793#define DMA13_IRQ_STATUS 0xFFC07030 /* DMA13 Status Register */
1794#define DMA13_CURR_X_COUNT 0xFFC07034 /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
1795#define DMA13_CURR_Y_COUNT 0xFFC07038 /* DMA13 Current Row Count (2D only) */
1796#define DMA13_BWL_COUNT 0xFFC07040 /* DMA13 Bandwidth Limit Count */
1797#define DMA13_CURR_BWL_COUNT 0xFFC07044 /* DMA13 Bandwidth Limit Count Current */
1798#define DMA13_BWM_COUNT 0xFFC07048 /* DMA13 Bandwidth Monitor Count */
1799#define DMA13_CURR_BWM_COUNT 0xFFC0704C /* DMA13 Bandwidth Monitor Count Current */
1800
1801/* =========================
1802 DMA14
1803 ========================= */
1804#define DMA14_NEXT_DESC_PTR 0xFFC07080 /* DMA14 Pointer to Next Initial Descriptor */
1805#define DMA14_START_ADDR 0xFFC07084 /* DMA14 Start Address of Current Buffer */
1806#define DMA14_CONFIG 0xFFC07088 /* DMA14 Configuration Register */
1807#define DMA14_X_COUNT 0xFFC0708C /* DMA14 Inner Loop Count Start Value */
1808#define DMA14_X_MODIFY 0xFFC07090 /* DMA14 Inner Loop Address Increment */
1809#define DMA14_Y_COUNT 0xFFC07094 /* DMA14 Outer Loop Count Start Value (2D only) */
1810#define DMA14_Y_MODIFY 0xFFC07098 /* DMA14 Outer Loop Address Increment (2D only) */
1811#define DMA14_CURR_DESC_PTR 0xFFC070A4 /* DMA14 Current Descriptor Pointer */
1812#define DMA14_PREV_DESC_PTR 0xFFC070A8 /* DMA14 Previous Initial Descriptor Pointer */
1813#define DMA14_CURR_ADDR 0xFFC070AC /* DMA14 Current Address */
1814#define DMA14_IRQ_STATUS 0xFFC070B0 /* DMA14 Status Register */
1815#define DMA14_CURR_X_COUNT 0xFFC070B4 /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
1816#define DMA14_CURR_Y_COUNT 0xFFC070B8 /* DMA14 Current Row Count (2D only) */
1817#define DMA14_BWL_COUNT 0xFFC070C0 /* DMA14 Bandwidth Limit Count */
1818#define DMA14_CURR_BWL_COUNT 0xFFC070C4 /* DMA14 Bandwidth Limit Count Current */
1819#define DMA14_BWM_COUNT 0xFFC070C8 /* DMA14 Bandwidth Monitor Count */
1820#define DMA14_CURR_BWM_COUNT 0xFFC070CC /* DMA14 Bandwidth Monitor Count Current */
1821
1822/* =========================
1823 DMA15
1824 ========================= */
1825#define DMA15_NEXT_DESC_PTR 0xFFC07100 /* DMA15 Pointer to Next Initial Descriptor */
1826#define DMA15_START_ADDR 0xFFC07104 /* DMA15 Start Address of Current Buffer */
1827#define DMA15_CONFIG 0xFFC07108 /* DMA15 Configuration Register */
1828#define DMA15_X_COUNT 0xFFC0710C /* DMA15 Inner Loop Count Start Value */
1829#define DMA15_X_MODIFY 0xFFC07110 /* DMA15 Inner Loop Address Increment */
1830#define DMA15_Y_COUNT 0xFFC07114 /* DMA15 Outer Loop Count Start Value (2D only) */
1831#define DMA15_Y_MODIFY 0xFFC07118 /* DMA15 Outer Loop Address Increment (2D only) */
1832#define DMA15_CURR_DESC_PTR 0xFFC07124 /* DMA15 Current Descriptor Pointer */
1833#define DMA15_PREV_DESC_PTR 0xFFC07128 /* DMA15 Previous Initial Descriptor Pointer */
1834#define DMA15_CURR_ADDR 0xFFC0712C /* DMA15 Current Address */
1835#define DMA15_IRQ_STATUS 0xFFC07130 /* DMA15 Status Register */
1836#define DMA15_CURR_X_COUNT 0xFFC07134 /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
1837#define DMA15_CURR_Y_COUNT 0xFFC07138 /* DMA15 Current Row Count (2D only) */
1838#define DMA15_BWL_COUNT 0xFFC07140 /* DMA15 Bandwidth Limit Count */
1839#define DMA15_CURR_BWL_COUNT 0xFFC07144 /* DMA15 Bandwidth Limit Count Current */
1840#define DMA15_BWM_COUNT 0xFFC07148 /* DMA15 Bandwidth Monitor Count */
1841#define DMA15_CURR_BWM_COUNT 0xFFC0714C /* DMA15 Bandwidth Monitor Count Current */
1842
1843/* =========================
1844 DMA16
1845 ========================= */
1846#define DMA16_NEXT_DESC_PTR 0xFFC07180 /* DMA16 Pointer to Next Initial Descriptor */
1847#define DMA16_START_ADDR 0xFFC07184 /* DMA16 Start Address of Current Buffer */
1848#define DMA16_CONFIG 0xFFC07188 /* DMA16 Configuration Register */
1849#define DMA16_X_COUNT 0xFFC0718C /* DMA16 Inner Loop Count Start Value */
1850#define DMA16_X_MODIFY 0xFFC07190 /* DMA16 Inner Loop Address Increment */
1851#define DMA16_Y_COUNT 0xFFC07194 /* DMA16 Outer Loop Count Start Value (2D only) */
1852#define DMA16_Y_MODIFY 0xFFC07198 /* DMA16 Outer Loop Address Increment (2D only) */
1853#define DMA16_CURR_DESC_PTR 0xFFC071A4 /* DMA16 Current Descriptor Pointer */
1854#define DMA16_PREV_DESC_PTR 0xFFC071A8 /* DMA16 Previous Initial Descriptor Pointer */
1855#define DMA16_CURR_ADDR 0xFFC071AC /* DMA16 Current Address */
1856#define DMA16_IRQ_STATUS 0xFFC071B0 /* DMA16 Status Register */
1857#define DMA16_CURR_X_COUNT 0xFFC071B4 /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
1858#define DMA16_CURR_Y_COUNT 0xFFC071B8 /* DMA16 Current Row Count (2D only) */
1859#define DMA16_BWL_COUNT 0xFFC071C0 /* DMA16 Bandwidth Limit Count */
1860#define DMA16_CURR_BWL_COUNT 0xFFC071C4 /* DMA16 Bandwidth Limit Count Current */
1861#define DMA16_BWM_COUNT 0xFFC071C8 /* DMA16 Bandwidth Monitor Count */
1862#define DMA16_CURR_BWM_COUNT 0xFFC071CC /* DMA16 Bandwidth Monitor Count Current */
1863
1864/* =========================
1865 DMA17
1866 ========================= */
1867#define DMA17_NEXT_DESC_PTR 0xFFC07200 /* DMA17 Pointer to Next Initial Descriptor */
1868#define DMA17_START_ADDR 0xFFC07204 /* DMA17 Start Address of Current Buffer */
1869#define DMA17_CONFIG 0xFFC07208 /* DMA17 Configuration Register */
1870#define DMA17_X_COUNT 0xFFC0720C /* DMA17 Inner Loop Count Start Value */
1871#define DMA17_X_MODIFY 0xFFC07210 /* DMA17 Inner Loop Address Increment */
1872#define DMA17_Y_COUNT 0xFFC07214 /* DMA17 Outer Loop Count Start Value (2D only) */
1873#define DMA17_Y_MODIFY 0xFFC07218 /* DMA17 Outer Loop Address Increment (2D only) */
1874#define DMA17_CURR_DESC_PTR 0xFFC07224 /* DMA17 Current Descriptor Pointer */
1875#define DMA17_PREV_DESC_PTR 0xFFC07228 /* DMA17 Previous Initial Descriptor Pointer */
1876#define DMA17_CURR_ADDR 0xFFC0722C /* DMA17 Current Address */
1877#define DMA17_IRQ_STATUS 0xFFC07230 /* DMA17 Status Register */
1878#define DMA17_CURR_X_COUNT 0xFFC07234 /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
1879#define DMA17_CURR_Y_COUNT 0xFFC07238 /* DMA17 Current Row Count (2D only) */
1880#define DMA17_BWL_COUNT 0xFFC07240 /* DMA17 Bandwidth Limit Count */
1881#define DMA17_CURR_BWL_COUNT 0xFFC07244 /* DMA17 Bandwidth Limit Count Current */
1882#define DMA17_BWM_COUNT 0xFFC07248 /* DMA17 Bandwidth Monitor Count */
1883#define DMA17_CURR_BWM_COUNT 0xFFC0724C /* DMA17 Bandwidth Monitor Count Current */
1884
1885/* =========================
1886 DMA18
1887 ========================= */
1888#define DMA18_NEXT_DESC_PTR 0xFFC07280 /* DMA18 Pointer to Next Initial Descriptor */
1889#define DMA18_START_ADDR 0xFFC07284 /* DMA18 Start Address of Current Buffer */
1890#define DMA18_CONFIG 0xFFC07288 /* DMA18 Configuration Register */
1891#define DMA18_X_COUNT 0xFFC0728C /* DMA18 Inner Loop Count Start Value */
1892#define DMA18_X_MODIFY 0xFFC07290 /* DMA18 Inner Loop Address Increment */
1893#define DMA18_Y_COUNT 0xFFC07294 /* DMA18 Outer Loop Count Start Value (2D only) */
1894#define DMA18_Y_MODIFY 0xFFC07298 /* DMA18 Outer Loop Address Increment (2D only) */
1895#define DMA18_CURR_DESC_PTR 0xFFC072A4 /* DMA18 Current Descriptor Pointer */
1896#define DMA18_PREV_DESC_PTR 0xFFC072A8 /* DMA18 Previous Initial Descriptor Pointer */
1897#define DMA18_CURR_ADDR 0xFFC072AC /* DMA18 Current Address */
1898#define DMA18_IRQ_STATUS 0xFFC072B0 /* DMA18 Status Register */
1899#define DMA18_CURR_X_COUNT 0xFFC072B4 /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
1900#define DMA18_CURR_Y_COUNT 0xFFC072B8 /* DMA18 Current Row Count (2D only) */
1901#define DMA18_BWL_COUNT 0xFFC072C0 /* DMA18 Bandwidth Limit Count */
1902#define DMA18_CURR_BWL_COUNT 0xFFC072C4 /* DMA18 Bandwidth Limit Count Current */
1903#define DMA18_BWM_COUNT 0xFFC072C8 /* DMA18 Bandwidth Monitor Count */
1904#define DMA18_CURR_BWM_COUNT 0xFFC072CC /* DMA18 Bandwidth Monitor Count Current */
1905
1906/* =========================
1907 DMA19
1908 ========================= */
1909#define DMA19_NEXT_DESC_PTR 0xFFC07300 /* DMA19 Pointer to Next Initial Descriptor */
1910#define DMA19_START_ADDR 0xFFC07304 /* DMA19 Start Address of Current Buffer */
1911#define DMA19_CONFIG 0xFFC07308 /* DMA19 Configuration Register */
1912#define DMA19_X_COUNT 0xFFC0730C /* DMA19 Inner Loop Count Start Value */
1913#define DMA19_X_MODIFY 0xFFC07310 /* DMA19 Inner Loop Address Increment */
1914#define DMA19_Y_COUNT 0xFFC07314 /* DMA19 Outer Loop Count Start Value (2D only) */
1915#define DMA19_Y_MODIFY 0xFFC07318 /* DMA19 Outer Loop Address Increment (2D only) */
1916#define DMA19_CURR_DESC_PTR 0xFFC07324 /* DMA19 Current Descriptor Pointer */
1917#define DMA19_PREV_DESC_PTR 0xFFC07328 /* DMA19 Previous Initial Descriptor Pointer */
1918#define DMA19_CURR_ADDR 0xFFC0732C /* DMA19 Current Address */
1919#define DMA19_IRQ_STATUS 0xFFC07330 /* DMA19 Status Register */
1920#define DMA19_CURR_X_COUNT 0xFFC07334 /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
1921#define DMA19_CURR_Y_COUNT 0xFFC07338 /* DMA19 Current Row Count (2D only) */
1922#define DMA19_BWL_COUNT 0xFFC07340 /* DMA19 Bandwidth Limit Count */
1923#define DMA19_CURR_BWL_COUNT 0xFFC07344 /* DMA19 Bandwidth Limit Count Current */
1924#define DMA19_BWM_COUNT 0xFFC07348 /* DMA19 Bandwidth Monitor Count */
1925#define DMA19_CURR_BWM_COUNT 0xFFC0734C /* DMA19 Bandwidth Monitor Count Current */
1926
1927/* =========================
1928 DMA20
1929 ========================= */
1930#define DMA20_NEXT_DESC_PTR 0xFFC07380 /* DMA20 Pointer to Next Initial Descriptor */
1931#define DMA20_START_ADDR 0xFFC07384 /* DMA20 Start Address of Current Buffer */
1932#define DMA20_CONFIG 0xFFC07388 /* DMA20 Configuration Register */
1933#define DMA20_X_COUNT 0xFFC0738C /* DMA20 Inner Loop Count Start Value */
1934#define DMA20_X_MODIFY 0xFFC07390 /* DMA20 Inner Loop Address Increment */
1935#define DMA20_Y_COUNT 0xFFC07394 /* DMA20 Outer Loop Count Start Value (2D only) */
1936#define DMA20_Y_MODIFY 0xFFC07398 /* DMA20 Outer Loop Address Increment (2D only) */
1937#define DMA20_CURR_DESC_PTR 0xFFC073A4 /* DMA20 Current Descriptor Pointer */
1938#define DMA20_PREV_DESC_PTR 0xFFC073A8 /* DMA20 Previous Initial Descriptor Pointer */
1939#define DMA20_CURR_ADDR 0xFFC073AC /* DMA20 Current Address */
1940#define DMA20_IRQ_STATUS 0xFFC073B0 /* DMA20 Status Register */
1941#define DMA20_CURR_X_COUNT 0xFFC073B4 /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
1942#define DMA20_CURR_Y_COUNT 0xFFC073B8 /* DMA20 Current Row Count (2D only) */
1943#define DMA20_BWL_COUNT 0xFFC073C0 /* DMA20 Bandwidth Limit Count */
1944#define DMA20_CURR_BWL_COUNT 0xFFC073C4 /* DMA20 Bandwidth Limit Count Current */
1945#define DMA20_BWM_COUNT 0xFFC073C8 /* DMA20 Bandwidth Monitor Count */
1946#define DMA20_CURR_BWM_COUNT 0xFFC073CC /* DMA20 Bandwidth Monitor Count Current */
1947
1948/* =========================
1949 DMA21
1950 ========================= */
1951#define DMA21_NEXT_DESC_PTR 0xFFC09000 /* DMA21 Pointer to Next Initial Descriptor */
1952#define DMA21_START_ADDR 0xFFC09004 /* DMA21 Start Address of Current Buffer */
1953#define DMA21_CONFIG 0xFFC09008 /* DMA21 Configuration Register */
1954#define DMA21_X_COUNT 0xFFC0900C /* DMA21 Inner Loop Count Start Value */
1955#define DMA21_X_MODIFY 0xFFC09010 /* DMA21 Inner Loop Address Increment */
1956#define DMA21_Y_COUNT 0xFFC09014 /* DMA21 Outer Loop Count Start Value (2D only) */
1957#define DMA21_Y_MODIFY 0xFFC09018 /* DMA21 Outer Loop Address Increment (2D only) */
1958#define DMA21_CURR_DESC_PTR 0xFFC09024 /* DMA21 Current Descriptor Pointer */
1959#define DMA21_PREV_DESC_PTR 0xFFC09028 /* DMA21 Previous Initial Descriptor Pointer */
1960#define DMA21_CURR_ADDR 0xFFC0902C /* DMA21 Current Address */
1961#define DMA21_IRQ_STATUS 0xFFC09030 /* DMA21 Status Register */
1962#define DMA21_CURR_X_COUNT 0xFFC09034 /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
1963#define DMA21_CURR_Y_COUNT 0xFFC09038 /* DMA21 Current Row Count (2D only) */
1964#define DMA21_BWL_COUNT 0xFFC09040 /* DMA21 Bandwidth Limit Count */
1965#define DMA21_CURR_BWL_COUNT 0xFFC09044 /* DMA21 Bandwidth Limit Count Current */
1966#define DMA21_BWM_COUNT 0xFFC09048 /* DMA21 Bandwidth Monitor Count */
1967#define DMA21_CURR_BWM_COUNT 0xFFC0904C /* DMA21 Bandwidth Monitor Count Current */
1968
1969/* =========================
1970 DMA22
1971 ========================= */
1972#define DMA22_NEXT_DESC_PTR 0xFFC09080 /* DMA22 Pointer to Next Initial Descriptor */
1973#define DMA22_START_ADDR 0xFFC09084 /* DMA22 Start Address of Current Buffer */
1974#define DMA22_CONFIG 0xFFC09088 /* DMA22 Configuration Register */
1975#define DMA22_X_COUNT 0xFFC0908C /* DMA22 Inner Loop Count Start Value */
1976#define DMA22_X_MODIFY 0xFFC09090 /* DMA22 Inner Loop Address Increment */
1977#define DMA22_Y_COUNT 0xFFC09094 /* DMA22 Outer Loop Count Start Value (2D only) */
1978#define DMA22_Y_MODIFY 0xFFC09098 /* DMA22 Outer Loop Address Increment (2D only) */
1979#define DMA22_CURR_DESC_PTR 0xFFC090A4 /* DMA22 Current Descriptor Pointer */
1980#define DMA22_PREV_DESC_PTR 0xFFC090A8 /* DMA22 Previous Initial Descriptor Pointer */
1981#define DMA22_CURR_ADDR 0xFFC090AC /* DMA22 Current Address */
1982#define DMA22_IRQ_STATUS 0xFFC090B0 /* DMA22 Status Register */
1983#define DMA22_CURR_X_COUNT 0xFFC090B4 /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
1984#define DMA22_CURR_Y_COUNT 0xFFC090B8 /* DMA22 Current Row Count (2D only) */
1985#define DMA22_BWL_COUNT 0xFFC090C0 /* DMA22 Bandwidth Limit Count */
1986#define DMA22_CURR_BWL_COUNT 0xFFC090C4 /* DMA22 Bandwidth Limit Count Current */
1987#define DMA22_BWM_COUNT 0xFFC090C8 /* DMA22 Bandwidth Monitor Count */
1988#define DMA22_CURR_BWM_COUNT 0xFFC090CC /* DMA22 Bandwidth Monitor Count Current */
1989
1990/* =========================
1991 DMA23
1992 ========================= */
1993#define DMA23_NEXT_DESC_PTR 0xFFC09100 /* DMA23 Pointer to Next Initial Descriptor */
1994#define DMA23_START_ADDR 0xFFC09104 /* DMA23 Start Address of Current Buffer */
1995#define DMA23_CONFIG 0xFFC09108 /* DMA23 Configuration Register */
1996#define DMA23_X_COUNT 0xFFC0910C /* DMA23 Inner Loop Count Start Value */
1997#define DMA23_X_MODIFY 0xFFC09110 /* DMA23 Inner Loop Address Increment */
1998#define DMA23_Y_COUNT 0xFFC09114 /* DMA23 Outer Loop Count Start Value (2D only) */
1999#define DMA23_Y_MODIFY 0xFFC09118 /* DMA23 Outer Loop Address Increment (2D only) */
2000#define DMA23_CURR_DESC_PTR 0xFFC09124 /* DMA23 Current Descriptor Pointer */
2001#define DMA23_PREV_DESC_PTR 0xFFC09128 /* DMA23 Previous Initial Descriptor Pointer */
2002#define DMA23_CURR_ADDR 0xFFC0912C /* DMA23 Current Address */
2003#define DMA23_IRQ_STATUS 0xFFC09130 /* DMA23 Status Register */
2004#define DMA23_CURR_X_COUNT 0xFFC09134 /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
2005#define DMA23_CURR_Y_COUNT 0xFFC09138 /* DMA23 Current Row Count (2D only) */
2006#define DMA23_BWL_COUNT 0xFFC09140 /* DMA23 Bandwidth Limit Count */
2007#define DMA23_CURR_BWL_COUNT 0xFFC09144 /* DMA23 Bandwidth Limit Count Current */
2008#define DMA23_BWM_COUNT 0xFFC09148 /* DMA23 Bandwidth Monitor Count */
2009#define DMA23_CURR_BWM_COUNT 0xFFC0914C /* DMA23 Bandwidth Monitor Count Current */
2010
2011/* =========================
2012 DMA24
2013 ========================= */
2014#define DMA24_NEXT_DESC_PTR 0xFFC09180 /* DMA24 Pointer to Next Initial Descriptor */
2015#define DMA24_START_ADDR 0xFFC09184 /* DMA24 Start Address of Current Buffer */
2016#define DMA24_CONFIG 0xFFC09188 /* DMA24 Configuration Register */
2017#define DMA24_X_COUNT 0xFFC0918C /* DMA24 Inner Loop Count Start Value */
2018#define DMA24_X_MODIFY 0xFFC09190 /* DMA24 Inner Loop Address Increment */
2019#define DMA24_Y_COUNT 0xFFC09194 /* DMA24 Outer Loop Count Start Value (2D only) */
2020#define DMA24_Y_MODIFY 0xFFC09198 /* DMA24 Outer Loop Address Increment (2D only) */
2021#define DMA24_CURR_DESC_PTR 0xFFC091A4 /* DMA24 Current Descriptor Pointer */
2022#define DMA24_PREV_DESC_PTR 0xFFC091A8 /* DMA24 Previous Initial Descriptor Pointer */
2023#define DMA24_CURR_ADDR 0xFFC091AC /* DMA24 Current Address */
2024#define DMA24_IRQ_STATUS 0xFFC091B0 /* DMA24 Status Register */
2025#define DMA24_CURR_X_COUNT 0xFFC091B4 /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
2026#define DMA24_CURR_Y_COUNT 0xFFC091B8 /* DMA24 Current Row Count (2D only) */
2027#define DMA24_BWL_COUNT 0xFFC091C0 /* DMA24 Bandwidth Limit Count */
2028#define DMA24_CURR_BWL_COUNT 0xFFC091C4 /* DMA24 Bandwidth Limit Count Current */
2029#define DMA24_BWM_COUNT 0xFFC091C8 /* DMA24 Bandwidth Monitor Count */
2030#define DMA24_CURR_BWM_COUNT 0xFFC091CC /* DMA24 Bandwidth Monitor Count Current */
2031
2032/* =========================
2033 DMA25
2034 ========================= */
2035#define DMA25_NEXT_DESC_PTR 0xFFC09200 /* DMA25 Pointer to Next Initial Descriptor */
2036#define DMA25_START_ADDR 0xFFC09204 /* DMA25 Start Address of Current Buffer */
2037#define DMA25_CONFIG 0xFFC09208 /* DMA25 Configuration Register */
2038#define DMA25_X_COUNT 0xFFC0920C /* DMA25 Inner Loop Count Start Value */
2039#define DMA25_X_MODIFY 0xFFC09210 /* DMA25 Inner Loop Address Increment */
2040#define DMA25_Y_COUNT 0xFFC09214 /* DMA25 Outer Loop Count Start Value (2D only) */
2041#define DMA25_Y_MODIFY 0xFFC09218 /* DMA25 Outer Loop Address Increment (2D only) */
2042#define DMA25_CURR_DESC_PTR 0xFFC09224 /* DMA25 Current Descriptor Pointer */
2043#define DMA25_PREV_DESC_PTR 0xFFC09228 /* DMA25 Previous Initial Descriptor Pointer */
2044#define DMA25_CURR_ADDR 0xFFC0922C /* DMA25 Current Address */
2045#define DMA25_IRQ_STATUS 0xFFC09230 /* DMA25 Status Register */
2046#define DMA25_CURR_X_COUNT 0xFFC09234 /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
2047#define DMA25_CURR_Y_COUNT 0xFFC09238 /* DMA25 Current Row Count (2D only) */
2048#define DMA25_BWL_COUNT 0xFFC09240 /* DMA25 Bandwidth Limit Count */
2049#define DMA25_CURR_BWL_COUNT 0xFFC09244 /* DMA25 Bandwidth Limit Count Current */
2050#define DMA25_BWM_COUNT 0xFFC09248 /* DMA25 Bandwidth Monitor Count */
2051#define DMA25_CURR_BWM_COUNT 0xFFC0924C /* DMA25 Bandwidth Monitor Count Current */
2052
2053/* =========================
2054 DMA26
2055 ========================= */
2056#define DMA26_NEXT_DESC_PTR 0xFFC09280 /* DMA26 Pointer to Next Initial Descriptor */
2057#define DMA26_START_ADDR 0xFFC09284 /* DMA26 Start Address of Current Buffer */
2058#define DMA26_CONFIG 0xFFC09288 /* DMA26 Configuration Register */
2059#define DMA26_X_COUNT 0xFFC0928C /* DMA26 Inner Loop Count Start Value */
2060#define DMA26_X_MODIFY 0xFFC09290 /* DMA26 Inner Loop Address Increment */
2061#define DMA26_Y_COUNT 0xFFC09294 /* DMA26 Outer Loop Count Start Value (2D only) */
2062#define DMA26_Y_MODIFY 0xFFC09298 /* DMA26 Outer Loop Address Increment (2D only) */
2063#define DMA26_CURR_DESC_PTR 0xFFC092A4 /* DMA26 Current Descriptor Pointer */
2064#define DMA26_PREV_DESC_PTR 0xFFC092A8 /* DMA26 Previous Initial Descriptor Pointer */
2065#define DMA26_CURR_ADDR 0xFFC092AC /* DMA26 Current Address */
2066#define DMA26_IRQ_STATUS 0xFFC092B0 /* DMA26 Status Register */
2067#define DMA26_CURR_X_COUNT 0xFFC092B4 /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
2068#define DMA26_CURR_Y_COUNT 0xFFC092B8 /* DMA26 Current Row Count (2D only) */
2069#define DMA26_BWL_COUNT 0xFFC092C0 /* DMA26 Bandwidth Limit Count */
2070#define DMA26_CURR_BWL_COUNT 0xFFC092C4 /* DMA26 Bandwidth Limit Count Current */
2071#define DMA26_BWM_COUNT 0xFFC092C8 /* DMA26 Bandwidth Monitor Count */
2072#define DMA26_CURR_BWM_COUNT 0xFFC092CC /* DMA26 Bandwidth Monitor Count Current */
2073
2074/* =========================
2075 DMA27
2076 ========================= */
2077#define DMA27_NEXT_DESC_PTR 0xFFC09300 /* DMA27 Pointer to Next Initial Descriptor */
2078#define DMA27_START_ADDR 0xFFC09304 /* DMA27 Start Address of Current Buffer */
2079#define DMA27_CONFIG 0xFFC09308 /* DMA27 Configuration Register */
2080#define DMA27_X_COUNT 0xFFC0930C /* DMA27 Inner Loop Count Start Value */
2081#define DMA27_X_MODIFY 0xFFC09310 /* DMA27 Inner Loop Address Increment */
2082#define DMA27_Y_COUNT 0xFFC09314 /* DMA27 Outer Loop Count Start Value (2D only) */
2083#define DMA27_Y_MODIFY 0xFFC09318 /* DMA27 Outer Loop Address Increment (2D only) */
2084#define DMA27_CURR_DESC_PTR 0xFFC09324 /* DMA27 Current Descriptor Pointer */
2085#define DMA27_PREV_DESC_PTR 0xFFC09328 /* DMA27 Previous Initial Descriptor Pointer */
2086#define DMA27_CURR_ADDR 0xFFC0932C /* DMA27 Current Address */
2087#define DMA27_IRQ_STATUS 0xFFC09330 /* DMA27 Status Register */
2088#define DMA27_CURR_X_COUNT 0xFFC09334 /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
2089#define DMA27_CURR_Y_COUNT 0xFFC09338 /* DMA27 Current Row Count (2D only) */
2090#define DMA27_BWL_COUNT 0xFFC09340 /* DMA27 Bandwidth Limit Count */
2091#define DMA27_CURR_BWL_COUNT 0xFFC09344 /* DMA27 Bandwidth Limit Count Current */
2092#define DMA27_BWM_COUNT 0xFFC09348 /* DMA27 Bandwidth Monitor Count */
2093#define DMA27_CURR_BWM_COUNT 0xFFC0934C /* DMA27 Bandwidth Monitor Count Current */
2094
2095/* =========================
2096 DMA28
2097 ========================= */
2098#define DMA28_NEXT_DESC_PTR 0xFFC09380 /* DMA28 Pointer to Next Initial Descriptor */
2099#define DMA28_START_ADDR 0xFFC09384 /* DMA28 Start Address of Current Buffer */
2100#define DMA28_CONFIG 0xFFC09388 /* DMA28 Configuration Register */
2101#define DMA28_X_COUNT 0xFFC0938C /* DMA28 Inner Loop Count Start Value */
2102#define DMA28_X_MODIFY 0xFFC09390 /* DMA28 Inner Loop Address Increment */
2103#define DMA28_Y_COUNT 0xFFC09394 /* DMA28 Outer Loop Count Start Value (2D only) */
2104#define DMA28_Y_MODIFY 0xFFC09398 /* DMA28 Outer Loop Address Increment (2D only) */
2105#define DMA28_CURR_DESC_PTR 0xFFC093A4 /* DMA28 Current Descriptor Pointer */
2106#define DMA28_PREV_DESC_PTR 0xFFC093A8 /* DMA28 Previous Initial Descriptor Pointer */
2107#define DMA28_CURR_ADDR 0xFFC093AC /* DMA28 Current Address */
2108#define DMA28_IRQ_STATUS 0xFFC093B0 /* DMA28 Status Register */
2109#define DMA28_CURR_X_COUNT 0xFFC093B4 /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
2110#define DMA28_CURR_Y_COUNT 0xFFC093B8 /* DMA28 Current Row Count (2D only) */
2111#define DMA28_BWL_COUNT 0xFFC093C0 /* DMA28 Bandwidth Limit Count */
2112#define DMA28_CURR_BWL_COUNT 0xFFC093C4 /* DMA28 Bandwidth Limit Count Current */
2113#define DMA28_BWM_COUNT 0xFFC093C8 /* DMA28 Bandwidth Monitor Count */
2114#define DMA28_CURR_BWM_COUNT 0xFFC093CC /* DMA28 Bandwidth Monitor Count Current */
2115
2116/* =========================
2117 DMA29
2118 ========================= */
2119#define DMA29_NEXT_DESC_PTR 0xFFC0B000 /* DMA29 Pointer to Next Initial Descriptor */
2120#define DMA29_START_ADDR 0xFFC0B004 /* DMA29 Start Address of Current Buffer */
2121#define DMA29_CONFIG 0xFFC0B008 /* DMA29 Configuration Register */
2122#define DMA29_X_COUNT 0xFFC0B00C /* DMA29 Inner Loop Count Start Value */
2123#define DMA29_X_MODIFY 0xFFC0B010 /* DMA29 Inner Loop Address Increment */
2124#define DMA29_Y_COUNT 0xFFC0B014 /* DMA29 Outer Loop Count Start Value (2D only) */
2125#define DMA29_Y_MODIFY 0xFFC0B018 /* DMA29 Outer Loop Address Increment (2D only) */
2126#define DMA29_CURR_DESC_PTR 0xFFC0B024 /* DMA29 Current Descriptor Pointer */
2127#define DMA29_PREV_DESC_PTR 0xFFC0B028 /* DMA29 Previous Initial Descriptor Pointer */
2128#define DMA29_CURR_ADDR 0xFFC0B02C /* DMA29 Current Address */
2129#define DMA29_IRQ_STATUS 0xFFC0B030 /* DMA29 Status Register */
2130#define DMA29_CURR_X_COUNT 0xFFC0B034 /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
2131#define DMA29_CURR_Y_COUNT 0xFFC0B038 /* DMA29 Current Row Count (2D only) */
2132#define DMA29_BWL_COUNT 0xFFC0B040 /* DMA29 Bandwidth Limit Count */
2133#define DMA29_CURR_BWL_COUNT 0xFFC0B044 /* DMA29 Bandwidth Limit Count Current */
2134#define DMA29_BWM_COUNT 0xFFC0B048 /* DMA29 Bandwidth Monitor Count */
2135#define DMA29_CURR_BWM_COUNT 0xFFC0B04C /* DMA29 Bandwidth Monitor Count Current */
2136
2137/* =========================
2138 DMA30
2139 ========================= */
2140#define DMA30_NEXT_DESC_PTR 0xFFC0B080 /* DMA30 Pointer to Next Initial Descriptor */
2141#define DMA30_START_ADDR 0xFFC0B084 /* DMA30 Start Address of Current Buffer */
2142#define DMA30_CONFIG 0xFFC0B088 /* DMA30 Configuration Register */
2143#define DMA30_X_COUNT 0xFFC0B08C /* DMA30 Inner Loop Count Start Value */
2144#define DMA30_X_MODIFY 0xFFC0B090 /* DMA30 Inner Loop Address Increment */
2145#define DMA30_Y_COUNT 0xFFC0B094 /* DMA30 Outer Loop Count Start Value (2D only) */
2146#define DMA30_Y_MODIFY 0xFFC0B098 /* DMA30 Outer Loop Address Increment (2D only) */
2147#define DMA30_CURR_DESC_PTR 0xFFC0B0A4 /* DMA30 Current Descriptor Pointer */
2148#define DMA30_PREV_DESC_PTR 0xFFC0B0A8 /* DMA30 Previous Initial Descriptor Pointer */
2149#define DMA30_CURR_ADDR 0xFFC0B0AC /* DMA30 Current Address */
2150#define DMA30_IRQ_STATUS 0xFFC0B0B0 /* DMA30 Status Register */
2151#define DMA30_CURR_X_COUNT 0xFFC0B0B4 /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
2152#define DMA30_CURR_Y_COUNT 0xFFC0B0B8 /* DMA30 Current Row Count (2D only) */
2153#define DMA30_BWL_COUNT 0xFFC0B0C0 /* DMA30 Bandwidth Limit Count */
2154#define DMA30_CURR_BWL_COUNT 0xFFC0B0C4 /* DMA30 Bandwidth Limit Count Current */
2155#define DMA30_BWM_COUNT 0xFFC0B0C8 /* DMA30 Bandwidth Monitor Count */
2156#define DMA30_CURR_BWM_COUNT 0xFFC0B0CC /* DMA30 Bandwidth Monitor Count Current */
2157
2158/* =========================
2159 DMA31
2160 ========================= */
2161#define DMA31_NEXT_DESC_PTR 0xFFC0B100 /* DMA31 Pointer to Next Initial Descriptor */
2162#define DMA31_START_ADDR 0xFFC0B104 /* DMA31 Start Address of Current Buffer */
2163#define DMA31_CONFIG 0xFFC0B108 /* DMA31 Configuration Register */
2164#define DMA31_X_COUNT 0xFFC0B10C /* DMA31 Inner Loop Count Start Value */
2165#define DMA31_X_MODIFY 0xFFC0B110 /* DMA31 Inner Loop Address Increment */
2166#define DMA31_Y_COUNT 0xFFC0B114 /* DMA31 Outer Loop Count Start Value (2D only) */
2167#define DMA31_Y_MODIFY 0xFFC0B118 /* DMA31 Outer Loop Address Increment (2D only) */
2168#define DMA31_CURR_DESC_PTR 0xFFC0B124 /* DMA31 Current Descriptor Pointer */
2169#define DMA31_PREV_DESC_PTR 0xFFC0B128 /* DMA31 Previous Initial Descriptor Pointer */
2170#define DMA31_CURR_ADDR 0xFFC0B12C /* DMA31 Current Address */
2171#define DMA31_IRQ_STATUS 0xFFC0B130 /* DMA31 Status Register */
2172#define DMA31_CURR_X_COUNT 0xFFC0B134 /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
2173#define DMA31_CURR_Y_COUNT 0xFFC0B138 /* DMA31 Current Row Count (2D only) */
2174#define DMA31_BWL_COUNT 0xFFC0B140 /* DMA31 Bandwidth Limit Count */
2175#define DMA31_CURR_BWL_COUNT 0xFFC0B144 /* DMA31 Bandwidth Limit Count Current */
2176#define DMA31_BWM_COUNT 0xFFC0B148 /* DMA31 Bandwidth Monitor Count */
2177#define DMA31_CURR_BWM_COUNT 0xFFC0B14C /* DMA31 Bandwidth Monitor Count Current */
2178
2179/* =========================
2180 DMA32
2181 ========================= */
2182#define DMA32_NEXT_DESC_PTR 0xFFC0B180 /* DMA32 Pointer to Next Initial Descriptor */
2183#define DMA32_START_ADDR 0xFFC0B184 /* DMA32 Start Address of Current Buffer */
2184#define DMA32_CONFIG 0xFFC0B188 /* DMA32 Configuration Register */
2185#define DMA32_X_COUNT 0xFFC0B18C /* DMA32 Inner Loop Count Start Value */
2186#define DMA32_X_MODIFY 0xFFC0B190 /* DMA32 Inner Loop Address Increment */
2187#define DMA32_Y_COUNT 0xFFC0B194 /* DMA32 Outer Loop Count Start Value (2D only) */
2188#define DMA32_Y_MODIFY 0xFFC0B198 /* DMA32 Outer Loop Address Increment (2D only) */
2189#define DMA32_CURR_DESC_PTR 0xFFC0B1A4 /* DMA32 Current Descriptor Pointer */
2190#define DMA32_PREV_DESC_PTR 0xFFC0B1A8 /* DMA32 Previous Initial Descriptor Pointer */
2191#define DMA32_CURR_ADDR 0xFFC0B1AC /* DMA32 Current Address */
2192#define DMA32_IRQ_STATUS 0xFFC0B1B0 /* DMA32 Status Register */
2193#define DMA32_CURR_X_COUNT 0xFFC0B1B4 /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
2194#define DMA32_CURR_Y_COUNT 0xFFC0B1B8 /* DMA32 Current Row Count (2D only) */
2195#define DMA32_BWL_COUNT 0xFFC0B1C0 /* DMA32 Bandwidth Limit Count */
2196#define DMA32_CURR_BWL_COUNT 0xFFC0B1C4 /* DMA32 Bandwidth Limit Count Current */
2197#define DMA32_BWM_COUNT 0xFFC0B1C8 /* DMA32 Bandwidth Monitor Count */
2198#define DMA32_CURR_BWM_COUNT 0xFFC0B1CC /* DMA32 Bandwidth Monitor Count Current */
2199
2200/* =========================
2201 DMA33
2202 ========================= */
2203#define DMA33_NEXT_DESC_PTR 0xFFC0D000 /* DMA33 Pointer to Next Initial Descriptor */
2204#define DMA33_START_ADDR 0xFFC0D004 /* DMA33 Start Address of Current Buffer */
2205#define DMA33_CONFIG 0xFFC0D008 /* DMA33 Configuration Register */
2206#define DMA33_X_COUNT 0xFFC0D00C /* DMA33 Inner Loop Count Start Value */
2207#define DMA33_X_MODIFY 0xFFC0D010 /* DMA33 Inner Loop Address Increment */
2208#define DMA33_Y_COUNT 0xFFC0D014 /* DMA33 Outer Loop Count Start Value (2D only) */
2209#define DMA33_Y_MODIFY 0xFFC0D018 /* DMA33 Outer Loop Address Increment (2D only) */
2210#define DMA33_CURR_DESC_PTR 0xFFC0D024 /* DMA33 Current Descriptor Pointer */
2211#define DMA33_PREV_DESC_PTR 0xFFC0D028 /* DMA33 Previous Initial Descriptor Pointer */
2212#define DMA33_CURR_ADDR 0xFFC0D02C /* DMA33 Current Address */
2213#define DMA33_IRQ_STATUS 0xFFC0D030 /* DMA33 Status Register */
2214#define DMA33_CURR_X_COUNT 0xFFC0D034 /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
2215#define DMA33_CURR_Y_COUNT 0xFFC0D038 /* DMA33 Current Row Count (2D only) */
2216#define DMA33_BWL_COUNT 0xFFC0D040 /* DMA33 Bandwidth Limit Count */
2217#define DMA33_CURR_BWL_COUNT 0xFFC0D044 /* DMA33 Bandwidth Limit Count Current */
2218#define DMA33_BWM_COUNT 0xFFC0D048 /* DMA33 Bandwidth Monitor Count */
2219#define DMA33_CURR_BWM_COUNT 0xFFC0D04C /* DMA33 Bandwidth Monitor Count Current */
2220
2221/* =========================
2222 DMA34
2223 ========================= */
2224#define DMA34_NEXT_DESC_PTR 0xFFC0D080 /* DMA34 Pointer to Next Initial Descriptor */
2225#define DMA34_START_ADDR 0xFFC0D084 /* DMA34 Start Address of Current Buffer */
2226#define DMA34_CONFIG 0xFFC0D088 /* DMA34 Configuration Register */
2227#define DMA34_X_COUNT 0xFFC0D08C /* DMA34 Inner Loop Count Start Value */
2228#define DMA34_X_MODIFY 0xFFC0D090 /* DMA34 Inner Loop Address Increment */
2229#define DMA34_Y_COUNT 0xFFC0D094 /* DMA34 Outer Loop Count Start Value (2D only) */
2230#define DMA34_Y_MODIFY 0xFFC0D098 /* DMA34 Outer Loop Address Increment (2D only) */
2231#define DMA34_CURR_DESC_PTR 0xFFC0D0A4 /* DMA34 Current Descriptor Pointer */
2232#define DMA34_PREV_DESC_PTR 0xFFC0D0A8 /* DMA34 Previous Initial Descriptor Pointer */
2233#define DMA34_CURR_ADDR 0xFFC0D0AC /* DMA34 Current Address */
2234#define DMA34_IRQ_STATUS 0xFFC0D0B0 /* DMA34 Status Register */
2235#define DMA34_CURR_X_COUNT 0xFFC0D0B4 /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
2236#define DMA34_CURR_Y_COUNT 0xFFC0D0B8 /* DMA34 Current Row Count (2D only) */
2237#define DMA34_BWL_COUNT 0xFFC0D0C0 /* DMA34 Bandwidth Limit Count */
2238#define DMA34_CURR_BWL_COUNT 0xFFC0D0C4 /* DMA34 Bandwidth Limit Count Current */
2239#define DMA34_BWM_COUNT 0xFFC0D0C8 /* DMA34 Bandwidth Monitor Count */
2240#define DMA34_CURR_BWM_COUNT 0xFFC0D0CC /* DMA34 Bandwidth Monitor Count Current */
2241
2242/* =========================
2243 DMA35
2244 ========================= */
2245#define DMA35_NEXT_DESC_PTR 0xFFC10000 /* DMA35 Pointer to Next Initial Descriptor */
2246#define DMA35_START_ADDR 0xFFC10004 /* DMA35 Start Address of Current Buffer */
2247#define DMA35_CONFIG 0xFFC10008 /* DMA35 Configuration Register */
2248#define DMA35_X_COUNT 0xFFC1000C /* DMA35 Inner Loop Count Start Value */
2249#define DMA35_X_MODIFY 0xFFC10010 /* DMA35 Inner Loop Address Increment */
2250#define DMA35_Y_COUNT 0xFFC10014 /* DMA35 Outer Loop Count Start Value (2D only) */
2251#define DMA35_Y_MODIFY 0xFFC10018 /* DMA35 Outer Loop Address Increment (2D only) */
2252#define DMA35_CURR_DESC_PTR 0xFFC10024 /* DMA35 Current Descriptor Pointer */
2253#define DMA35_PREV_DESC_PTR 0xFFC10028 /* DMA35 Previous Initial Descriptor Pointer */
2254#define DMA35_CURR_ADDR 0xFFC1002C /* DMA35 Current Address */
2255#define DMA35_IRQ_STATUS 0xFFC10030 /* DMA35 Status Register */
2256#define DMA35_CURR_X_COUNT 0xFFC10034 /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
2257#define DMA35_CURR_Y_COUNT 0xFFC10038 /* DMA35 Current Row Count (2D only) */
2258#define DMA35_BWL_COUNT 0xFFC10040 /* DMA35 Bandwidth Limit Count */
2259#define DMA35_CURR_BWL_COUNT 0xFFC10044 /* DMA35 Bandwidth Limit Count Current */
2260#define DMA35_BWM_COUNT 0xFFC10048 /* DMA35 Bandwidth Monitor Count */
2261#define DMA35_CURR_BWM_COUNT 0xFFC1004C /* DMA35 Bandwidth Monitor Count Current */
2262
2263/* =========================
2264 DMA36
2265 ========================= */
2266#define DMA36_NEXT_DESC_PTR 0xFFC10080 /* DMA36 Pointer to Next Initial Descriptor */
2267#define DMA36_START_ADDR 0xFFC10084 /* DMA36 Start Address of Current Buffer */
2268#define DMA36_CONFIG 0xFFC10088 /* DMA36 Configuration Register */
2269#define DMA36_X_COUNT 0xFFC1008C /* DMA36 Inner Loop Count Start Value */
2270#define DMA36_X_MODIFY 0xFFC10090 /* DMA36 Inner Loop Address Increment */
2271#define DMA36_Y_COUNT 0xFFC10094 /* DMA36 Outer Loop Count Start Value (2D only) */
2272#define DMA36_Y_MODIFY 0xFFC10098 /* DMA36 Outer Loop Address Increment (2D only) */
2273#define DMA36_CURR_DESC_PTR 0xFFC100A4 /* DMA36 Current Descriptor Pointer */
2274#define DMA36_PREV_DESC_PTR 0xFFC100A8 /* DMA36 Previous Initial Descriptor Pointer */
2275#define DMA36_CURR_ADDR 0xFFC100AC /* DMA36 Current Address */
2276#define DMA36_IRQ_STATUS 0xFFC100B0 /* DMA36 Status Register */
2277#define DMA36_CURR_X_COUNT 0xFFC100B4 /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
2278#define DMA36_CURR_Y_COUNT 0xFFC100B8 /* DMA36 Current Row Count (2D only) */
2279#define DMA36_BWL_COUNT 0xFFC100C0 /* DMA36 Bandwidth Limit Count */
2280#define DMA36_CURR_BWL_COUNT 0xFFC100C4 /* DMA36 Bandwidth Limit Count Current */
2281#define DMA36_BWM_COUNT 0xFFC100C8 /* DMA36 Bandwidth Monitor Count */
2282#define DMA36_CURR_BWM_COUNT 0xFFC100CC /* DMA36 Bandwidth Monitor Count Current */
2283
2284/* =========================
2285 DMA37
2286 ========================= */
2287#define DMA37_NEXT_DESC_PTR 0xFFC10100 /* DMA37 Pointer to Next Initial Descriptor */
2288#define DMA37_START_ADDR 0xFFC10104 /* DMA37 Start Address of Current Buffer */
2289#define DMA37_CONFIG 0xFFC10108 /* DMA37 Configuration Register */
2290#define DMA37_X_COUNT 0xFFC1010C /* DMA37 Inner Loop Count Start Value */
2291#define DMA37_X_MODIFY 0xFFC10110 /* DMA37 Inner Loop Address Increment */
2292#define DMA37_Y_COUNT 0xFFC10114 /* DMA37 Outer Loop Count Start Value (2D only) */
2293#define DMA37_Y_MODIFY 0xFFC10118 /* DMA37 Outer Loop Address Increment (2D only) */
2294#define DMA37_CURR_DESC_PTR 0xFFC10124 /* DMA37 Current Descriptor Pointer */
2295#define DMA37_PREV_DESC_PTR 0xFFC10128 /* DMA37 Previous Initial Descriptor Pointer */
2296#define DMA37_CURR_ADDR 0xFFC1012C /* DMA37 Current Address */
2297#define DMA37_IRQ_STATUS 0xFFC10130 /* DMA37 Status Register */
2298#define DMA37_CURR_X_COUNT 0xFFC10134 /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
2299#define DMA37_CURR_Y_COUNT 0xFFC10138 /* DMA37 Current Row Count (2D only) */
2300#define DMA37_BWL_COUNT 0xFFC10140 /* DMA37 Bandwidth Limit Count */
2301#define DMA37_CURR_BWL_COUNT 0xFFC10144 /* DMA37 Bandwidth Limit Count Current */
2302#define DMA37_BWM_COUNT 0xFFC10148 /* DMA37 Bandwidth Monitor Count */
2303#define DMA37_CURR_BWM_COUNT 0xFFC1014C /* DMA37 Bandwidth Monitor Count Current */
2304
2305/* =========================
2306 DMA38
2307 ========================= */
2308#define DMA38_NEXT_DESC_PTR 0xFFC12000 /* DMA38 Pointer to Next Initial Descriptor */
2309#define DMA38_START_ADDR 0xFFC12004 /* DMA38 Start Address of Current Buffer */
2310#define DMA38_CONFIG 0xFFC12008 /* DMA38 Configuration Register */
2311#define DMA38_X_COUNT 0xFFC1200C /* DMA38 Inner Loop Count Start Value */
2312#define DMA38_X_MODIFY 0xFFC12010 /* DMA38 Inner Loop Address Increment */
2313#define DMA38_Y_COUNT 0xFFC12014 /* DMA38 Outer Loop Count Start Value (2D only) */
2314#define DMA38_Y_MODIFY 0xFFC12018 /* DMA38 Outer Loop Address Increment (2D only) */
2315#define DMA38_CURR_DESC_PTR 0xFFC12024 /* DMA38 Current Descriptor Pointer */
2316#define DMA38_PREV_DESC_PTR 0xFFC12028 /* DMA38 Previous Initial Descriptor Pointer */
2317#define DMA38_CURR_ADDR 0xFFC1202C /* DMA38 Current Address */
2318#define DMA38_IRQ_STATUS 0xFFC12030 /* DMA38 Status Register */
2319#define DMA38_CURR_X_COUNT 0xFFC12034 /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
2320#define DMA38_CURR_Y_COUNT 0xFFC12038 /* DMA38 Current Row Count (2D only) */
2321#define DMA38_BWL_COUNT 0xFFC12040 /* DMA38 Bandwidth Limit Count */
2322#define DMA38_CURR_BWL_COUNT 0xFFC12044 /* DMA38 Bandwidth Limit Count Current */
2323#define DMA38_BWM_COUNT 0xFFC12048 /* DMA38 Bandwidth Monitor Count */
2324#define DMA38_CURR_BWM_COUNT 0xFFC1204C /* DMA38 Bandwidth Monitor Count Current */
2325
2326/* =========================
2327 DMA39
2328 ========================= */
2329#define DMA39_NEXT_DESC_PTR 0xFFC12080 /* DMA39 Pointer to Next Initial Descriptor */
2330#define DMA39_START_ADDR 0xFFC12084 /* DMA39 Start Address of Current Buffer */
2331#define DMA39_CONFIG 0xFFC12088 /* DMA39 Configuration Register */
2332#define DMA39_X_COUNT 0xFFC1208C /* DMA39 Inner Loop Count Start Value */
2333#define DMA39_X_MODIFY 0xFFC12090 /* DMA39 Inner Loop Address Increment */
2334#define DMA39_Y_COUNT 0xFFC12094 /* DMA39 Outer Loop Count Start Value (2D only) */
2335#define DMA39_Y_MODIFY 0xFFC12098 /* DMA39 Outer Loop Address Increment (2D only) */
2336#define DMA39_CURR_DESC_PTR 0xFFC120A4 /* DMA39 Current Descriptor Pointer */
2337#define DMA39_PREV_DESC_PTR 0xFFC120A8 /* DMA39 Previous Initial Descriptor Pointer */
2338#define DMA39_CURR_ADDR 0xFFC120AC /* DMA39 Current Address */
2339#define DMA39_IRQ_STATUS 0xFFC120B0 /* DMA39 Status Register */
2340#define DMA39_CURR_X_COUNT 0xFFC120B4 /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
2341#define DMA39_CURR_Y_COUNT 0xFFC120B8 /* DMA39 Current Row Count (2D only) */
2342#define DMA39_BWL_COUNT 0xFFC120C0 /* DMA39 Bandwidth Limit Count */
2343#define DMA39_CURR_BWL_COUNT 0xFFC120C4 /* DMA39 Bandwidth Limit Count Current */
2344#define DMA39_BWM_COUNT 0xFFC120C8 /* DMA39 Bandwidth Monitor Count */
2345#define DMA39_CURR_BWM_COUNT 0xFFC120CC /* DMA39 Bandwidth Monitor Count Current */
2346
2347/* =========================
2348 DMA40
2349 ========================= */
2350#define DMA40_NEXT_DESC_PTR 0xFFC12100 /* DMA40 Pointer to Next Initial Descriptor */
2351#define DMA40_START_ADDR 0xFFC12104 /* DMA40 Start Address of Current Buffer */
2352#define DMA40_CONFIG 0xFFC12108 /* DMA40 Configuration Register */
2353#define DMA40_X_COUNT 0xFFC1210C /* DMA40 Inner Loop Count Start Value */
2354#define DMA40_X_MODIFY 0xFFC12110 /* DMA40 Inner Loop Address Increment */
2355#define DMA40_Y_COUNT 0xFFC12114 /* DMA40 Outer Loop Count Start Value (2D only) */
2356#define DMA40_Y_MODIFY 0xFFC12118 /* DMA40 Outer Loop Address Increment (2D only) */
2357#define DMA40_CURR_DESC_PTR 0xFFC12124 /* DMA40 Current Descriptor Pointer */
2358#define DMA40_PREV_DESC_PTR 0xFFC12128 /* DMA40 Previous Initial Descriptor Pointer */
2359#define DMA40_CURR_ADDR 0xFFC1212C /* DMA40 Current Address */
2360#define DMA40_IRQ_STATUS 0xFFC12130 /* DMA40 Status Register */
2361#define DMA40_CURR_X_COUNT 0xFFC12134 /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
2362#define DMA40_CURR_Y_COUNT 0xFFC12138 /* DMA40 Current Row Count (2D only) */
2363#define DMA40_BWL_COUNT 0xFFC12140 /* DMA40 Bandwidth Limit Count */
2364#define DMA40_CURR_BWL_COUNT 0xFFC12144 /* DMA40 Bandwidth Limit Count Current */
2365#define DMA40_BWM_COUNT 0xFFC12148 /* DMA40 Bandwidth Monitor Count */
2366#define DMA40_CURR_BWM_COUNT 0xFFC1214C /* DMA40 Bandwidth Monitor Count Current */
2367
2368/* =========================
2369 DMA41
2370 ========================= */
2371#define DMA41_NEXT_DESC_PTR 0xFFC12180 /* DMA41 Pointer to Next Initial Descriptor */
2372#define DMA41_START_ADDR 0xFFC12184 /* DMA41 Start Address of Current Buffer */
2373#define DMA41_CONFIG 0xFFC12188 /* DMA41 Configuration Register */
2374#define DMA41_X_COUNT 0xFFC1218C /* DMA41 Inner Loop Count Start Value */
2375#define DMA41_X_MODIFY 0xFFC12190 /* DMA41 Inner Loop Address Increment */
2376#define DMA41_Y_COUNT 0xFFC12194 /* DMA41 Outer Loop Count Start Value (2D only) */
2377#define DMA41_Y_MODIFY 0xFFC12198 /* DMA41 Outer Loop Address Increment (2D only) */
2378#define DMA41_CURR_DESC_PTR 0xFFC121A4 /* DMA41 Current Descriptor Pointer */
2379#define DMA41_PREV_DESC_PTR 0xFFC121A8 /* DMA41 Previous Initial Descriptor Pointer */
2380#define DMA41_CURR_ADDR 0xFFC121AC /* DMA41 Current Address */
2381#define DMA41_IRQ_STATUS 0xFFC121B0 /* DMA41 Status Register */
2382#define DMA41_CURR_X_COUNT 0xFFC121B4 /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
2383#define DMA41_CURR_Y_COUNT 0xFFC121B8 /* DMA41 Current Row Count (2D only) */
2384#define DMA41_BWL_COUNT 0xFFC121C0 /* DMA41 Bandwidth Limit Count */
2385#define DMA41_CURR_BWL_COUNT 0xFFC121C4 /* DMA41 Bandwidth Limit Count Current */
2386#define DMA41_BWM_COUNT 0xFFC121C8 /* DMA41 Bandwidth Monitor Count */
2387#define DMA41_CURR_BWM_COUNT 0xFFC121CC /* DMA41 Bandwidth Monitor Count Current */
2388
2389/* =========================
2390 DMA42
2391 ========================= */
2392#define DMA42_NEXT_DESC_PTR 0xFFC14000 /* DMA42 Pointer to Next Initial Descriptor */
2393#define DMA42_START_ADDR 0xFFC14004 /* DMA42 Start Address of Current Buffer */
2394#define DMA42_CONFIG 0xFFC14008 /* DMA42 Configuration Register */
2395#define DMA42_X_COUNT 0xFFC1400C /* DMA42 Inner Loop Count Start Value */
2396#define DMA42_X_MODIFY 0xFFC14010 /* DMA42 Inner Loop Address Increment */
2397#define DMA42_Y_COUNT 0xFFC14014 /* DMA42 Outer Loop Count Start Value (2D only) */
2398#define DMA42_Y_MODIFY 0xFFC14018 /* DMA42 Outer Loop Address Increment (2D only) */
2399#define DMA42_CURR_DESC_PTR 0xFFC14024 /* DMA42 Current Descriptor Pointer */
2400#define DMA42_PREV_DESC_PTR 0xFFC14028 /* DMA42 Previous Initial Descriptor Pointer */
2401#define DMA42_CURR_ADDR 0xFFC1402C /* DMA42 Current Address */
2402#define DMA42_IRQ_STATUS 0xFFC14030 /* DMA42 Status Register */
2403#define DMA42_CURR_X_COUNT 0xFFC14034 /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
2404#define DMA42_CURR_Y_COUNT 0xFFC14038 /* DMA42 Current Row Count (2D only) */
2405#define DMA42_BWL_COUNT 0xFFC14040 /* DMA42 Bandwidth Limit Count */
2406#define DMA42_CURR_BWL_COUNT 0xFFC14044 /* DMA42 Bandwidth Limit Count Current */
2407#define DMA42_BWM_COUNT 0xFFC14048 /* DMA42 Bandwidth Monitor Count */
2408#define DMA42_CURR_BWM_COUNT 0xFFC1404C /* DMA42 Bandwidth Monitor Count Current */
2409
2410/* =========================
2411 DMA43
2412 ========================= */
2413#define DMA43_NEXT_DESC_PTR 0xFFC14080 /* DMA43 Pointer to Next Initial Descriptor */
2414#define DMA43_START_ADDR 0xFFC14084 /* DMA43 Start Address of Current Buffer */
2415#define DMA43_CONFIG 0xFFC14088 /* DMA43 Configuration Register */
2416#define DMA43_X_COUNT 0xFFC1408C /* DMA43 Inner Loop Count Start Value */
2417#define DMA43_X_MODIFY 0xFFC14090 /* DMA43 Inner Loop Address Increment */
2418#define DMA43_Y_COUNT 0xFFC14094 /* DMA43 Outer Loop Count Start Value (2D only) */
2419#define DMA43_Y_MODIFY 0xFFC14098 /* DMA43 Outer Loop Address Increment (2D only) */
2420#define DMA43_CURR_DESC_PTR 0xFFC140A4 /* DMA43 Current Descriptor Pointer */
2421#define DMA43_PREV_DESC_PTR 0xFFC140A8 /* DMA43 Previous Initial Descriptor Pointer */
2422#define DMA43_CURR_ADDR 0xFFC140AC /* DMA43 Current Address */
2423#define DMA43_IRQ_STATUS 0xFFC140B0 /* DMA43 Status Register */
2424#define DMA43_CURR_X_COUNT 0xFFC140B4 /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
2425#define DMA43_CURR_Y_COUNT 0xFFC140B8 /* DMA43 Current Row Count (2D only) */
2426#define DMA43_BWL_COUNT 0xFFC140C0 /* DMA43 Bandwidth Limit Count */
2427#define DMA43_CURR_BWL_COUNT 0xFFC140C4 /* DMA43 Bandwidth Limit Count Current */
2428#define DMA43_BWM_COUNT 0xFFC140C8 /* DMA43 Bandwidth Monitor Count */
2429#define DMA43_CURR_BWM_COUNT 0xFFC140CC /* DMA43 Bandwidth Monitor Count Current */
2430
2431/* =========================
2432 DMA44
2433 ========================= */
2434#define DMA44_NEXT_DESC_PTR 0xFFC14100 /* DMA44 Pointer to Next Initial Descriptor */
2435#define DMA44_START_ADDR 0xFFC14104 /* DMA44 Start Address of Current Buffer */
2436#define DMA44_CONFIG 0xFFC14108 /* DMA44 Configuration Register */
2437#define DMA44_X_COUNT 0xFFC1410C /* DMA44 Inner Loop Count Start Value */
2438#define DMA44_X_MODIFY 0xFFC14110 /* DMA44 Inner Loop Address Increment */
2439#define DMA44_Y_COUNT 0xFFC14114 /* DMA44 Outer Loop Count Start Value (2D only) */
2440#define DMA44_Y_MODIFY 0xFFC14118 /* DMA44 Outer Loop Address Increment (2D only) */
2441#define DMA44_CURR_DESC_PTR 0xFFC14124 /* DMA44 Current Descriptor Pointer */
2442#define DMA44_PREV_DESC_PTR 0xFFC14128 /* DMA44 Previous Initial Descriptor Pointer */
2443#define DMA44_CURR_ADDR 0xFFC1412C /* DMA44 Current Address */
2444#define DMA44_IRQ_STATUS 0xFFC14130 /* DMA44 Status Register */
2445#define DMA44_CURR_X_COUNT 0xFFC14134 /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
2446#define DMA44_CURR_Y_COUNT 0xFFC14138 /* DMA44 Current Row Count (2D only) */
2447#define DMA44_BWL_COUNT 0xFFC14140 /* DMA44 Bandwidth Limit Count */
2448#define DMA44_CURR_BWL_COUNT 0xFFC14144 /* DMA44 Bandwidth Limit Count Current */
2449#define DMA44_BWM_COUNT 0xFFC14148 /* DMA44 Bandwidth Monitor Count */
2450#define DMA44_CURR_BWM_COUNT 0xFFC1414C /* DMA44 Bandwidth Monitor Count Current */
2451
2452/* =========================
2453 DMA45
2454 ========================= */
2455#define DMA45_NEXT_DESC_PTR 0xFFC14180 /* DMA45 Pointer to Next Initial Descriptor */
2456#define DMA45_START_ADDR 0xFFC14184 /* DMA45 Start Address of Current Buffer */
2457#define DMA45_CONFIG 0xFFC14188 /* DMA45 Configuration Register */
2458#define DMA45_X_COUNT 0xFFC1418C /* DMA45 Inner Loop Count Start Value */
2459#define DMA45_X_MODIFY 0xFFC14190 /* DMA45 Inner Loop Address Increment */
2460#define DMA45_Y_COUNT 0xFFC14194 /* DMA45 Outer Loop Count Start Value (2D only) */
2461#define DMA45_Y_MODIFY 0xFFC14198 /* DMA45 Outer Loop Address Increment (2D only) */
2462#define DMA45_CURR_DESC_PTR 0xFFC141A4 /* DMA45 Current Descriptor Pointer */
2463#define DMA45_PREV_DESC_PTR 0xFFC141A8 /* DMA45 Previous Initial Descriptor Pointer */
2464#define DMA45_CURR_ADDR 0xFFC141AC /* DMA45 Current Address */
2465#define DMA45_IRQ_STATUS 0xFFC141B0 /* DMA45 Status Register */
2466#define DMA45_CURR_X_COUNT 0xFFC141B4 /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
2467#define DMA45_CURR_Y_COUNT 0xFFC141B8 /* DMA45 Current Row Count (2D only) */
2468#define DMA45_BWL_COUNT 0xFFC141C0 /* DMA45 Bandwidth Limit Count */
2469#define DMA45_CURR_BWL_COUNT 0xFFC141C4 /* DMA45 Bandwidth Limit Count Current */
2470#define DMA45_BWM_COUNT 0xFFC141C8 /* DMA45 Bandwidth Monitor Count */
2471#define DMA45_CURR_BWM_COUNT 0xFFC141CC /* DMA45 Bandwidth Monitor Count Current */
2472
2473/* =========================
2474 DMA46
2475 ========================= */
2476#define DMA46_NEXT_DESC_PTR 0xFFC14200 /* DMA46 Pointer to Next Initial Descriptor */
2477#define DMA46_START_ADDR 0xFFC14204 /* DMA46 Start Address of Current Buffer */
2478#define DMA46_CONFIG 0xFFC14208 /* DMA46 Configuration Register */
2479#define DMA46_X_COUNT 0xFFC1420C /* DMA46 Inner Loop Count Start Value */
2480#define DMA46_X_MODIFY 0xFFC14210 /* DMA46 Inner Loop Address Increment */
2481#define DMA46_Y_COUNT 0xFFC14214 /* DMA46 Outer Loop Count Start Value (2D only) */
2482#define DMA46_Y_MODIFY 0xFFC14218 /* DMA46 Outer Loop Address Increment (2D only) */
2483#define DMA46_CURR_DESC_PTR 0xFFC14224 /* DMA46 Current Descriptor Pointer */
2484#define DMA46_PREV_DESC_PTR 0xFFC14228 /* DMA46 Previous Initial Descriptor Pointer */
2485#define DMA46_CURR_ADDR 0xFFC1422C /* DMA46 Current Address */
2486#define DMA46_IRQ_STATUS 0xFFC14230 /* DMA46 Status Register */
2487#define DMA46_CURR_X_COUNT 0xFFC14234 /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
2488#define DMA46_CURR_Y_COUNT 0xFFC14238 /* DMA46 Current Row Count (2D only) */
2489#define DMA46_BWL_COUNT 0xFFC14240 /* DMA46 Bandwidth Limit Count */
2490#define DMA46_CURR_BWL_COUNT 0xFFC14244 /* DMA46 Bandwidth Limit Count Current */
2491#define DMA46_BWM_COUNT 0xFFC14248 /* DMA46 Bandwidth Monitor Count */
2492#define DMA46_CURR_BWM_COUNT 0xFFC1424C /* DMA46 Bandwidth Monitor Count Current */
2493
2494
2495/********************************************************************************
2496 DMA Alias Definitions
2497 ********************************************************************************/
2498#define MDMA0_DEST_CRC0_NEXT_DESC_PTR (DMA22_NEXT_DESC_PTR)
2499#define MDMA0_DEST_CRC0_START_ADDR (DMA22_START_ADDR)
2500#define MDMA0_DEST_CRC0_CONFIG (DMA22_CONFIG)
2501#define MDMA0_DEST_CRC0_X_COUNT (DMA22_X_COUNT)
2502#define MDMA0_DEST_CRC0_X_MODIFY (DMA22_X_MODIFY)
2503#define MDMA0_DEST_CRC0_Y_COUNT (DMA22_Y_COUNT)
2504#define MDMA0_DEST_CRC0_Y_MODIFY (DMA22_Y_MODIFY)
2505#define MDMA0_DEST_CRC0_CURR_DESC_PTR (DMA22_CURR_DESC_PTR)
2506#define MDMA0_DEST_CRC0_PREV_DESC_PTR (DMA22_PREV_DESC_PTR)
2507#define MDMA0_DEST_CRC0_CURR_ADDR (DMA22_CURR_ADDR)
2508#define MDMA0_DEST_CRC0_IRQ_STATUS (DMA22_IRQ_STATUS)
2509#define MDMA0_DEST_CRC0_CURR_X_COUNT (DMA22_CURR_X_COUNT)
2510#define MDMA0_DEST_CRC0_CURR_Y_COUNT (DMA22_CURR_Y_COUNT)
2511#define MDMA0_DEST_CRC0_BWL_COUNT (DMA22_BWL_COUNT)
2512#define MDMA0_DEST_CRC0_CURR_BWL_COUNT (DMA22_CURR_BWL_COUNT)
2513#define MDMA0_DEST_CRC0_BWM_COUNT (DMA22_BWM_COUNT)
2514#define MDMA0_DEST_CRC0_CURR_BWM_COUNT (DMA22_CURR_BWM_COUNT)
2515#define MDMA0_SRC_CRC0_NEXT_DESC_PTR (DMA21_NEXT_DESC_PTR)
2516#define MDMA0_SRC_CRC0_START_ADDR (DMA21_START_ADDR)
2517#define MDMA0_SRC_CRC0_CONFIG (DMA21_CONFIG)
2518#define MDMA0_SRC_CRC0_X_COUNT (DMA21_X_COUNT)
2519#define MDMA0_SRC_CRC0_X_MODIFY (DMA21_X_MODIFY)
2520#define MDMA0_SRC_CRC0_Y_COUNT (DMA21_Y_COUNT)
2521#define MDMA0_SRC_CRC0_Y_MODIFY (DMA21_Y_MODIFY)
2522#define MDMA0_SRC_CRC0_CURR_DESC_PTR (DMA21_CURR_DESC_PTR)
2523#define MDMA0_SRC_CRC0_PREV_DESC_PTR (DMA21_PREV_DESC_PTR)
2524#define MDMA0_SRC_CRC0_CURR_ADDR (DMA21_CURR_ADDR)
2525#define MDMA0_SRC_CRC0_IRQ_STATUS (DMA21_IRQ_STATUS)
2526#define MDMA0_SRC_CRC0_CURR_X_COUNT (DMA21_CURR_X_COUNT)
2527#define MDMA0_SRC_CRC0_CURR_Y_COUNT (DMA21_CURR_Y_COUNT)
2528#define MDMA0_SRC_CRC0_BWL_COUNT (DMA21_BWL_COUNT)
2529#define MDMA0_SRC_CRC0_CURR_BWL_COUNT (DMA21_CURR_BWL_COUNT)
2530#define MDMA0_SRC_CRC0_BWM_COUNT (DMA21_BWM_COUNT)
2531#define MDMA0_SRC_CRC0_CURR_BWM_COUNT (DMA21_CURR_BWM_COUNT)
2532#define MDMA1_DEST_CRC1_NEXT_DESC_PTR (DMA24_NEXT_DESC_PTR)
2533#define MDMA1_DEST_CRC1_START_ADDR (DMA24_START_ADDR)
2534#define MDMA1_DEST_CRC1_CONFIG (DMA24_CONFIG)
2535#define MDMA1_DEST_CRC1_X_COUNT (DMA24_X_COUNT)
2536#define MDMA1_DEST_CRC1_X_MODIFY (DMA24_X_MODIFY)
2537#define MDMA1_DEST_CRC1_Y_COUNT (DMA24_Y_COUNT)
2538#define MDMA1_DEST_CRC1_Y_MODIFY (DMA24_Y_MODIFY)
2539#define MDMA1_DEST_CRC1_CURR_DESC_PTR (DMA24_CURR_DESC_PTR)
2540#define MDMA1_DEST_CRC1_PREV_DESC_PTR (DMA24_PREV_DESC_PTR)
2541#define MDMA1_DEST_CRC1_CURR_ADDR (DMA24_CURR_ADDR)
2542#define MDMA1_DEST_CRC1_IRQ_STATUS (DMA24_IRQ_STATUS)
2543#define MDMA1_DEST_CRC1_CURR_X_COUNT (DMA24_CURR_X_COUNT)
2544#define MDMA1_DEST_CRC1_CURR_Y_COUNT (DMA24_CURR_Y_COUNT)
2545#define MDMA1_DEST_CRC1_BWL_COUNT (DMA24_BWL_COUNT)
2546#define MDMA1_DEST_CRC1_CURR_BWL_COUNT (DMA24_CURR_BWL_COUNT)
2547#define MDMA1_DEST_CRC1_BWM_COUNT (DMA24_BWM_COUNT)
2548#define MDMA1_DEST_CRC1_CURR_BWM_COUNT (DMA24_CURR_BWM_COUNT)
2549#define MDMA1_SRC_CRC1_NEXT_DESC_PTR (DMA23_NEXT_DESC_PTR)
2550#define MDMA1_SRC_CRC1_START_ADDR (DMA23_START_ADDR)
2551#define MDMA1_SRC_CRC1_CONFIG (DMA23_CONFIG)
2552#define MDMA1_SRC_CRC1_X_COUNT (DMA23_X_COUNT)
2553#define MDMA1_SRC_CRC1_X_MODIFY (DMA23_X_MODIFY)
2554#define MDMA1_SRC_CRC1_Y_COUNT (DMA23_Y_COUNT)
2555#define MDMA1_SRC_CRC1_Y_MODIFY (DMA23_Y_MODIFY)
2556#define MDMA1_SRC_CRC1_CURR_DESC_PTR (DMA23_CURR_DESC_PTR)
2557#define MDMA1_SRC_CRC1_PREV_DESC_PTR (DMA23_PREV_DESC_PTR)
2558#define MDMA1_SRC_CRC1_CURR_ADDR (DMA23_CURR_ADDR)
2559#define MDMA1_SRC_CRC1_IRQ_STATUS (DMA23_IRQ_STATUS)
2560#define MDMA1_SRC_CRC1_CURR_X_COUNT (DMA23_CURR_X_COUNT)
2561#define MDMA1_SRC_CRC1_CURR_Y_COUNT (DMA23_CURR_Y_COUNT)
2562#define MDMA1_SRC_CRC1_BWL_COUNT (DMA23_BWL_COUNT)
2563#define MDMA1_SRC_CRC1_CURR_BWL_COUNT (DMA23_CURR_BWL_COUNT)
2564#define MDMA1_SRC_CRC1_BWM_COUNT (DMA23_BWM_COUNT)
2565#define MDMA1_SRC_CRC1_CURR_BWM_COUNT (DMA23_CURR_BWM_COUNT)
2566#define MDMA2_DEST_NEXT_DESC_PTR (DMA26_NEXT_DESC_PTR)
2567#define MDMA2_DEST_START_ADDR (DMA26_START_ADDR)
2568#define MDMA2_DEST_CONFIG (DMA26_CONFIG)
2569#define MDMA2_DEST_X_COUNT (DMA26_X_COUNT)
2570#define MDMA2_DEST_X_MODIFY (DMA26_X_MODIFY)
2571#define MDMA2_DEST_Y_COUNT (DMA26_Y_COUNT)
2572#define MDMA2_DEST_Y_MODIFY (DMA26_Y_MODIFY)
2573#define MDMA2_DEST_CURR_DESC_PTR (DMA26_CURR_DESC_PTR)
2574#define MDMA2_DEST_PREV_DESC_PTR (DMA26_PREV_DESC_PTR)
2575#define MDMA2_DEST_CURR_ADDR (DMA26_CURR_ADDR)
2576#define MDMA2_DEST_IRQ_STATUS (DMA26_IRQ_STATUS)
2577#define MDMA2_DEST_CURR_X_COUNT (DMA26_CURR_X_COUNT)
2578#define MDMA2_DEST_CURR_Y_COUNT (DMA26_CURR_Y_COUNT)
2579#define MDMA2_DEST_BWL_COUNT (DMA26_BWL_COUNT)
2580#define MDMA2_DEST_CURR_BWL_COUNT (DMA26_CURR_BWL_COUNT)
2581#define MDMA2_DEST_BWM_COUNT (DMA26_BWM_COUNT)
2582#define MDMA2_DEST_CURR_BWM_COUNT (DMA26_CURR_BWM_COUNT)
2583#define MDMA2_SRC_NEXT_DESC_PTR (DMA25_NEXT_DESC_PTR)
2584#define MDMA2_SRC_START_ADDR (DMA25_START_ADDR)
2585#define MDMA2_SRC_CONFIG (DMA25_CONFIG)
2586#define MDMA2_SRC_X_COUNT (DMA25_X_COUNT)
2587#define MDMA2_SRC_X_MODIFY (DMA25_X_MODIFY)
2588#define MDMA2_SRC_Y_COUNT (DMA25_Y_COUNT)
2589#define MDMA2_SRC_Y_MODIFY (DMA25_Y_MODIFY)
2590#define MDMA2_SRC_CURR_DESC_PTR (DMA25_CURR_DESC_PTR)
2591#define MDMA2_SRC_PREV_DESC_PTR (DMA25_PREV_DESC_PTR)
2592#define MDMA2_SRC_CURR_ADDR (DMA25_CURR_ADDR)
2593#define MDMA2_SRC_IRQ_STATUS (DMA25_IRQ_STATUS)
2594#define MDMA2_SRC_CURR_X_COUNT (DMA25_CURR_X_COUNT)
2595#define MDMA2_SRC_CURR_Y_COUNT (DMA25_CURR_Y_COUNT)
2596#define MDMA2_SRC_BWL_COUNT (DMA25_BWL_COUNT)
2597#define MDMA2_SRC_CURR_BWL_COUNT (DMA25_CURR_BWL_COUNT)
2598#define MDMA2_SRC_BWM_COUNT (DMA25_BWM_COUNT)
2599#define MDMA2_SRC_CURR_BWM_COUNT (DMA25_CURR_BWM_COUNT)
2600#define MDMA3_DEST_NEXT_DESC_PTR (DMA28_NEXT_DESC_PTR)
2601#define MDMA3_DEST_START_ADDR (DMA28_START_ADDR)
2602#define MDMA3_DEST_CONFIG (DMA28_CONFIG)
2603#define MDMA3_DEST_X_COUNT (DMA28_X_COUNT)
2604#define MDMA3_DEST_X_MODIFY (DMA28_X_MODIFY)
2605#define MDMA3_DEST_Y_COUNT (DMA28_Y_COUNT)
2606#define MDMA3_DEST_Y_MODIFY (DMA28_Y_MODIFY)
2607#define MDMA3_DEST_CURR_DESC_PTR (DMA28_CURR_DESC_PTR)
2608#define MDMA3_DEST_PREV_DESC_PTR (DMA28_PREV_DESC_PTR)
2609#define MDMA3_DEST_CURR_ADDR (DMA28_CURR_ADDR)
2610#define MDMA3_DEST_IRQ_STATUS (DMA28_IRQ_STATUS)
2611#define MDMA3_DEST_CURR_X_COUNT (DMA28_CURR_X_COUNT)
2612#define MDMA3_DEST_CURR_Y_COUNT (DMA28_CURR_Y_COUNT)
2613#define MDMA3_DEST_BWL_COUNT (DMA28_BWL_COUNT)
2614#define MDMA3_DEST_CURR_BWL_COUNT (DMA28_CURR_BWL_COUNT)
2615#define MDMA3_DEST_BWM_COUNT (DMA28_BWM_COUNT)
2616#define MDMA3_DEST_CURR_BWM_COUNT (DMA28_CURR_BWM_COUNT)
2617#define MDMA3_SRC_NEXT_DESC_PTR (DMA27_NEXT_DESC_PTR)
2618#define MDMA3_SRC_START_ADDR (DMA27_START_ADDR)
2619#define MDMA3_SRC_CONFIG (DMA27_CONFIG)
2620#define MDMA3_SRC_X_COUNT (DMA27_X_COUNT)
2621#define MDMA3_SRC_X_MODIFY (DMA27_X_MODIFY)
2622#define MDMA3_SRC_Y_COUNT (DMA27_Y_COUNT)
2623#define MDMA3_SRC_Y_MODIFY (DMA27_Y_MODIFY)
2624#define MDMA3_SRC_CURR_DESC_PTR (DMA27_CURR_DESC_PTR)
2625#define MDMA3_SRC_PREV_DESC_PTR (DMA27_PREV_DESC_PTR)
2626#define MDMA3_SRC_CURR_ADDR (DMA27_CURR_ADDR)
2627#define MDMA3_SRC_IRQ_STATUS (DMA27_IRQ_STATUS)
2628#define MDMA3_SRC_CURR_X_COUNT (DMA27_CURR_X_COUNT)
2629#define MDMA3_SRC_CURR_Y_COUNT (DMA27_CURR_Y_COUNT)
2630#define MDMA3_SRC_BWL_COUNT (DMA27_BWL_COUNT)
2631#define MDMA3_SRC_CURR_BWL_COUNT (DMA27_CURR_BWL_COUNT)
2632#define MDMA3_SRC_BWM_COUNT (DMA27_BWM_COUNT)
2633#define MDMA3_SRC_CURR_BWM_COUNT (DMA27_CURR_BWM_COUNT)
2634
2635
2636/* =========================
2637 DDR Registers
2638 ========================= */
2639
2640/* =========================
2641 DDR0
2642 ========================= */
2643#define DDR0_ID 0xFFC80000 /* DDR0 Identification Register */
2644#define DDR0_CTL 0xFFC80004 /* DDR0 Control Register */
2645#define DDR0_STAT 0xFFC80008 /* DDR0 Status Register */
2646#define DDR0_EFFCTL 0xFFC8000C /* DDR0 Efficiency Controller */
2647#define DDR0_PRIO 0xFFC80010 /* DDR0 Priority ID Register */
2648#define DDR0_PRIOMSK 0xFFC80014 /* DDR0 Priority ID Mask */
2649#define DDR0_CFG 0xFFC80040 /* DDR0 SDRAM Configuration */
2650#define DDR0_TR0 0xFFC80044 /* DDR0 Timing Register 0 */
2651#define DDR0_TR1 0xFFC80048 /* DDR0 Timing Register 1 */
2652#define DDR0_TR2 0xFFC8004C /* DDR0 Timing Register 2 */
2653#define DDR0_MSK 0xFFC8005C /* DDR0 Mode Register Mask */
2654#define DDR0_MR 0xFFC80060 /* DDR0 Mode Shadow register */
2655#define DDR0_EMR1 0xFFC80064 /* DDR0 EMR1 Shadow Register */
2656#define DDR0_EMR2 0xFFC80068 /* DDR0 EMR2 Shadow Register */
2657#define DDR0_EMR3 0xFFC8006C /* DDR0 EMR3 Shadow Register */
2658#define DDR0_DLLCTL 0xFFC80080 /* DDR0 DLL Control Register */
2659#define DDR0_PADCTL 0xFFC800C0 /* DDR0 PAD Control Register 0 */
2660
2661#define DEVSZ_64 0x000 /* DDR External Bank Size = 64Mbit */
2662#define DEVSZ_128 0x100 /* DDR External Bank Size = 128Mbit */
2663#define DEVSZ_256 0x200 /* DDR External Bank Size = 256Mbit */
2664#define DEVSZ_512 0x300 /* DDR External Bank Size = 512Mbit */
2665#define DEVSZ_1G 0x400 /* DDR External Bank Size = 1Gbit */
2666#define DEVSZ_2G 0x500 /* DDR External Bank Size = 2Gbit */
2667
2668
2669/* =========================
2670 L2CTL Registers
2671 ========================= */
2672
2673/* =========================
2674 L2CTL0
2675 ========================= */
2676#define L2CTL0_CTL 0xFFCA3000 /* L2CTL0 L2 Control Register */
2677#define L2CTL0_ACTL_C0 0xFFCA3004 /* L2CTL0 L2 Core 0 Access Control Register */
2678#define L2CTL0_ACTL_C1 0xFFCA3008 /* L2CTL0 L2 Core 1 Access Control Register */
2679#define L2CTL0_ACTL_SYS 0xFFCA300C /* L2CTL0 L2 System Access Control Register */
2680#define L2CTL0_STAT 0xFFCA3010 /* L2CTL0 L2 Status Register */
2681#define L2CTL0_RPCR 0xFFCA3014 /* L2CTL0 L2 Read Priority Count Register */
2682#define L2CTL0_WPCR 0xFFCA3018 /* L2CTL0 L2 Write Priority Count Register */
2683#define L2CTL0_RFA 0xFFCA3024 /* L2CTL0 L2 Refresh Address Regsiter */
2684#define L2CTL0_ERRADDR0 0xFFCA3040 /* L2CTL0 L2 Bank 0 ECC Error Address Register */
2685#define L2CTL0_ERRADDR1 0xFFCA3044 /* L2CTL0 L2 Bank 1 ECC Error Address Register */
2686#define L2CTL0_ERRADDR2 0xFFCA3048 /* L2CTL0 L2 Bank 2 ECC Error Address Register */
2687#define L2CTL0_ERRADDR3 0xFFCA304C /* L2CTL0 L2 Bank 3 ECC Error Address Register */
2688#define L2CTL0_ERRADDR4 0xFFCA3050 /* L2CTL0 L2 Bank 4 ECC Error Address Register */
2689#define L2CTL0_ERRADDR5 0xFFCA3054 /* L2CTL0 L2 Bank 5 ECC Error Address Register */
2690#define L2CTL0_ERRADDR6 0xFFCA3058 /* L2CTL0 L2 Bank 6 ECC Error Address Register */
2691#define L2CTL0_ERRADDR7 0xFFCA305C /* L2CTL0 L2 Bank 7 ECC Error Address Register */
2692#define L2CTL0_ET0 0xFFCA3080 /* L2CTL0 L2 AXI Error 0 Type Register */
2693#define L2CTL0_EADDR0 0xFFCA3084 /* L2CTL0 L2 AXI Error 0 Address Register */
2694#define L2CTL0_ET1 0xFFCA3088 /* L2CTL0 L2 AXI Error 1 Type Register */
2695#define L2CTL0_EADDR1 0xFFCA308C /* L2CTL0 L2 AXI Error 1 Address Register */
2696
2697
2698/* =========================
2699 SEC Registers
2700 ========================= */
2701/* ------------------------------------------------------------------------------------------------------------------------
2702 SEC Core Interface (SCI) Register Definitions
2703 ------------------------------------------------------------------------------------------------------------------------ */
2704
2705#define SEC_SCI_BASE 0xFFCA4400
2706#define SEC_SCI_OFF 0x40
2707#define SEC_CCTL 0x0 /* SEC Core Control Register n */
2708#define SEC_CSTAT 0x4 /* SEC Core Status Register n */
2709#define SEC_CPND 0x8 /* SEC Core Pending IRQ Register n */
2710#define SEC_CACT 0xC /* SEC Core Active IRQ Register n */
2711#define SEC_CPMSK 0x10 /* SEC Core IRQ Priority Mask Register n */
2712#define SEC_CGMSK 0x14 /* SEC Core IRQ Group Mask Register n */
2713#define SEC_CPLVL 0x18 /* SEC Core IRQ Priority Level Register n */
2714#define SEC_CSID 0x1C /* SEC Core IRQ Source ID Register n */
2715
2716#define bfin_read_SEC_SCI(n, reg) bfin_read32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg)
2717#define bfin_write_SEC_SCI(n, reg, val) \
2718 bfin_write32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg, val)
2719
2720/* ------------------------------------------------------------------------------------------------------------------------
2721 SEC Fault Management Interface (SFI) Register Definitions
2722 ------------------------------------------------------------------------------------------------------------------------ */
2723#define SEC_FCTL 0xFFCA4010 /* SEC Fault Control Register */
2724#define SEC_FSTAT 0xFFCA4014 /* SEC Fault Status Register */
2725#define SEC_FSID 0xFFCA4018 /* SEC Fault Source ID Register */
2726#define SEC_FEND 0xFFCA401C /* SEC Fault End Register */
2727#define SEC_FDLY 0xFFCA4020 /* SEC Fault Delay Register */
2728#define SEC_FDLY_CUR 0xFFCA4024 /* SEC Fault Delay Current Register */
2729#define SEC_FSRDLY 0xFFCA4028 /* SEC Fault System Reset Delay Register */
2730#define SEC_FSRDLY_CUR 0xFFCA402C /* SEC Fault System Reset Delay Current Register */
2731#define SEC_FCOPP 0xFFCA4030 /* SEC Fault COP Period Register */
2732#define SEC_FCOPP_CUR 0xFFCA4034 /* SEC Fault COP Period Current Register */
2733
2734/* ------------------------------------------------------------------------------------------------------------------------
2735 SEC Global Register Definitions
2736 ------------------------------------------------------------------------------------------------------------------------ */
2737#define SEC_GCTL 0xFFCA4000 /* SEC Global Control Register */
2738#define SEC_GSTAT 0xFFCA4004 /* SEC Global Status Register */
2739#define SEC_RAISE 0xFFCA4008 /* SEC Global Raise Register */
2740#define SEC_END 0xFFCA400C /* SEC Global End Register */
2741
2742/* ------------------------------------------------------------------------------------------------------------------------
2743 SEC Source Interface (SSI) Register Definitions
2744 ------------------------------------------------------------------------------------------------------------------------ */
2745#define SEC_SCTL0 0xFFCA4800 /* SEC IRQ Source Control Register n */
2746#define SEC_SCTL1 0xFFCA4808 /* SEC IRQ Source Control Register n */
2747#define SEC_SCTL2 0xFFCA4810 /* SEC IRQ Source Control Register n */
2748#define SEC_SCTL3 0xFFCA4818 /* SEC IRQ Source Control Register n */
2749#define SEC_SCTL4 0xFFCA4820 /* SEC IRQ Source Control Register n */
2750#define SEC_SCTL5 0xFFCA4828 /* SEC IRQ Source Control Register n */
2751#define SEC_SCTL6 0xFFCA4830 /* SEC IRQ Source Control Register n */
2752#define SEC_SCTL7 0xFFCA4838 /* SEC IRQ Source Control Register n */
2753#define SEC_SCTL8 0xFFCA4840 /* SEC IRQ Source Control Register n */
2754#define SEC_SCTL9 0xFFCA4848 /* SEC IRQ Source Control Register n */
2755#define SEC_SCTL10 0xFFCA4850 /* SEC IRQ Source Control Register n */
2756#define SEC_SCTL11 0xFFCA4858 /* SEC IRQ Source Control Register n */
2757#define SEC_SCTL12 0xFFCA4860 /* SEC IRQ Source Control Register n */
2758#define SEC_SCTL13 0xFFCA4868 /* SEC IRQ Source Control Register n */
2759#define SEC_SCTL14 0xFFCA4870 /* SEC IRQ Source Control Register n */
2760#define SEC_SCTL15 0xFFCA4878 /* SEC IRQ Source Control Register n */
2761#define SEC_SCTL16 0xFFCA4880 /* SEC IRQ Source Control Register n */
2762#define SEC_SCTL17 0xFFCA4888 /* SEC IRQ Source Control Register n */
2763#define SEC_SCTL18 0xFFCA4890 /* SEC IRQ Source Control Register n */
2764#define SEC_SCTL19 0xFFCA4898 /* SEC IRQ Source Control Register n */
2765#define SEC_SCTL20 0xFFCA48A0 /* SEC IRQ Source Control Register n */
2766#define SEC_SCTL21 0xFFCA48A8 /* SEC IRQ Source Control Register n */
2767#define SEC_SCTL22 0xFFCA48B0 /* SEC IRQ Source Control Register n */
2768#define SEC_SCTL23 0xFFCA48B8 /* SEC IRQ Source Control Register n */
2769#define SEC_SCTL24 0xFFCA48C0 /* SEC IRQ Source Control Register n */
2770#define SEC_SCTL25 0xFFCA48C8 /* SEC IRQ Source Control Register n */
2771#define SEC_SCTL26 0xFFCA48D0 /* SEC IRQ Source Control Register n */
2772#define SEC_SCTL27 0xFFCA48D8 /* SEC IRQ Source Control Register n */
2773#define SEC_SCTL28 0xFFCA48E0 /* SEC IRQ Source Control Register n */
2774#define SEC_SCTL29 0xFFCA48E8 /* SEC IRQ Source Control Register n */
2775#define SEC_SCTL30 0xFFCA48F0 /* SEC IRQ Source Control Register n */
2776#define SEC_SCTL31 0xFFCA48F8 /* SEC IRQ Source Control Register n */
2777#define SEC_SCTL32 0xFFCA4900 /* SEC IRQ Source Control Register n */
2778#define SEC_SCTL33 0xFFCA4908 /* SEC IRQ Source Control Register n */
2779#define SEC_SCTL34 0xFFCA4910 /* SEC IRQ Source Control Register n */
2780#define SEC_SCTL35 0xFFCA4918 /* SEC IRQ Source Control Register n */
2781#define SEC_SCTL36 0xFFCA4920 /* SEC IRQ Source Control Register n */
2782#define SEC_SCTL37 0xFFCA4928 /* SEC IRQ Source Control Register n */
2783#define SEC_SCTL38 0xFFCA4930 /* SEC IRQ Source Control Register n */
2784#define SEC_SCTL39 0xFFCA4938 /* SEC IRQ Source Control Register n */
2785#define SEC_SCTL40 0xFFCA4940 /* SEC IRQ Source Control Register n */
2786#define SEC_SCTL41 0xFFCA4948 /* SEC IRQ Source Control Register n */
2787#define SEC_SCTL42 0xFFCA4950 /* SEC IRQ Source Control Register n */
2788#define SEC_SCTL43 0xFFCA4958 /* SEC IRQ Source Control Register n */
2789#define SEC_SCTL44 0xFFCA4960 /* SEC IRQ Source Control Register n */
2790#define SEC_SCTL45 0xFFCA4968 /* SEC IRQ Source Control Register n */
2791#define SEC_SCTL46 0xFFCA4970 /* SEC IRQ Source Control Register n */
2792#define SEC_SCTL47 0xFFCA4978 /* SEC IRQ Source Control Register n */
2793#define SEC_SCTL48 0xFFCA4980 /* SEC IRQ Source Control Register n */
2794#define SEC_SCTL49 0xFFCA4988 /* SEC IRQ Source Control Register n */
2795#define SEC_SCTL50 0xFFCA4990 /* SEC IRQ Source Control Register n */
2796#define SEC_SCTL51 0xFFCA4998 /* SEC IRQ Source Control Register n */
2797#define SEC_SCTL52 0xFFCA49A0 /* SEC IRQ Source Control Register n */
2798#define SEC_SCTL53 0xFFCA49A8 /* SEC IRQ Source Control Register n */
2799#define SEC_SCTL54 0xFFCA49B0 /* SEC IRQ Source Control Register n */
2800#define SEC_SCTL55 0xFFCA49B8 /* SEC IRQ Source Control Register n */
2801#define SEC_SCTL56 0xFFCA49C0 /* SEC IRQ Source Control Register n */
2802#define SEC_SCTL57 0xFFCA49C8 /* SEC IRQ Source Control Register n */
2803#define SEC_SCTL58 0xFFCA49D0 /* SEC IRQ Source Control Register n */
2804#define SEC_SCTL59 0xFFCA49D8 /* SEC IRQ Source Control Register n */
2805#define SEC_SCTL60 0xFFCA49E0 /* SEC IRQ Source Control Register n */
2806#define SEC_SCTL61 0xFFCA49E8 /* SEC IRQ Source Control Register n */
2807#define SEC_SCTL62 0xFFCA49F0 /* SEC IRQ Source Control Register n */
2808#define SEC_SCTL63 0xFFCA49F8 /* SEC IRQ Source Control Register n */
2809#define SEC_SCTL64 0xFFCA4A00 /* SEC IRQ Source Control Register n */
2810#define SEC_SCTL65 0xFFCA4A08 /* SEC IRQ Source Control Register n */
2811#define SEC_SCTL66 0xFFCA4A10 /* SEC IRQ Source Control Register n */
2812#define SEC_SCTL67 0xFFCA4A18 /* SEC IRQ Source Control Register n */
2813#define SEC_SCTL68 0xFFCA4A20 /* SEC IRQ Source Control Register n */
2814#define SEC_SCTL69 0xFFCA4A28 /* SEC IRQ Source Control Register n */
2815#define SEC_SCTL70 0xFFCA4A30 /* SEC IRQ Source Control Register n */
2816#define SEC_SCTL71 0xFFCA4A38 /* SEC IRQ Source Control Register n */
2817#define SEC_SCTL72 0xFFCA4A40 /* SEC IRQ Source Control Register n */
2818#define SEC_SCTL73 0xFFCA4A48 /* SEC IRQ Source Control Register n */
2819#define SEC_SCTL74 0xFFCA4A50 /* SEC IRQ Source Control Register n */
2820#define SEC_SCTL75 0xFFCA4A58 /* SEC IRQ Source Control Register n */
2821#define SEC_SCTL76 0xFFCA4A60 /* SEC IRQ Source Control Register n */
2822#define SEC_SCTL77 0xFFCA4A68 /* SEC IRQ Source Control Register n */
2823#define SEC_SCTL78 0xFFCA4A70 /* SEC IRQ Source Control Register n */
2824#define SEC_SCTL79 0xFFCA4A78 /* SEC IRQ Source Control Register n */
2825#define SEC_SCTL80 0xFFCA4A80 /* SEC IRQ Source Control Register n */
2826#define SEC_SCTL81 0xFFCA4A88 /* SEC IRQ Source Control Register n */
2827#define SEC_SCTL82 0xFFCA4A90 /* SEC IRQ Source Control Register n */
2828#define SEC_SCTL83 0xFFCA4A98 /* SEC IRQ Source Control Register n */
2829#define SEC_SCTL84 0xFFCA4AA0 /* SEC IRQ Source Control Register n */
2830#define SEC_SCTL85 0xFFCA4AA8 /* SEC IRQ Source Control Register n */
2831#define SEC_SCTL86 0xFFCA4AB0 /* SEC IRQ Source Control Register n */
2832#define SEC_SCTL87 0xFFCA4AB8 /* SEC IRQ Source Control Register n */
2833#define SEC_SCTL88 0xFFCA4AC0 /* SEC IRQ Source Control Register n */
2834#define SEC_SCTL89 0xFFCA4AC8 /* SEC IRQ Source Control Register n */
2835#define SEC_SCTL90 0xFFCA4AD0 /* SEC IRQ Source Control Register n */
2836#define SEC_SCTL91 0xFFCA4AD8 /* SEC IRQ Source Control Register n */
2837#define SEC_SCTL92 0xFFCA4AE0 /* SEC IRQ Source Control Register n */
2838#define SEC_SCTL93 0xFFCA4AE8 /* SEC IRQ Source Control Register n */
2839#define SEC_SCTL94 0xFFCA4AF0 /* SEC IRQ Source Control Register n */
2840#define SEC_SCTL95 0xFFCA4AF8 /* SEC IRQ Source Control Register n */
2841#define SEC_SCTL96 0xFFCA4B00 /* SEC IRQ Source Control Register n */
2842#define SEC_SCTL97 0xFFCA4B08 /* SEC IRQ Source Control Register n */
2843#define SEC_SCTL98 0xFFCA4B10 /* SEC IRQ Source Control Register n */
2844#define SEC_SCTL99 0xFFCA4B18 /* SEC IRQ Source Control Register n */
2845#define SEC_SCTL100 0xFFCA4B20 /* SEC IRQ Source Control Register n */
2846#define SEC_SCTL101 0xFFCA4B28 /* SEC IRQ Source Control Register n */
2847#define SEC_SCTL102 0xFFCA4B30 /* SEC IRQ Source Control Register n */
2848#define SEC_SCTL103 0xFFCA4B38 /* SEC IRQ Source Control Register n */
2849#define SEC_SCTL104 0xFFCA4B40 /* SEC IRQ Source Control Register n */
2850#define SEC_SCTL105 0xFFCA4B48 /* SEC IRQ Source Control Register n */
2851#define SEC_SCTL106 0xFFCA4B50 /* SEC IRQ Source Control Register n */
2852#define SEC_SCTL107 0xFFCA4B58 /* SEC IRQ Source Control Register n */
2853#define SEC_SCTL108 0xFFCA4B60 /* SEC IRQ Source Control Register n */
2854#define SEC_SCTL109 0xFFCA4B68 /* SEC IRQ Source Control Register n */
2855#define SEC_SCTL110 0xFFCA4B70 /* SEC IRQ Source Control Register n */
2856#define SEC_SCTL111 0xFFCA4B78 /* SEC IRQ Source Control Register n */
2857#define SEC_SCTL112 0xFFCA4B80 /* SEC IRQ Source Control Register n */
2858#define SEC_SCTL113 0xFFCA4B88 /* SEC IRQ Source Control Register n */
2859#define SEC_SCTL114 0xFFCA4B90 /* SEC IRQ Source Control Register n */
2860#define SEC_SCTL115 0xFFCA4B98 /* SEC IRQ Source Control Register n */
2861#define SEC_SCTL116 0xFFCA4BA0 /* SEC IRQ Source Control Register n */
2862#define SEC_SCTL117 0xFFCA4BA8 /* SEC IRQ Source Control Register n */
2863#define SEC_SCTL118 0xFFCA4BB0 /* SEC IRQ Source Control Register n */
2864#define SEC_SCTL119 0xFFCA4BB8 /* SEC IRQ Source Control Register n */
2865#define SEC_SCTL120 0xFFCA4BC0 /* SEC IRQ Source Control Register n */
2866#define SEC_SCTL121 0xFFCA4BC8 /* SEC IRQ Source Control Register n */
2867#define SEC_SCTL122 0xFFCA4BD0 /* SEC IRQ Source Control Register n */
2868#define SEC_SCTL123 0xFFCA4BD8 /* SEC IRQ Source Control Register n */
2869#define SEC_SCTL124 0xFFCA4BE0 /* SEC IRQ Source Control Register n */
2870#define SEC_SCTL125 0xFFCA4BE8 /* SEC IRQ Source Control Register n */
2871#define SEC_SCTL126 0xFFCA4BF0 /* SEC IRQ Source Control Register n */
2872#define SEC_SCTL127 0xFFCA4BF8 /* SEC IRQ Source Control Register n */
2873#define SEC_SCTL128 0xFFCA4C00 /* SEC IRQ Source Control Register n */
2874#define SEC_SCTL129 0xFFCA4C08 /* SEC IRQ Source Control Register n */
2875#define SEC_SCTL130 0xFFCA4C10 /* SEC IRQ Source Control Register n */
2876#define SEC_SCTL131 0xFFCA4C18 /* SEC IRQ Source Control Register n */
2877#define SEC_SCTL132 0xFFCA4C20 /* SEC IRQ Source Control Register n */
2878#define SEC_SCTL133 0xFFCA4C28 /* SEC IRQ Source Control Register n */
2879#define SEC_SCTL134 0xFFCA4C30 /* SEC IRQ Source Control Register n */
2880#define SEC_SCTL135 0xFFCA4C38 /* SEC IRQ Source Control Register n */
2881#define SEC_SCTL136 0xFFCA4C40 /* SEC IRQ Source Control Register n */
2882#define SEC_SCTL137 0xFFCA4C48 /* SEC IRQ Source Control Register n */
2883#define SEC_SCTL138 0xFFCA4C50 /* SEC IRQ Source Control Register n */
2884#define SEC_SCTL139 0xFFCA4C58 /* SEC IRQ Source Control Register n */
2885#define SEC_SSTAT0 0xFFCA4804 /* SEC IRQ Source Status Register n */
2886#define SEC_SSTAT1 0xFFCA480C /* SEC IRQ Source Status Register n */
2887#define SEC_SSTAT2 0xFFCA4814 /* SEC IRQ Source Status Register n */
2888#define SEC_SSTAT3 0xFFCA481C /* SEC IRQ Source Status Register n */
2889#define SEC_SSTAT4 0xFFCA4824 /* SEC IRQ Source Status Register n */
2890#define SEC_SSTAT5 0xFFCA482C /* SEC IRQ Source Status Register n */
2891#define SEC_SSTAT6 0xFFCA4834 /* SEC IRQ Source Status Register n */
2892#define SEC_SSTAT7 0xFFCA483C /* SEC IRQ Source Status Register n */
2893#define SEC_SSTAT8 0xFFCA4844 /* SEC IRQ Source Status Register n */
2894#define SEC_SSTAT9 0xFFCA484C /* SEC IRQ Source Status Register n */
2895#define SEC_SSTAT10 0xFFCA4854 /* SEC IRQ Source Status Register n */
2896#define SEC_SSTAT11 0xFFCA485C /* SEC IRQ Source Status Register n */
2897#define SEC_SSTAT12 0xFFCA4864 /* SEC IRQ Source Status Register n */
2898#define SEC_SSTAT13 0xFFCA486C /* SEC IRQ Source Status Register n */
2899#define SEC_SSTAT14 0xFFCA4874 /* SEC IRQ Source Status Register n */
2900#define SEC_SSTAT15 0xFFCA487C /* SEC IRQ Source Status Register n */
2901#define SEC_SSTAT16 0xFFCA4884 /* SEC IRQ Source Status Register n */
2902#define SEC_SSTAT17 0xFFCA488C /* SEC IRQ Source Status Register n */
2903#define SEC_SSTAT18 0xFFCA4894 /* SEC IRQ Source Status Register n */
2904#define SEC_SSTAT19 0xFFCA489C /* SEC IRQ Source Status Register n */
2905#define SEC_SSTAT20 0xFFCA48A4 /* SEC IRQ Source Status Register n */
2906#define SEC_SSTAT21 0xFFCA48AC /* SEC IRQ Source Status Register n */
2907#define SEC_SSTAT22 0xFFCA48B4 /* SEC IRQ Source Status Register n */
2908#define SEC_SSTAT23 0xFFCA48BC /* SEC IRQ Source Status Register n */
2909#define SEC_SSTAT24 0xFFCA48C4 /* SEC IRQ Source Status Register n */
2910#define SEC_SSTAT25 0xFFCA48CC /* SEC IRQ Source Status Register n */
2911#define SEC_SSTAT26 0xFFCA48D4 /* SEC IRQ Source Status Register n */
2912#define SEC_SSTAT27 0xFFCA48DC /* SEC IRQ Source Status Register n */
2913#define SEC_SSTAT28 0xFFCA48E4 /* SEC IRQ Source Status Register n */
2914#define SEC_SSTAT29 0xFFCA48EC /* SEC IRQ Source Status Register n */
2915#define SEC_SSTAT30 0xFFCA48F4 /* SEC IRQ Source Status Register n */
2916#define SEC_SSTAT31 0xFFCA48FC /* SEC IRQ Source Status Register n */
2917#define SEC_SSTAT32 0xFFCA4904 /* SEC IRQ Source Status Register n */
2918#define SEC_SSTAT33 0xFFCA490C /* SEC IRQ Source Status Register n */
2919#define SEC_SSTAT34 0xFFCA4914 /* SEC IRQ Source Status Register n */
2920#define SEC_SSTAT35 0xFFCA491C /* SEC IRQ Source Status Register n */
2921#define SEC_SSTAT36 0xFFCA4924 /* SEC IRQ Source Status Register n */
2922#define SEC_SSTAT37 0xFFCA492C /* SEC IRQ Source Status Register n */
2923#define SEC_SSTAT38 0xFFCA4934 /* SEC IRQ Source Status Register n */
2924#define SEC_SSTAT39 0xFFCA493C /* SEC IRQ Source Status Register n */
2925#define SEC_SSTAT40 0xFFCA4944 /* SEC IRQ Source Status Register n */
2926#define SEC_SSTAT41 0xFFCA494C /* SEC IRQ Source Status Register n */
2927#define SEC_SSTAT42 0xFFCA4954 /* SEC IRQ Source Status Register n */
2928#define SEC_SSTAT43 0xFFCA495C /* SEC IRQ Source Status Register n */
2929#define SEC_SSTAT44 0xFFCA4964 /* SEC IRQ Source Status Register n */
2930#define SEC_SSTAT45 0xFFCA496C /* SEC IRQ Source Status Register n */
2931#define SEC_SSTAT46 0xFFCA4974 /* SEC IRQ Source Status Register n */
2932#define SEC_SSTAT47 0xFFCA497C /* SEC IRQ Source Status Register n */
2933#define SEC_SSTAT48 0xFFCA4984 /* SEC IRQ Source Status Register n */
2934#define SEC_SSTAT49 0xFFCA498C /* SEC IRQ Source Status Register n */
2935#define SEC_SSTAT50 0xFFCA4994 /* SEC IRQ Source Status Register n */
2936#define SEC_SSTAT51 0xFFCA499C /* SEC IRQ Source Status Register n */
2937#define SEC_SSTAT52 0xFFCA49A4 /* SEC IRQ Source Status Register n */
2938#define SEC_SSTAT53 0xFFCA49AC /* SEC IRQ Source Status Register n */
2939#define SEC_SSTAT54 0xFFCA49B4 /* SEC IRQ Source Status Register n */
2940#define SEC_SSTAT55 0xFFCA49BC /* SEC IRQ Source Status Register n */
2941#define SEC_SSTAT56 0xFFCA49C4 /* SEC IRQ Source Status Register n */
2942#define SEC_SSTAT57 0xFFCA49CC /* SEC IRQ Source Status Register n */
2943#define SEC_SSTAT58 0xFFCA49D4 /* SEC IRQ Source Status Register n */
2944#define SEC_SSTAT59 0xFFCA49DC /* SEC IRQ Source Status Register n */
2945#define SEC_SSTAT60 0xFFCA49E4 /* SEC IRQ Source Status Register n */
2946#define SEC_SSTAT61 0xFFCA49EC /* SEC IRQ Source Status Register n */
2947#define SEC_SSTAT62 0xFFCA49F4 /* SEC IRQ Source Status Register n */
2948#define SEC_SSTAT63 0xFFCA49FC /* SEC IRQ Source Status Register n */
2949#define SEC_SSTAT64 0xFFCA4A04 /* SEC IRQ Source Status Register n */
2950#define SEC_SSTAT65 0xFFCA4A0C /* SEC IRQ Source Status Register n */
2951#define SEC_SSTAT66 0xFFCA4A14 /* SEC IRQ Source Status Register n */
2952#define SEC_SSTAT67 0xFFCA4A1C /* SEC IRQ Source Status Register n */
2953#define SEC_SSTAT68 0xFFCA4A24 /* SEC IRQ Source Status Register n */
2954#define SEC_SSTAT69 0xFFCA4A2C /* SEC IRQ Source Status Register n */
2955#define SEC_SSTAT70 0xFFCA4A34 /* SEC IRQ Source Status Register n */
2956#define SEC_SSTAT71 0xFFCA4A3C /* SEC IRQ Source Status Register n */
2957#define SEC_SSTAT72 0xFFCA4A44 /* SEC IRQ Source Status Register n */
2958#define SEC_SSTAT73 0xFFCA4A4C /* SEC IRQ Source Status Register n */
2959#define SEC_SSTAT74 0xFFCA4A54 /* SEC IRQ Source Status Register n */
2960#define SEC_SSTAT75 0xFFCA4A5C /* SEC IRQ Source Status Register n */
2961#define SEC_SSTAT76 0xFFCA4A64 /* SEC IRQ Source Status Register n */
2962#define SEC_SSTAT77 0xFFCA4A6C /* SEC IRQ Source Status Register n */
2963#define SEC_SSTAT78 0xFFCA4A74 /* SEC IRQ Source Status Register n */
2964#define SEC_SSTAT79 0xFFCA4A7C /* SEC IRQ Source Status Register n */
2965#define SEC_SSTAT80 0xFFCA4A84 /* SEC IRQ Source Status Register n */
2966#define SEC_SSTAT81 0xFFCA4A8C /* SEC IRQ Source Status Register n */
2967#define SEC_SSTAT82 0xFFCA4A94 /* SEC IRQ Source Status Register n */
2968#define SEC_SSTAT83 0xFFCA4A9C /* SEC IRQ Source Status Register n */
2969#define SEC_SSTAT84 0xFFCA4AA4 /* SEC IRQ Source Status Register n */
2970#define SEC_SSTAT85 0xFFCA4AAC /* SEC IRQ Source Status Register n */
2971#define SEC_SSTAT86 0xFFCA4AB4 /* SEC IRQ Source Status Register n */
2972#define SEC_SSTAT87 0xFFCA4ABC /* SEC IRQ Source Status Register n */
2973#define SEC_SSTAT88 0xFFCA4AC4 /* SEC IRQ Source Status Register n */
2974#define SEC_SSTAT89 0xFFCA4ACC /* SEC IRQ Source Status Register n */
2975#define SEC_SSTAT90 0xFFCA4AD4 /* SEC IRQ Source Status Register n */
2976#define SEC_SSTAT91 0xFFCA4ADC /* SEC IRQ Source Status Register n */
2977#define SEC_SSTAT92 0xFFCA4AE4 /* SEC IRQ Source Status Register n */
2978#define SEC_SSTAT93 0xFFCA4AEC /* SEC IRQ Source Status Register n */
2979#define SEC_SSTAT94 0xFFCA4AF4 /* SEC IRQ Source Status Register n */
2980#define SEC_SSTAT95 0xFFCA4AFC /* SEC IRQ Source Status Register n */
2981#define SEC_SSTAT96 0xFFCA4B04 /* SEC IRQ Source Status Register n */
2982#define SEC_SSTAT97 0xFFCA4B0C /* SEC IRQ Source Status Register n */
2983#define SEC_SSTAT98 0xFFCA4B14 /* SEC IRQ Source Status Register n */
2984#define SEC_SSTAT99 0xFFCA4B1C /* SEC IRQ Source Status Register n */
2985#define SEC_SSTAT100 0xFFCA4B24 /* SEC IRQ Source Status Register n */
2986#define SEC_SSTAT101 0xFFCA4B2C /* SEC IRQ Source Status Register n */
2987#define SEC_SSTAT102 0xFFCA4B34 /* SEC IRQ Source Status Register n */
2988#define SEC_SSTAT103 0xFFCA4B3C /* SEC IRQ Source Status Register n */
2989#define SEC_SSTAT104 0xFFCA4B44 /* SEC IRQ Source Status Register n */
2990#define SEC_SSTAT105 0xFFCA4B4C /* SEC IRQ Source Status Register n */
2991#define SEC_SSTAT106 0xFFCA4B54 /* SEC IRQ Source Status Register n */
2992#define SEC_SSTAT107 0xFFCA4B5C /* SEC IRQ Source Status Register n */
2993#define SEC_SSTAT108 0xFFCA4B64 /* SEC IRQ Source Status Register n */
2994#define SEC_SSTAT109 0xFFCA4B6C /* SEC IRQ Source Status Register n */
2995#define SEC_SSTAT110 0xFFCA4B74 /* SEC IRQ Source Status Register n */
2996#define SEC_SSTAT111 0xFFCA4B7C /* SEC IRQ Source Status Register n */
2997#define SEC_SSTAT112 0xFFCA4B84 /* SEC IRQ Source Status Register n */
2998#define SEC_SSTAT113 0xFFCA4B8C /* SEC IRQ Source Status Register n */
2999#define SEC_SSTAT114 0xFFCA4B94 /* SEC IRQ Source Status Register n */
3000#define SEC_SSTAT115 0xFFCA4B9C /* SEC IRQ Source Status Register n */
3001#define SEC_SSTAT116 0xFFCA4BA4 /* SEC IRQ Source Status Register n */
3002#define SEC_SSTAT117 0xFFCA4BAC /* SEC IRQ Source Status Register n */
3003#define SEC_SSTAT118 0xFFCA4BB4 /* SEC IRQ Source Status Register n */
3004#define SEC_SSTAT119 0xFFCA4BBC /* SEC IRQ Source Status Register n */
3005#define SEC_SSTAT120 0xFFCA4BC4 /* SEC IRQ Source Status Register n */
3006#define SEC_SSTAT121 0xFFCA4BCC /* SEC IRQ Source Status Register n */
3007#define SEC_SSTAT122 0xFFCA4BD4 /* SEC IRQ Source Status Register n */
3008#define SEC_SSTAT123 0xFFCA4BDC /* SEC IRQ Source Status Register n */
3009#define SEC_SSTAT124 0xFFCA4BE4 /* SEC IRQ Source Status Register n */
3010#define SEC_SSTAT125 0xFFCA4BEC /* SEC IRQ Source Status Register n */
3011#define SEC_SSTAT126 0xFFCA4BF4 /* SEC IRQ Source Status Register n */
3012#define SEC_SSTAT127 0xFFCA4BFC /* SEC IRQ Source Status Register n */
3013#define SEC_SSTAT128 0xFFCA4C04 /* SEC IRQ Source Status Register n */
3014#define SEC_SSTAT129 0xFFCA4C0C /* SEC IRQ Source Status Register n */
3015#define SEC_SSTAT130 0xFFCA4C14 /* SEC IRQ Source Status Register n */
3016#define SEC_SSTAT131 0xFFCA4C1C /* SEC IRQ Source Status Register n */
3017#define SEC_SSTAT132 0xFFCA4C24 /* SEC IRQ Source Status Register n */
3018#define SEC_SSTAT133 0xFFCA4C2C /* SEC IRQ Source Status Register n */
3019#define SEC_SSTAT134 0xFFCA4C34 /* SEC IRQ Source Status Register n */
3020#define SEC_SSTAT135 0xFFCA4C3C /* SEC IRQ Source Status Register n */
3021#define SEC_SSTAT136 0xFFCA4C44 /* SEC IRQ Source Status Register n */
3022#define SEC_SSTAT137 0xFFCA4C4C /* SEC IRQ Source Status Register n */
3023#define SEC_SSTAT138 0xFFCA4C54 /* SEC IRQ Source Status Register n */
3024#define SEC_SSTAT139 0xFFCA4C5C /* SEC IRQ Source Status Register n */
3025
3026/* ------------------------------------------------------------------------------------------------------------------------
3027 SEC_CCTL Pos/Masks Description
3028 ------------------------------------------------------------------------------------------------------------------------ */
3029#define SEC_CCTL_LOCK 0x80000000 /* LOCK: Lock */
3030#define SEC_CCTL_NMI_EN 0x00010000 /* NMIEN: Enable */
3031#define SEC_CCTL_WAITIDLE 0x00001000 /* WFI: Wait for Idle */
3032#define SEC_CCTL_RESET 0x00000002 /* RESET: Reset */
3033#define SEC_CCTL_EN 0x00000001 /* EN: Enable */
3034
3035/* ------------------------------------------------------------------------------------------------------------------------
3036 SEC_CSTAT Pos/Masks Description
3037 ------------------------------------------------------------------------------------------------------------------------ */
3038#define SEC_CSTAT_NMI 0x00010000 /* NMI Status */
3039#define SEC_CSTAT_WAITING 0x00001000 /* WFI: Waiting */
3040#define SEC_CSTAT_VALID_SID 0x00000400 /* SIDV: Valid */
3041#define SEC_CSTAT_VALID_ACT 0x00000200 /* ACTV: Valid */
3042#define SEC_CSTAT_VALID_PND 0x00000100 /* PNDV: Valid */
3043#define SEC_CSTAT_ERRC 0x00000030 /* Error Cause */
3044#define SEC_CSTAT_ACKERR 0x00000010 /* ERRC: Acknowledge Error */
3045#define SEC_CSTAT_ERR 0x00000002 /* ERR: Error Occurred */
3046
3047/* ------------------------------------------------------------------------------------------------------------------------
3048 SEC_CPND Pos/Masks Description
3049 ------------------------------------------------------------------------------------------------------------------------ */
3050#define SEC_CPND_PRIO 0x0000FF00 /* Highest Pending IRQ Priority */
3051#define SEC_CPND_SID 0x000000FF /* Highest Pending IRQ Source ID */
3052
3053/* ------------------------------------------------------------------------------------------------------------------------
3054 SEC_CACT Pos/Masks Description
3055 ------------------------------------------------------------------------------------------------------------------------ */
3056#define SEC_CACT_PRIO 0x0000FF00 /* Highest Active IRQ Priority */
3057#define SEC_CACT_SID 0x000000FF /* Highest Active IRQ Source ID */
3058
3059/* ------------------------------------------------------------------------------------------------------------------------
3060 SEC_CPMSK Pos/Masks Description
3061 ------------------------------------------------------------------------------------------------------------------------ */
3062#define SEC_CPMSK_LOCK 0x80000000 /* LOCK: Lock */
3063#define SEC_CPMSK_PRIO 0x000000FF /* IRQ Priority Mask */
3064
3065/* ------------------------------------------------------------------------------------------------------------------------
3066 SEC_CGMSK Pos/Masks Description
3067 ------------------------------------------------------------------------------------------------------------------------ */
3068#define SEC_CGMSK_LOCK 0x80000000 /* LOCK: Lock */
3069#define SEC_CGMSK_MASK 0x00000100 /* UGRP: Mask Ungrouped Sources */
3070#define SEC_CGMSK_GRP 0x0000000F /* Grouped Mask */
3071
3072/* ------------------------------------------------------------------------------------------------------------------------
3073 SEC_CPLVL Pos/Masks Description
3074 ------------------------------------------------------------------------------------------------------------------------ */
3075#define SEC_CPLVL_LOCK 0x80000000 /* LOCK: Lock */
3076#define SEC_CPLVL_PLVL 0x00000007 /* Priority Levels */
3077
3078/* ------------------------------------------------------------------------------------------------------------------------
3079 SEC_CSID Pos/Masks Description
3080 ------------------------------------------------------------------------------------------------------------------------ */
3081#define SEC_CSID_SID 0x000000FF /* Source ID */
3082
3083
3084/* ------------------------------------------------------------------------------------------------------------------------
3085 SEC_FCTL Pos/Masks Description
3086 ------------------------------------------------------------------------------------------------------------------------ */
3087#define SEC_FCTL_LOCK 0x80000000 /* LOCK: Lock */
3088#define SEC_FCTL_FLTPND_MODE 0x00002000 /* TES: Fault Pending Mode */
3089#define SEC_FCTL_COP_MODE 0x00001000 /* CMS: COP Mode */
3090#define SEC_FCTL_FLTIN_EN 0x00000080 /* FIEN: Enable */
3091#define SEC_FCTL_SYSRST_EN 0x00000040 /* SREN: Enable */
3092#define SEC_FCTL_TRGOUT_EN 0x00000020 /* TOEN: Enable */
3093#define SEC_FCTL_FLTOUT_EN 0x00000010 /* FOEN: Enable */
3094#define SEC_FCTL_RESET 0x00000002 /* RESET: Reset */
3095#define SEC_FCTL_EN 0x00000001 /* EN: Enable */
3096
3097/* ------------------------------------------------------------------------------------------------------------------------
3098 SEC_FSTAT Pos/Masks Description
3099 ------------------------------------------------------------------------------------------------------------------------ */
3100#define SEC_FSTAT_NXTFLT 0x00000400 /* NPND: Pending */
3101#define SEC_FSTAT_FLTACT 0x00000200 /* ACT: Active Fault */
3102#define SEC_FSTAT_FLTPND 0x00000100 /* PND: Pending */
3103#define SEC_FSTAT_ERRC 0x00000030 /* Error Cause */
3104#define SEC_FSTAT_ENDERR 0x00000020 /* ERRC: End Error */
3105#define SEC_FSTAT_ERR 0x00000002 /* ERR: Error Occurred */
3106
3107/* ------------------------------------------------------------------------------------------------------------------------
3108 SEC_FSID Pos/Masks Description
3109 ------------------------------------------------------------------------------------------------------------------------ */
3110#define SEC_FSID_SRC_EXTFLT 0x00010000 /* FEXT: Fault External */
3111#define SEC_FSID_SID 0x000000FF /* Source ID */
3112
3113/* ------------------------------------------------------------------------------------------------------------------------
3114 SEC_FEND Pos/Masks Description
3115 ------------------------------------------------------------------------------------------------------------------------ */
3116#define SEC_FEND_END_EXTFLT 0x00010000 /* FEXT: Fault External */
3117#define SEC_FEND_SID 0x000000FF /* Source ID */
3118
3119
3120/* ------------------------------------------------------------------------------------------------------------------------
3121 SEC_GCTL Pos/Masks Description
3122 ------------------------------------------------------------------------------------------------------------------------ */
3123#define SEC_GCTL_LOCK 0x80000000 /* Lock */
3124#define SEC_GCTL_RESET 0x00000002 /* Reset */
3125#define SEC_GCTL_EN 0x00000001 /* Enable */
3126
3127/* ------------------------------------------------------------------------------------------------------------------------
3128 SEC_GSTAT Pos/Masks Description
3129 ------------------------------------------------------------------------------------------------------------------------ */
3130#define SEC_GSTAT_LWERR 0x80000000 /* LWERR: Error Occurred */
3131#define SEC_GSTAT_ADRERR 0x40000000 /* ADRERR: Error Occurred */
3132#define SEC_GSTAT_SID 0x00FF0000 /* Source ID for SSI Error */
3133#define SEC_GSTAT_SCI 0x00000F00 /* SCI ID for SCI Error */
3134#define SEC_GSTAT_ERRC 0x00000030 /* Error Cause */
3135#define SEC_GSTAT_SCIERR 0x00000010 /* ERRC: SCI Error */
3136#define SEC_GSTAT_SSIERR 0x00000020 /* ERRC: SSI Error */
3137#define SEC_GSTAT_ERR 0x00000002 /* ERR: Error Occurred */
3138
3139/* ------------------------------------------------------------------------------------------------------------------------
3140 SEC_RAISE Pos/Masks Description
3141 ------------------------------------------------------------------------------------------------------------------------ */
3142#define SEC_RAISE_SID 0x000000FF /* Source ID IRQ Set to Pending */
3143
3144/* ------------------------------------------------------------------------------------------------------------------------
3145 SEC_END Pos/Masks Description
3146 ------------------------------------------------------------------------------------------------------------------------ */
3147#define SEC_END_SID 0x000000FF /* Source ID IRQ to End */
3148
3149
3150/* ------------------------------------------------------------------------------------------------------------------------
3151 SEC_SCTL Pos/Masks Description
3152 ------------------------------------------------------------------------------------------------------------------------ */
3153#define SEC_SCTL_LOCK 0x80000000 /* Lock */
3154#define SEC_SCTL_CTG 0x0F000000 /* Core Target Select */
3155#define SEC_SCTL_GRP 0x000F0000 /* Group Select */
3156#define SEC_SCTL_PRIO 0x0000FF00 /* Priority Level Select */
3157#define SEC_SCTL_ERR_EN 0x00000010 /* ERREN: Enable */
3158#define SEC_SCTL_EDGE 0x00000008 /* ES: Edge Sensitive */
3159#define SEC_SCTL_SRC_EN 0x00000004 /* SEN: Enable */
3160#define SEC_SCTL_FAULT_EN 0x00000002 /* FEN: Enable */
3161#define SEC_SCTL_INT_EN 0x00000001 /* IEN: Enable */
3162
3163/* ------------------------------------------------------------------------------------------------------------------------
3164 SEC_SSTAT Pos/Masks Description
3165 ------------------------------------------------------------------------------------------------------------------------ */
3166#define SEC_SSTAT_CHID 0x00FF0000 /* Channel ID */
3167#define SEC_SSTAT_ACTIVE_SRC 0x00000200 /* ACT: Active Source */
3168#define SEC_SSTAT_PENDING 0x00000100 /* PND: Pending */
3169#define SEC_SSTAT_ERRC 0x00000030 /* Error Cause */
3170#define SEC_SSTAT_ENDERR 0x00000020 /* ERRC: End Error */
3171#define SEC_SSTAT_ERR 0x00000002 /* Error */
3172
3173
3174/* =========================
3175 RCU Registers
3176 ========================= */
3177
3178/* =========================
3179 RCU0
3180 ========================= */
3181#define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */
3182#define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */
3183#define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */
3184#define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */
3185#define RCU0_SIDIS 0xFFCA6010 /* RCU0 System Interface Disable Register */
3186#define RCU0_SISTAT 0xFFCA6014 /* RCU0 System Interface Status Register */
3187#define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */
3188#define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */
3189#define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */
3190#define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */
3191
3192
3193/* =========================
3194 CGU0
3195 ========================= */
3196#define CGU0_CTL 0xFFCA8000 /* CGU0 Control Register */
3197#define CGU0_STAT 0xFFCA8004 /* CGU0 Status Register */
3198#define CGU0_DIV 0xFFCA8008 /* CGU0 Divisor Register */
3199#define CGU0_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */
3200
3201
3202/* =========================
3203 DPM Registers
3204 ========================= */
3205
3206/* =========================
3207 DPM0
3208 ========================= */
3209#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */
3210#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */
3211#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable Register */
3212#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable Register */
3213#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status Register */
3214#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Status Sticky Register */
3215#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable Register */
3216#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */
3217#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */
3218#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */
3219#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */
3220#define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */
3221#define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */
3222#define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */
3223#define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */
3224#define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */
3225#define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */
3226#define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */
3227#define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */
3228#define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */
3229#define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */
3230#define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */
3231#define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */
3232#define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */
3233#define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */
3234#define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */
3235#define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */
3236#define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */
3237
3238
3239/* =========================
3240 DBG Registers
3241 ========================= */
3242
3243/* USB register */
3244#define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode */
3245#define USB_POWER 0xFFCC1001 /* USB Power and Device Control */
3246#define USB_INTRTX 0xFFCC1002 /* USB Transmit Interrupt */
3247#define USB_INTRRX 0xFFCC1004 /* USB Receive Interrupts */
3248#define USB_INTRTXE 0xFFCC1006 /* USB Transmit Interrupt Enable */
3249#define USB_INTRRXE 0xFFCC1008 /* USB Receive Interrupt Enable */
3250#define USB_INTRUSB 0xFFCC100A /* USB USB Interrupts */
3251#define USB_INTRUSBE 0xFFCC100B /* USB USB Interrupt Enable */
3252#define USB_FRAME 0xFFCC100C /* USB Frame Number */
3253#define USB_INDEX 0xFFCC100E /* USB Index */
3254#define USB_TESTMODE 0xFFCC100F /* USB Testmodes */
3255#define USB_EPI_TXMAXP0 0xFFCC1010 /* USB Transmit Maximum Packet Length */
3256#define USB_EP_NI0_TXMAXP 0xFFCC1010
3257#define USB_EP0I_CSR0_H 0xFFCC1012 /* USB Config and Status EP0 */
3258#define USB_EPI_TXCSR0_H 0xFFCC1012 /* USB Transmit Configuration and Status */
3259#define USB_EP0I_CSR0_P 0xFFCC1012 /* USB Config and Status EP0 */
3260#define USB_EPI_TXCSR0_P 0xFFCC1012 /* USB Transmit Configuration and Status */
3261#define USB_EPI_RXMAXP0 0xFFCC1014 /* USB Receive Maximum Packet Length */
3262#define USB_EPI_RXCSR0_H 0xFFCC1016 /* USB Receive Configuration and Status Register */
3263#define USB_EPI_RXCSR0_P 0xFFCC1016 /* USB Receive Configuration and Status Register */
3264#define USB_EP0I_CNT0 0xFFCC1018 /* USB Number of Received Bytes for Endpoint 0 */
3265#define USB_EPI_RXCNT0 0xFFCC1018 /* USB Number of Byte Received */
3266#define USB_EP0I_TYPE0 0xFFCC101A /* USB Speed for Endpoint 0 */
3267#define USB_EPI_TXTYPE0 0xFFCC101A /* USB Transmit Type */
3268#define USB_EP0I_NAKLIMIT0 0xFFCC101B /* USB NAK Response Timeout for Endpoint 0 */
3269#define USB_EPI_TXINTERVAL0 0xFFCC101B /* USB Transmit Polling Interval */
3270#define USB_EPI_RXTYPE0 0xFFCC101C /* USB Receive Type */
3271#define USB_EPI_RXINTERVAL0 0xFFCC101D /* USB Receive Polling Interval */
3272#define USB_EP0I_CFGDATA0 0xFFCC101F /* USB Configuration Information */
3273#define USB_FIFOB0 0xFFCC1020 /* USB FIFO Data */
3274#define USB_FIFOB1 0xFFCC1024 /* USB FIFO Data */
3275#define USB_FIFOB2 0xFFCC1028 /* USB FIFO Data */
3276#define USB_FIFOB3 0xFFCC102C /* USB FIFO Data */
3277#define USB_FIFOB4 0xFFCC1030 /* USB FIFO Data */
3278#define USB_FIFOB5 0xFFCC1034 /* USB FIFO Data */
3279#define USB_FIFOB6 0xFFCC1038 /* USB FIFO Data */
3280#define USB_FIFOB7 0xFFCC103C /* USB FIFO Data */
3281#define USB_FIFOB8 0xFFCC1040 /* USB FIFO Data */
3282#define USB_FIFOB9 0xFFCC1044 /* USB FIFO Data */
3283#define USB_FIFOB10 0xFFCC1048 /* USB FIFO Data */
3284#define USB_FIFOB11 0xFFCC104C /* USB FIFO Data */
3285#define USB_FIFOH0 0xFFCC1020 /* USB FIFO Data */
3286#define USB_FIFOH1 0xFFCC1024 /* USB FIFO Data */
3287#define USB_FIFOH2 0xFFCC1028 /* USB FIFO Data */
3288#define USB_FIFOH3 0xFFCC102C /* USB FIFO Data */
3289#define USB_FIFOH4 0xFFCC1030 /* USB FIFO Data */
3290#define USB_FIFOH5 0xFFCC1034 /* USB FIFO Data */
3291#define USB_FIFOH6 0xFFCC1038 /* USB FIFO Data */
3292#define USB_FIFOH7 0xFFCC103C /* USB FIFO Data */
3293#define USB_FIFOH8 0xFFCC1040 /* USB FIFO Data */
3294#define USB_FIFOH9 0xFFCC1044 /* USB FIFO Data */
3295#define USB_FIFOH10 0xFFCC1048 /* USB FIFO Data */
3296#define USB_FIFOH11 0xFFCC104C /* USB FIFO Data */
3297#define USB_FIFO0 0xFFCC1020 /* USB FIFO Data */
3298#define USB_EP0_FIFO 0xFFCC1020
3299#define USB_FIFO1 0xFFCC1024 /* USB FIFO Data */
3300#define USB_FIFO2 0xFFCC1028 /* USB FIFO Data */
3301#define USB_FIFO3 0xFFCC102C /* USB FIFO Data */
3302#define USB_FIFO4 0xFFCC1030 /* USB FIFO Data */
3303#define USB_FIFO5 0xFFCC1034 /* USB FIFO Data */
3304#define USB_FIFO6 0xFFCC1038 /* USB FIFO Data */
3305#define USB_FIFO7 0xFFCC103C /* USB FIFO Data */
3306#define USB_FIFO8 0xFFCC1040 /* USB FIFO Data */
3307#define USB_FIFO9 0xFFCC1044 /* USB FIFO Data */
3308#define USB_FIFO10 0xFFCC1048 /* USB FIFO Data */
3309#define USB_FIFO11 0xFFCC104C /* USB FIFO Data */
3310#define USB_OTG_DEV_CTL 0xFFCC1060 /* USB Device Control */
3311#define USB_TXFIFOSZ 0xFFCC1062 /* USB Transmit FIFO Size */
3312#define USB_RXFIFOSZ 0xFFCC1063 /* USB Receive FIFO Size */
3313#define USB_TXFIFOADDR 0xFFCC1064 /* USB Transmit FIFO Address */
3314#define USB_RXFIFOADDR 0xFFCC1066 /* USB Receive FIFO Address */
3315#define USB_VENDSTAT 0xFFCC1068 /* USB Vendor Status */
3316#define USB_HWVERS 0xFFCC106C /* USB Hardware Version */
3317#define USB_EPINFO 0xFFCC1078 /* USB Endpoint Info */
3318#define USB_RAMINFO 0xFFCC1079 /* USB Ram Information */
3319#define USB_LINKINFO 0xFFCC107A /* USB Programmable Delay Values */
3320#define USB_VPLEN 0xFFCC107B /* USB VBus Pulse Duration */
3321#define USB_HS_EOF1 0xFFCC107C /* USB High Speed End of Frame Remaining */
3322#define USB_FS_EOF1 0xFFCC107D /* USB Full Speed End of Frame Remaining */
3323#define USB_LS_EOF1 0xFFCC107E /* USB Low Speed End of Frame Remaining */
3324#define USB_SOFT_RST 0xFFCC107F /* USB Software Reset */
3325#define USB_TXFUNCADDR0 0xFFCC1080 /* USB Transmit Function Address */
3326#define USB_TXFUNCADDR1 0xFFCC1088 /* USB Transmit Function Address */
3327#define USB_TXFUNCADDR2 0xFFCC1090 /* USB Transmit Function Address */
3328#define USB_TXFUNCADDR3 0xFFCC1098 /* USB Transmit Function Address */
3329#define USB_TXFUNCADDR4 0xFFCC10A0 /* USB Transmit Function Address */
3330#define USB_TXFUNCADDR5 0xFFCC10A8 /* USB Transmit Function Address */
3331#define USB_TXFUNCADDR6 0xFFCC10B0 /* USB Transmit Function Address */
3332#define USB_TXFUNCADDR7 0xFFCC10B8 /* USB Transmit Function Address */
3333#define USB_TXFUNCADDR8 0xFFCC10C0 /* USB Transmit Function Address */
3334#define USB_TXFUNCADDR9 0xFFCC10C8 /* USB Transmit Function Address */
3335#define USB_TXFUNCADDR10 0xFFCC10D0 /* USB Transmit Function Address */
3336#define USB_TXFUNCADDR11 0xFFCC10D8 /* USB Transmit Function Address */
3337#define USB_TXHUBADDR0 0xFFCC1082 /* USB Transmit Hub Address */
3338#define USB_TXHUBADDR1 0xFFCC108A /* USB Transmit Hub Address */
3339#define USB_TXHUBADDR2 0xFFCC1092 /* USB Transmit Hub Address */
3340#define USB_TXHUBADDR3 0xFFCC109A /* USB Transmit Hub Address */
3341#define USB_TXHUBADDR4 0xFFCC10A2 /* USB Transmit Hub Address */
3342#define USB_TXHUBADDR5 0xFFCC10AA /* USB Transmit Hub Address */
3343#define USB_TXHUBADDR6 0xFFCC10B2 /* USB Transmit Hub Address */
3344#define USB_TXHUBADDR7 0xFFCC10BA /* USB Transmit Hub Address */
3345#define USB_TXHUBADDR8 0xFFCC10C2 /* USB Transmit Hub Address */
3346#define USB_TXHUBADDR9 0xFFCC10CA /* USB Transmit Hub Address */
3347#define USB_TXHUBADDR10 0xFFCC10D2 /* USB Transmit Hub Address */
3348#define USB_TXHUBADDR11 0xFFCC10DA /* USB Transmit Hub Address */
3349#define USB_TXHUBPORT0 0xFFCC1083 /* USB Transmit Hub Port */
3350#define USB_TXHUBPORT1 0xFFCC108B /* USB Transmit Hub Port */
3351#define USB_TXHUBPORT2 0xFFCC1093 /* USB Transmit Hub Port */
3352#define USB_TXHUBPORT3 0xFFCC109B /* USB Transmit Hub Port */
3353#define USB_TXHUBPORT4 0xFFCC10A3 /* USB Transmit Hub Port */
3354#define USB_TXHUBPORT5 0xFFCC10AB /* USB Transmit Hub Port */
3355#define USB_TXHUBPORT6 0xFFCC10B3 /* USB Transmit Hub Port */
3356#define USB_TXHUBPORT7 0xFFCC10BB /* USB Transmit Hub Port */
3357#define USB_TXHUBPORT8 0xFFCC10C3 /* USB Transmit Hub Port */
3358#define USB_TXHUBPORT9 0xFFCC10CB /* USB Transmit Hub Port */
3359#define USB_TXHUBPORT10 0xFFCC10D3 /* USB Transmit Hub Port */
3360#define USB_TXHUBPORT11 0xFFCC10DB /* USB Transmit Hub Port */
3361#define USB_RXFUNCADDR0 0xFFCC1084 /* USB Receive Function Address */
3362#define USB_RXFUNCADDR1 0xFFCC108C /* USB Receive Function Address */
3363#define USB_RXFUNCADDR2 0xFFCC1094 /* USB Receive Function Address */
3364#define USB_RXFUNCADDR3 0xFFCC109C /* USB Receive Function Address */
3365#define USB_RXFUNCADDR4 0xFFCC10A4 /* USB Receive Function Address */
3366#define USB_RXFUNCADDR5 0xFFCC10AC /* USB Receive Function Address */
3367#define USB_RXFUNCADDR6 0xFFCC10B4 /* USB Receive Function Address */
3368#define USB_RXFUNCADDR7 0xFFCC10BC /* USB Receive Function Address */
3369#define USB_RXFUNCADDR8 0xFFCC10C4 /* USB Receive Function Address */
3370#define USB_RXFUNCADDR9 0xFFCC10CC /* USB Receive Function Address */
3371#define USB_RXFUNCADDR10 0xFFCC10D4 /* USB Receive Function Address */
3372#define USB_RXFUNCADDR11 0xFFCC10DC /* USB Receive Function Address */
3373#define USB_RXHUBADDR0 0xFFCC1086 /* USB Receive Hub Address */
3374#define USB_RXHUBADDR1 0xFFCC108E /* USB Receive Hub Address */
3375#define USB_RXHUBADDR2 0xFFCC1096 /* USB Receive Hub Address */
3376#define USB_RXHUBADDR3 0xFFCC109E /* USB Receive Hub Address */
3377#define USB_RXHUBADDR4 0xFFCC10A6 /* USB Receive Hub Address */
3378#define USB_RXHUBADDR5 0xFFCC10AE /* USB Receive Hub Address */
3379#define USB_RXHUBADDR6 0xFFCC10B6 /* USB Receive Hub Address */
3380#define USB_RXHUBADDR7 0xFFCC10BE /* USB Receive Hub Address */
3381#define USB_RXHUBADDR8 0xFFCC10C6 /* USB Receive Hub Address */
3382#define USB_RXHUBADDR9 0xFFCC10CE /* USB Receive Hub Address */
3383#define USB_RXHUBADDR10 0xFFCC10D6 /* USB Receive Hub Address */
3384#define USB_RXHUBADDR11 0xFFCC10DE /* USB Receive Hub Address */
3385#define USB_RXHUBPORT0 0xFFCC1087 /* USB Receive Hub Port */
3386#define USB_RXHUBPORT1 0xFFCC108F /* USB Receive Hub Port */
3387#define USB_RXHUBPORT2 0xFFCC1097 /* USB Receive Hub Port */
3388#define USB_RXHUBPORT3 0xFFCC109F /* USB Receive Hub Port */
3389#define USB_RXHUBPORT4 0xFFCC10A7 /* USB Receive Hub Port */
3390#define USB_RXHUBPORT5 0xFFCC10AF /* USB Receive Hub Port */
3391#define USB_RXHUBPORT6 0xFFCC10B7 /* USB Receive Hub Port */
3392#define USB_RXHUBPORT7 0xFFCC10BF /* USB Receive Hub Port */
3393#define USB_RXHUBPORT8 0xFFCC10C7 /* USB Receive Hub Port */
3394#define USB_RXHUBPORT9 0xFFCC10CF /* USB Receive Hub Port */
3395#define USB_RXHUBPORT10 0xFFCC10D7 /* USB Receive Hub Port */
3396#define USB_RXHUBPORT11 0xFFCC10DF /* USB Receive Hub Port */
3397#define USB_EP0_CSR0_H 0xFFCC1102 /* USB Config and Status EP0 */
3398#define USB_EP0_CSR0_P 0xFFCC1102 /* USB Config and Status EP0 */
3399#define USB_EP0_CNT0 0xFFCC1108 /* USB Number of Received Bytes for Endpoint 0 */
3400#define USB_EP0_TYPE0 0xFFCC110A /* USB Speed for Endpoint 0 */
3401#define USB_EP0_NAKLIMIT0 0xFFCC110B /* USB NAK Response Timeout for Endpoint 0 */
3402#define USB_EP0_CFGDATA0 0xFFCC110F /* USB Configuration Information */
3403#define USB_EP_TXMAXP0 0xFFCC1110 /* USB Transmit Maximum Packet Length */
3404#define USB_EP_TXMAXP1 0xFFCC1120 /* USB Transmit Maximum Packet Length */
3405#define USB_EP_TXMAXP2 0xFFCC1130 /* USB Transmit Maximum Packet Length */
3406#define USB_EP_TXMAXP3 0xFFCC1140 /* USB Transmit Maximum Packet Length */
3407#define USB_EP_TXMAXP4 0xFFCC1150 /* USB Transmit Maximum Packet Length */
3408#define USB_EP_TXMAXP5 0xFFCC1160 /* USB Transmit Maximum Packet Length */
3409#define USB_EP_TXMAXP6 0xFFCC1170 /* USB Transmit Maximum Packet Length */
3410#define USB_EP_TXMAXP7 0xFFCC1180 /* USB Transmit Maximum Packet Length */
3411#define USB_EP_TXMAXP8 0xFFCC1190 /* USB Transmit Maximum Packet Length */
3412#define USB_EP_TXMAXP9 0xFFCC11A0 /* USB Transmit Maximum Packet Length */
3413#define USB_EP_TXMAXP10 0xFFCC11B0 /* USB Transmit Maximum Packet Length */
3414#define USB_EP_TXCSR0_H 0xFFCC1112 /* USB Transmit Configuration and Status */
3415#define USB_EP_TXCSR1_H 0xFFCC1122 /* USB Transmit Configuration and Status */
3416#define USB_EP_TXCSR2_H 0xFFCC1132 /* USB Transmit Configuration and Status */
3417#define USB_EP_TXCSR3_H 0xFFCC1142 /* USB Transmit Configuration and Status */
3418#define USB_EP_TXCSR4_H 0xFFCC1152 /* USB Transmit Configuration and Status */
3419#define USB_EP_TXCSR5_H 0xFFCC1162 /* USB Transmit Configuration and Status */
3420#define USB_EP_TXCSR6_H 0xFFCC1172 /* USB Transmit Configuration and Status */
3421#define USB_EP_TXCSR7_H 0xFFCC1182 /* USB Transmit Configuration and Status */
3422#define USB_EP_TXCSR8_H 0xFFCC1192 /* USB Transmit Configuration and Status */
3423#define USB_EP_TXCSR9_H 0xFFCC11A2 /* USB Transmit Configuration and Status */
3424#define USB_EP_TXCSR10_H 0xFFCC11B2 /* USB Transmit Configuration and Status */
3425#define USB_EP_TXCSR0_P 0xFFCC1112 /* USB Transmit Configuration and Status */
3426#define USB_EP_TXCSR1_P 0xFFCC1122 /* USB Transmit Configuration and Status */
3427#define USB_EP_TXCSR2_P 0xFFCC1132 /* USB Transmit Configuration and Status */
3428#define USB_EP_TXCSR3_P 0xFFCC1142 /* USB Transmit Configuration and Status */
3429#define USB_EP_TXCSR4_P 0xFFCC1152 /* USB Transmit Configuration and Status */
3430#define USB_EP_TXCSR5_P 0xFFCC1162 /* USB Transmit Configuration and Status */
3431#define USB_EP_TXCSR6_P 0xFFCC1172 /* USB Transmit Configuration and Status */
3432#define USB_EP_TXCSR7_P 0xFFCC1182 /* USB Transmit Configuration and Status */
3433#define USB_EP_TXCSR8_P 0xFFCC1192 /* USB Transmit Configuration and Status */
3434#define USB_EP_TXCSR9_P 0xFFCC11A2 /* USB Transmit Configuration and Status */
3435#define USB_EP_TXCSR10_P 0xFFCC11B2 /* USB Transmit Configuration and Status */
3436#define USB_EP_RXMAXP0 0xFFCC1114 /* USB Receive Maximum Packet Length */
3437#define USB_EP_RXMAXP1 0xFFCC1124 /* USB Receive Maximum Packet Length */
3438#define USB_EP_RXMAXP2 0xFFCC1134 /* USB Receive Maximum Packet Length */
3439#define USB_EP_RXMAXP3 0xFFCC1144 /* USB Receive Maximum Packet Length */
3440#define USB_EP_RXMAXP4 0xFFCC1154 /* USB Receive Maximum Packet Length */
3441#define USB_EP_RXMAXP5 0xFFCC1164 /* USB Receive Maximum Packet Length */
3442#define USB_EP_RXMAXP6 0xFFCC1174 /* USB Receive Maximum Packet Length */
3443#define USB_EP_RXMAXP7 0xFFCC1184 /* USB Receive Maximum Packet Length */
3444#define USB_EP_RXMAXP8 0xFFCC1194 /* USB Receive Maximum Packet Length */
3445#define USB_EP_RXMAXP9 0xFFCC11A4 /* USB Receive Maximum Packet Length */
3446#define USB_EP_RXMAXP10 0xFFCC11B4 /* USB Receive Maximum Packet Length */
3447#define USB_EP_RXCSR0_H 0xFFCC1116 /* USB Receive Configuration and Status Register */
3448#define USB_EP_RXCSR1_H 0xFFCC1126 /* USB Receive Configuration and Status Register */
3449#define USB_EP_RXCSR2_H 0xFFCC1136 /* USB Receive Configuration and Status Register */
3450#define USB_EP_RXCSR3_H 0xFFCC1146 /* USB Receive Configuration and Status Register */
3451#define USB_EP_RXCSR4_H 0xFFCC1156 /* USB Receive Configuration and Status Register */
3452#define USB_EP_RXCSR5_H 0xFFCC1166 /* USB Receive Configuration and Status Register */
3453#define USB_EP_RXCSR6_H 0xFFCC1176 /* USB Receive Configuration and Status Register */
3454#define USB_EP_RXCSR7_H 0xFFCC1186 /* USB Receive Configuration and Status Register */
3455#define USB_EP_RXCSR8_H 0xFFCC1196 /* USB Receive Configuration and Status Register */
3456#define USB_EP_RXCSR9_H 0xFFCC11A6 /* USB Receive Configuration and Status Register */
3457#define USB_EP_RXCSR10_H 0xFFCC11B6 /* USB Receive Configuration and Status Register */
3458#define USB_EP_RXCSR0_P 0xFFCC1116 /* USB Receive Configuration and Status Register */
3459#define USB_EP_RXCSR1_P 0xFFCC1126 /* USB Receive Configuration and Status Register */
3460#define USB_EP_RXCSR2_P 0xFFCC1136 /* USB Receive Configuration and Status Register */
3461#define USB_EP_RXCSR3_P 0xFFCC1146 /* USB Receive Configuration and Status Register */
3462#define USB_EP_RXCSR4_P 0xFFCC1156 /* USB Receive Configuration and Status Register */
3463#define USB_EP_RXCSR5_P 0xFFCC1166 /* USB Receive Configuration and Status Register */
3464#define USB_EP_RXCSR6_P 0xFFCC1176 /* USB Receive Configuration and Status Register */
3465#define USB_EP_RXCSR7_P 0xFFCC1186 /* USB Receive Configuration and Status Register */
3466#define USB_EP_RXCSR8_P 0xFFCC1196 /* USB Receive Configuration and Status Register */
3467#define USB_EP_RXCSR9_P 0xFFCC11A6 /* USB Receive Configuration and Status Register */
3468#define USB_EP_RXCSR10_P 0xFFCC11B6 /* USB Receive Configuration and Status Register */
3469#define USB_EP_RXCNT0 0xFFCC1118 /* USB Number of Byte Received */
3470#define USB_EP_RXCNT1 0xFFCC1128 /* USB Number of Byte Received */
3471#define USB_EP_RXCNT2 0xFFCC1138 /* USB Number of Byte Received */
3472#define USB_EP_RXCNT3 0xFFCC1148 /* USB Number of Byte Received */
3473#define USB_EP_RXCNT4 0xFFCC1158 /* USB Number of Byte Received */
3474#define USB_EP_RXCNT5 0xFFCC1168 /* USB Number of Byte Received */
3475#define USB_EP_RXCNT6 0xFFCC1178 /* USB Number of Byte Received */
3476#define USB_EP_RXCNT7 0xFFCC1188 /* USB Number of Byte Received */
3477#define USB_EP_RXCNT8 0xFFCC1198 /* USB Number of Byte Received */
3478#define USB_EP_RXCNT9 0xFFCC11A8 /* USB Number of Byte Received */
3479#define USB_EP_RXCNT10 0xFFCC11B8 /* USB Number of Byte Received */
3480#define USB_EP_TXTYPE0 0xFFCC111A /* USB Transmit Type */
3481#define USB_EP_TXTYPE1 0xFFCC112A /* USB Transmit Type */
3482#define USB_EP_TXTYPE2 0xFFCC113A /* USB Transmit Type */
3483#define USB_EP_TXTYPE3 0xFFCC114A /* USB Transmit Type */
3484#define USB_EP_TXTYPE4 0xFFCC115A /* USB Transmit Type */
3485#define USB_EP_TXTYPE5 0xFFCC116A /* USB Transmit Type */
3486#define USB_EP_TXTYPE6 0xFFCC117A /* USB Transmit Type */
3487#define USB_EP_TXTYPE7 0xFFCC118A /* USB Transmit Type */
3488#define USB_EP_TXTYPE8 0xFFCC119A /* USB Transmit Type */
3489#define USB_EP_TXTYPE9 0xFFCC11AA /* USB Transmit Type */
3490#define USB_EP_TXTYPE10 0xFFCC11BA /* USB Transmit Type */
3491#define USB_EP_TXINTERVAL0 0xFFCC111B /* USB Transmit Polling Interval */
3492#define USB_EP_TXINTERVAL1 0xFFCC112B /* USB Transmit Polling Interval */
3493#define USB_EP_TXINTERVAL2 0xFFCC113B /* USB Transmit Polling Interval */
3494#define USB_EP_TXINTERVAL3 0xFFCC114B /* USB Transmit Polling Interval */
3495#define USB_EP_TXINTERVAL4 0xFFCC115B /* USB Transmit Polling Interval */
3496#define USB_EP_TXINTERVAL5 0xFFCC116B /* USB Transmit Polling Interval */
3497#define USB_EP_TXINTERVAL6 0xFFCC117B /* USB Transmit Polling Interval */
3498#define USB_EP_TXINTERVAL7 0xFFCC118B /* USB Transmit Polling Interval */
3499#define USB_EP_TXINTERVAL8 0xFFCC119B /* USB Transmit Polling Interval */
3500#define USB_EP_TXINTERVAL9 0xFFCC11AB /* USB Transmit Polling Interval */
3501#define USB_EP_TXINTERVAL10 0xFFCC11BB /* USB Transmit Polling Interval */
3502#define USB_EP_RXTYPE0 0xFFCC111C /* USB Receive Type */
3503#define USB_EP_RXTYPE1 0xFFCC112C /* USB Receive Type */
3504#define USB_EP_RXTYPE2 0xFFCC113C /* USB Receive Type */
3505#define USB_EP_RXTYPE3 0xFFCC114C /* USB Receive Type */
3506#define USB_EP_RXTYPE4 0xFFCC115C /* USB Receive Type */
3507#define USB_EP_RXTYPE5 0xFFCC116C /* USB Receive Type */
3508#define USB_EP_RXTYPE6 0xFFCC117C /* USB Receive Type */
3509#define USB_EP_RXTYPE7 0xFFCC118C /* USB Receive Type */
3510#define USB_EP_RXTYPE8 0xFFCC119C /* USB Receive Type */
3511#define USB_EP_RXTYPE9 0xFFCC11AC /* USB Receive Type */
3512#define USB_EP_RXTYPE10 0xFFCC11BC /* USB Receive Type */
3513#define USB_EP_RXINTERVAL0 0xFFCC111D /* USB Receive Polling Interval */
3514#define USB_EP_RXINTERVAL1 0xFFCC112D /* USB Receive Polling Interval */
3515#define USB_EP_RXINTERVAL2 0xFFCC113D /* USB Receive Polling Interval */
3516#define USB_EP_RXINTERVAL3 0xFFCC114D /* USB Receive Polling Interval */
3517#define USB_EP_RXINTERVAL4 0xFFCC115D /* USB Receive Polling Interval */
3518#define USB_EP_RXINTERVAL5 0xFFCC116D /* USB Receive Polling Interval */
3519#define USB_EP_RXINTERVAL6 0xFFCC117D /* USB Receive Polling Interval */
3520#define USB_EP_RXINTERVAL7 0xFFCC118D /* USB Receive Polling Interval */
3521#define USB_EP_RXINTERVAL8 0xFFCC119D /* USB Receive Polling Interval */
3522#define USB_EP_RXINTERVAL9 0xFFCC11AD /* USB Receive Polling Interval */
3523#define USB_EP_RXINTERVAL10 0xFFCC11BD /* USB Receive Polling Interval */
3524#define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */
3525#define USB_DMA_CTL0 0xFFCC1204 /* USB DMA Control */
3526#define USB_DMA_CTL1 0xFFCC1214 /* USB DMA Control */
3527#define USB_DMA_CTL2 0xFFCC1224 /* USB DMA Control */
3528#define USB_DMA_CTL3 0xFFCC1234 /* USB DMA Control */
3529#define USB_DMA_CTL4 0xFFCC1244 /* USB DMA Control */
3530#define USB_DMA_CTL5 0xFFCC1254 /* USB DMA Control */
3531#define USB_DMA_CTL6 0xFFCC1264 /* USB DMA Control */
3532#define USB_DMA_CTL7 0xFFCC1274 /* USB DMA Control */
3533#define USB_DMA_ADDR0 0xFFCC1208 /* USB DMA Address */
3534#define USB_DMA_ADDR1 0xFFCC1218 /* USB DMA Address */
3535#define USB_DMA_ADDR2 0xFFCC1228 /* USB DMA Address */
3536#define USB_DMA_ADDR3 0xFFCC1238 /* USB DMA Address */
3537#define USB_DMA_ADDR4 0xFFCC1248 /* USB DMA Address */
3538#define USB_DMA_ADDR5 0xFFCC1258 /* USB DMA Address */
3539#define USB_DMA_ADDR6 0xFFCC1268 /* USB DMA Address */
3540#define USB_DMA_ADDR7 0xFFCC1278 /* USB DMA Address */
3541#define USB_DMA_CNT0 0xFFCC120C /* USB DMA Count */
3542#define USB_DMA_CNT1 0xFFCC121C /* USB DMA Count */
3543#define USB_DMA_CNT2 0xFFCC122C /* USB DMA Count */
3544#define USB_DMA_CNT3 0xFFCC123C /* USB DMA Count */
3545#define USB_DMA_CNT4 0xFFCC124C /* USB DMA Count */
3546#define USB_DMA_CNT5 0xFFCC125C /* USB DMA Count */
3547#define USB_DMA_CNT6 0xFFCC126C /* USB DMA Count */
3548#define USB_DMA_CNT7 0xFFCC127C /* USB DMA Count */
3549#define USB_RQPKTCNT0 0xFFCC1300 /* USB Request Packet Count */
3550#define USB_RQPKTCNT1 0xFFCC1304 /* USB Request Packet Count */
3551#define USB_RQPKTCNT2 0xFFCC1308 /* USB Request Packet Count */
3552#define USB_RQPKTCNT3 0xFFCC130C /* USB Request Packet Count */
3553#define USB_RQPKTCNT4 0xFFCC1310 /* USB Request Packet Count */
3554#define USB_RQPKTCNT5 0xFFCC1314 /* USB Request Packet Count */
3555#define USB_RQPKTCNT6 0xFFCC1318 /* USB Request Packet Count */
3556#define USB_RQPKTCNT7 0xFFCC131C /* USB Request Packet Count */
3557#define USB_RQPKTCNT8 0xFFCC1320 /* USB Request Packet Count */
3558#define USB_RQPKTCNT9 0xFFCC1324 /* USB Request Packet Count */
3559#define USB_RQPKTCNT10 0xFFCC1328 /* USB Request Packet Count */
3560#define USB_CT_UCH 0xFFCC1344 /* USB Chirp Timeout */
3561#define USB_CT_HHSRTN 0xFFCC1346 /* USB High Speed Resume Return to Normal */
3562#define USB_CT_HSBT 0xFFCC1348 /* USB High Speed Timeout */
3563#define USB_LPM_ATTR 0xFFCC1360 /* USB LPM Attribute */
3564#define USB_LPM_CTL 0xFFCC1362 /* USB LPM Control */
3565#define USB_LPM_IEN 0xFFCC1363 /* USB LPM Interrupt Enable */
3566#define USB_LPM_IRQ 0xFFCC1364 /* USB LPM Interrupt */
3567#define USB_LPM_FADDR 0xFFCC1365 /* USB LPM Function Address */
3568#define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */
3569#define USB_BAT_CHG 0xFFCC1381 /* USB Battery Charging */
3570#define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */
3571#define USB_TESTCTL 0xFFCC1397 /* USB Test Control */
3572#define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */
3573
3574
3575
3576/* =========================
3577 CHIPID
3578 ========================= */
3579
3580#define CHIPID 0xffc00014
3581/* CHIPID Masks */
3582#define CHIPID_VERSION 0xF0000000
3583#define CHIPID_FAMILY 0x0FFFF000
3584#define CHIPID_MANUFACTURE 0x00000FFE
3585
3586
3587#endif /* _DEF_BF60X_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/dma.h b/arch/blackfin/mach-bf609/include/mach/dma.h
new file mode 100644
index 000000000000..872d141ca119
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/dma.h
@@ -0,0 +1,116 @@
1/* mach/dma.h - arch-specific DMA defines
2 *
3 * Copyright 2011 Analog Devices Inc.
4 *
5 * Licensed under the GPL-2 or later.
6 */
7
8#ifndef _MACH_DMA_H_
9#define _MACH_DMA_H_
10
11#define CH_SPORT0_TX 0
12#define CH_SPORT0_RX 1
13#define CH_SPORT1_TX 2
14#define CH_SPORT1_RX 3
15#define CH_SPORT2_TX 4
16#define CH_SPORT2_RX 5
17#define CH_SPI0_TX 6
18#define CH_SPI0_RX 7
19#define CH_SPI1_TX 8
20#define CH_SPI1_RX 9
21#define CH_RSI 10
22#define CH_SDU 11
23#define CH_LP0 13
24#define CH_LP1 14
25#define CH_LP2 15
26#define CH_LP3 16
27#define CH_UART0_TX 17
28#define CH_UART0_RX 18
29#define CH_UART1_TX 19
30#define CH_UART1_RX 20
31#define CH_MEM_STREAM0_SRC_CRC0 21
32#define CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0
33#define CH_MEM_STREAM0_DEST_CRC0 22
34#define CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0
35#define CH_MEM_STREAM1_SRC_CRC1 23
36#define CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1
37#define CH_MEM_STREAM1_DEST_CRC1 24
38#define CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1
39#define CH_MEM_STREAM2_SRC 25
40#define CH_MEM_STREAM2_DEST 26
41#define CH_MEM_STREAM3_SRC 27
42#define CH_MEM_STREAM3_DEST 28
43#define CH_EPPI0_CH0 29
44#define CH_EPPI0_CH1 30
45#define CH_EPPI1_CH0 31
46#define CH_EPPI1_CH1 32
47#define CH_EPPI2_CH0 33
48#define CH_EPPI2_CH1 34
49#define CH_PIXC_CH0 35
50#define CH_PIXC_CH1 36
51#define CH_PIXC_CH2 37
52#define CH_PVP_CPDOB 38
53#define CH_PVP_CPDOC 39
54#define CH_PVP_CPSTAT 40
55#define CH_PVP_CPCI 41
56#define CH_PVP_MPDO 42
57#define CH_PVP_MPDI 43
58#define CH_PVP_MPSTAT 44
59#define CH_PVP_MPCI 45
60#define CH_PVP_CPDOA 46
61
62#define MAX_DMA_CHANNELS 47
63#define MAX_DMA_SUSPEND_CHANNELS 0
64#define DMA_MMR_SIZE_32
65
66#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG
67#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG
68#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS
69#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS
70#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR
71#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT
72#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY
73#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT
74#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY
75#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG
76#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG
77#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS
78#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS
79#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR
80#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT
81#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY
82#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT
83#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY
84
85#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG
86#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG
87#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG
88#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG
89#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS
90#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS
91
92#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG
93#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG
94#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS
95#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS
96#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR
97#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT
98#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY
99#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT
100#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY
101#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG
102#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG
103#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS
104#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS
105#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR
106#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT
107#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY
108#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT
109#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY
110
111#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR
112#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR
113#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR
114#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR
115
116#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
new file mode 100644
index 000000000000..127586b1e04a
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/gpio.h
@@ -0,0 +1,171 @@
1/*
2 * Copyright 2007-2009 Analog Devices Inc.
3 * Licensed under the GPL-2 or later.
4 */
5
6#ifndef _MACH_GPIO_H_
7#define _MACH_GPIO_H_
8
9#define MAX_BLACKFIN_GPIOS 112
10
11#define GPIO_PA0 0
12#define GPIO_PA1 1
13#define GPIO_PA2 2
14#define GPIO_PA3 3
15#define GPIO_PA4 4
16#define GPIO_PA5 5
17#define GPIO_PA6 6
18#define GPIO_PA7 7
19#define GPIO_PA8 8
20#define GPIO_PA9 9
21#define GPIO_PA10 10
22#define GPIO_PA11 11
23#define GPIO_PA12 12
24#define GPIO_PA13 13
25#define GPIO_PA14 14
26#define GPIO_PA15 15
27#define GPIO_PB0 16
28#define GPIO_PB1 17
29#define GPIO_PB2 18
30#define GPIO_PB3 19
31#define GPIO_PB4 20
32#define GPIO_PB5 21
33#define GPIO_PB6 22
34#define GPIO_PB7 23
35#define GPIO_PB8 24
36#define GPIO_PB9 25
37#define GPIO_PB10 26
38#define GPIO_PB11 27
39#define GPIO_PB12 28
40#define GPIO_PB13 29
41#define GPIO_PB14 30
42#define GPIO_PB15 31
43#define GPIO_PC0 32
44#define GPIO_PC1 33
45#define GPIO_PC2 34
46#define GPIO_PC3 35
47#define GPIO_PC4 36
48#define GPIO_PC5 37
49#define GPIO_PC6 38
50#define GPIO_PC7 39
51#define GPIO_PC8 40
52#define GPIO_PC9 41
53#define GPIO_PC10 42
54#define GPIO_PC11 43
55#define GPIO_PC12 44
56#define GPIO_PC13 45
57#define GPIO_PC14 46
58#define GPIO_PC15 47
59#define GPIO_PD0 48
60#define GPIO_PD1 49
61#define GPIO_PD2 50
62#define GPIO_PD3 51
63#define GPIO_PD4 52
64#define GPIO_PD5 53
65#define GPIO_PD6 54
66#define GPIO_PD7 55
67#define GPIO_PD8 56
68#define GPIO_PD9 57
69#define GPIO_PD10 58
70#define GPIO_PD11 59
71#define GPIO_PD12 60
72#define GPIO_PD13 61
73#define GPIO_PD14 62
74#define GPIO_PD15 63
75#define GPIO_PE0 64
76#define GPIO_PE1 65
77#define GPIO_PE2 66
78#define GPIO_PE3 67
79#define GPIO_PE4 68
80#define GPIO_PE5 69
81#define GPIO_PE6 70
82#define GPIO_PE7 71
83#define GPIO_PE8 72
84#define GPIO_PE9 73
85#define GPIO_PE10 74
86#define GPIO_PE11 75
87#define GPIO_PE12 76
88#define GPIO_PE13 77
89#define GPIO_PE14 78
90#define GPIO_PE15 79
91#define GPIO_PF0 80
92#define GPIO_PF1 81
93#define GPIO_PF2 82
94#define GPIO_PF3 83
95#define GPIO_PF4 84
96#define GPIO_PF5 85
97#define GPIO_PF6 86
98#define GPIO_PF7 87
99#define GPIO_PF8 88
100#define GPIO_PF9 89
101#define GPIO_PF10 90
102#define GPIO_PF11 91
103#define GPIO_PF12 92
104#define GPIO_PF13 93
105#define GPIO_PF14 94
106#define GPIO_PF15 95
107#define GPIO_PG0 96
108#define GPIO_PG1 97
109#define GPIO_PG2 98
110#define GPIO_PG3 99
111#define GPIO_PG4 100
112#define GPIO_PG5 101
113#define GPIO_PG6 102
114#define GPIO_PG7 103
115#define GPIO_PG8 104
116#define GPIO_PG9 105
117#define GPIO_PG10 106
118#define GPIO_PG11 107
119#define GPIO_PG12 108
120#define GPIO_PG13 109
121#define GPIO_PG14 110
122#define GPIO_PG15 111
123
124
125#define BFIN_GPIO_PINT 1
126
127
128#ifndef __ASSEMBLY__
129
130struct gpio_port_t {
131 unsigned long port_fer;
132 unsigned long port_fer_set;
133 unsigned long port_fer_clear;
134 unsigned long data;
135 unsigned long data_set;
136 unsigned long data_clear;
137 unsigned long dir;
138 unsigned long dir_set;
139 unsigned long dir_clear;
140 unsigned long inen;
141 unsigned long inen_set;
142 unsigned long inen_clear;
143 unsigned long port_mux;
144 unsigned long toggle;
145 unsigned long polar;
146 unsigned long polar_set;
147 unsigned long polar_clear;
148 unsigned long lock;
149 unsigned long spare;
150 unsigned long revid;
151};
152
153struct gpio_port_s {
154 unsigned short fer;
155 unsigned short data;
156 unsigned short dir;
157 unsigned short inen;
158 unsigned int mux;
159};
160
161#endif
162
163#include <mach-common/ports-a.h>
164#include <mach-common/ports-b.h>
165#include <mach-common/ports-c.h>
166#include <mach-common/ports-d.h>
167#include <mach-common/ports-e.h>
168#include <mach-common/ports-f.h>
169#include <mach-common/ports-g.h>
170
171#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
new file mode 100644
index 000000000000..0004552433b2
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/irq.h
@@ -0,0 +1,318 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _BF60x_IRQ_H_
8#define _BF60x_IRQ_H_
9
10#include <mach-common/irq.h>
11
12#undef BFIN_IRQ
13#define BFIN_IRQ(x) ((x) + IVG15)
14
15#define NR_PERI_INTS (5 * 32)
16
17#define IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */
18#define IRQ_CGU_EVT BFIN_IRQ(1) /* CGU Event */
19#define IRQ_WATCH0 BFIN_IRQ(2) /* Watchdog0 Interrupt */
20#define IRQ_WATCH1 BFIN_IRQ(3) /* Watchdog1 Interrupt */
21#define IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */
22#define IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */
23#define IRQ_C0_DBL_FAULT BFIN_IRQ(6) /* Core 0 Double Fault */
24#define IRQ_C1_DBL_FAULT BFIN_IRQ(7) /* Core 1 Double Fault */
25#define IRQ_C0_HW_ERR BFIN_IRQ(8) /* Core 0 Hardware Error */
26#define IRQ_C1_HW_ERR BFIN_IRQ(9) /* Core 1 Hardware Error */
27#define IRQ_C0_NMI_L1_PARITY_ERR BFIN_IRQ(10) /* Core 0 Unhandled NMI or L1 Memory Parity Error */
28#define IRQ_C1_NMI_L1_PARITY_ERR BFIN_IRQ(11) /* Core 1 Unhandled NMI or L1 Memory Parity Error */
29#define CORE_IRQS (IRQ_C1_NMI_L1_PARITY_ERR + 1)
30
31#define IRQ_TIMER0 BFIN_IRQ(12) /* Timer 0 Interrupt */
32#define IRQ_TIMER1 BFIN_IRQ(13) /* Timer 1 Interrupt */
33#define IRQ_TIMER2 BFIN_IRQ(14) /* Timer 2 Interrupt */
34#define IRQ_TIMER3 BFIN_IRQ(15) /* Timer 3 Interrupt */
35#define IRQ_TIMER4 BFIN_IRQ(16) /* Timer 4 Interrupt */
36#define IRQ_TIMER5 BFIN_IRQ(17) /* Timer 5 Interrupt */
37#define IRQ_TIMER6 BFIN_IRQ(18) /* Timer 6 Interrupt */
38#define IRQ_TIMER7 BFIN_IRQ(19) /* Timer 7 Interrupt */
39#define IRQ_TIMER_STAT BFIN_IRQ(20) /* Timer Block Status */
40#define IRQ_PINT0 BFIN_IRQ(21) /* PINT0 Interrupt */
41#define IRQ_PINT1 BFIN_IRQ(22) /* PINT1 Interrupt */
42#define IRQ_PINT2 BFIN_IRQ(23) /* PINT2 Interrupt */
43#define IRQ_PINT3 BFIN_IRQ(24) /* PINT3 Interrupt */
44#define IRQ_PINT4 BFIN_IRQ(25) /* PINT4 Interrupt */
45#define IRQ_PINT5 BFIN_IRQ(26) /* PINT5 Interrupt */
46#define IRQ_CNT BFIN_IRQ(27) /* CNT Interrupt */
47#define IRQ_PWM0_TRIP BFIN_IRQ(28) /* PWM0 Trip Interrupt */
48#define IRQ_PWM0_SYNC BFIN_IRQ(29) /* PWM0 Sync Interrupt */
49#define IRQ_PWM1_TRIP BFIN_IRQ(30) /* PWM1 Trip Interrupt */
50#define IRQ_PWM1_SYNC BFIN_IRQ(31) /* PWM1 Sync Interrupt */
51#define IRQ_TWI0 BFIN_IRQ(32) /* TWI0 Interrupt */
52#define IRQ_TWI1 BFIN_IRQ(33) /* TWI1 Interrupt */
53#define IRQ_SOFT0 BFIN_IRQ(34) /* Software-Driven Interrupt 0 */
54#define IRQ_SOFT1 BFIN_IRQ(35) /* Software-Driven Interrupt 1 */
55#define IRQ_SOFT2 BFIN_IRQ(36) /* Software-Driven Interrupt 2 */
56#define IRQ_SOFT3 BFIN_IRQ(37) /* Software-Driven Interrupt 3 */
57#define IRQ_ACM_EVT_MISS BFIN_IRQ(38) /* ACM Event Miss */
58#define IRQ_ACM_EVT_COMPLETE BFIN_IRQ(39) /* ACM Event Complete */
59#define IRQ_CAN0_RX BFIN_IRQ(40) /* CAN0 Receive Interrupt */
60#define IRQ_CAN0_TX BFIN_IRQ(41) /* CAN0 Transmit Interrupt */
61#define IRQ_CAN0_STAT BFIN_IRQ(42) /* CAN0 Status */
62#define IRQ_SPORT0_TX BFIN_IRQ(43) /* SPORT0 TX Interrupt (DMA0) */
63#define IRQ_SPORT0_TX_STAT BFIN_IRQ(44) /* SPORT0 TX Status Interrupt */
64#define IRQ_SPORT0_RX BFIN_IRQ(45) /* SPORT0 RX Interrupt (DMA1) */
65#define IRQ_SPORT0_RX_STAT BFIN_IRQ(46) /* SPORT0 RX Status Interrupt */
66#define IRQ_SPORT1_TX BFIN_IRQ(47) /* SPORT1 TX Interrupt (DMA2) */
67#define IRQ_SPORT1_TX_STAT BFIN_IRQ(48) /* SPORT1 TX Status Interrupt */
68#define IRQ_SPORT1_RX BFIN_IRQ(49) /* SPORT1 RX Interrupt (DMA3) */
69#define IRQ_SPORT1_RX_STAT BFIN_IRQ(50) /* SPORT1 RX Status Interrupt */
70#define IRQ_SPORT2_TX BFIN_IRQ(51) /* SPORT2 TX Interrupt (DMA4) */
71#define IRQ_SPORT2_TX_STAT BFIN_IRQ(52) /* SPORT2 TX Status Interrupt */
72#define IRQ_SPORT2_RX BFIN_IRQ(53) /* SPORT2 RX Interrupt (DMA5) */
73#define IRQ_SPORT2_RX_STAT BFIN_IRQ(54) /* SPORT2 RX Status Interrupt */
74#define IRQ_SPI0_TX BFIN_IRQ(55) /* SPI0 TX Interrupt (DMA6) */
75#define IRQ_SPI0_RX BFIN_IRQ(56) /* SPI0 RX Interrupt (DMA7) */
76#define IRQ_SPI0_STAT BFIN_IRQ(57) /* SPI0 Status Interrupt */
77#define IRQ_SPI1_TX BFIN_IRQ(58) /* SPI1 TX Interrupt (DMA8) */
78#define IRQ_SPI1_RX BFIN_IRQ(59) /* SPI1 RX Interrupt (DMA9) */
79#define IRQ_SPI1_STAT BFIN_IRQ(60) /* SPI1 Status Interrupt */
80#define IRQ_RSI BFIN_IRQ(61) /* RSI (DMA10) Interrupt */
81#define IRQ_RSI_INT0 BFIN_IRQ(62) /* RSI Interrupt0 */
82#define IRQ_RSI_INT1 BFIN_IRQ(63) /* RSI Interrupt1 */
83#define IRQ_SDU BFIN_IRQ(64) /* DMA11 Data (SDU) */
84/* -- RESERVED -- 65 DMA12 Data (Reserved) */
85/* -- RESERVED -- 66 Reserved */
86/* -- RESERVED -- 67 Reserved */
87#define IRQ_EMAC0_STAT BFIN_IRQ(68) /* EMAC0 Status */
88/* -- RESERVED -- 69 EMAC0 Power (Reserved) */
89#define IRQ_EMAC1_STAT BFIN_IRQ(70) /* EMAC1 Status */
90/* -- RESERVED -- 71 EMAC1 Power (Reserved) */
91#define IRQ_LP0 BFIN_IRQ(72) /* DMA13 Data (Link Port 0) */
92#define IRQ_LP0_STAT BFIN_IRQ(73) /* Link Port 0 Status */
93#define IRQ_LP1 BFIN_IRQ(74) /* DMA14 Data (Link Port 1) */
94#define IRQ_LP1_STAT BFIN_IRQ(75) /* Link Port 1 Status */
95#define IRQ_LP2 BFIN_IRQ(76) /* DMA15 Data (Link Port 2) */
96#define IRQ_LP2_STAT BFIN_IRQ(77) /* Link Port 2 Status */
97#define IRQ_LP3 BFIN_IRQ(78) /* DMA16 Data(Link Port 3) */
98#define IRQ_LP3_STAT BFIN_IRQ(79) /* Link Port 3 Status */
99#define IRQ_UART0_TX BFIN_IRQ(80) /* UART0 TX Interrupt (DMA17) */
100#define IRQ_UART0_RX BFIN_IRQ(81) /* UART0 RX Interrupt (DMA18) */
101#define IRQ_UART0_STAT BFIN_IRQ(82) /* UART0 Status(Error) Interrupt */
102#define IRQ_UART1_TX BFIN_IRQ(83) /* UART1 TX Interrupt (DMA19) */
103#define IRQ_UART1_RX BFIN_IRQ(84) /* UART1 RX Interrupt (DMA20) */
104#define IRQ_UART1_STAT BFIN_IRQ(85) /* UART1 Status(Error) Interrupt */
105#define IRQ_MDMA0_SRC_CRC0 BFIN_IRQ(86) /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */
106#define IRQ_MDMA0_DEST_CRC0 BFIN_IRQ(87) /* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */
107#define IRQ_MDMAS0 IRQ_MDMA0_DEST_CRC0
108#define IRQ_CRC0_DCNTEXP BFIN_IRQ(88) /* CRC0 DATACOUNT Expiration */
109#define IRQ_CRC0_ERR BFIN_IRQ(89) /* CRC0 Error */
110#define IRQ_MDMA1_SRC_CRC1 BFIN_IRQ(90) /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */
111#define IRQ_MDMA1_DEST_CRC1 BFIN_IRQ(91) /* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */
112#define IRQ_MDMAS1 IRQ_MDMA1_DEST_CRC1
113#define IRQ_CRC1_DCNTEXP BFIN_IRQ(92) /* CRC1 DATACOUNT Expiration */
114#define IRQ_CRC1_ERR BFIN_IRQ(93) /* CRC1 Error */
115#define IRQ_MDMA2_SRC BFIN_IRQ(94) /* DMA25 Data (MDMA Stream 2 Source Channel) */
116#define IRQ_MDMA2_DEST BFIN_IRQ(95) /* DMA26 Data (MDMA Stream 2 Destination Channel) */
117#define IRQ_MDMAS2 IRQ_MDMA2_DEST
118#define IRQ_MDMA3_SRC BFIN_IRQ(96) /* DMA27 Data (MDMA Stream 3 Source Channel) */
119#define IRQ_MDMA3_DEST BFIN_IRQ(97) /* DMA28 Data (MDMA Stream 3 Destination Channel) */
120#define IRQ_MDMAS3 IRQ_MDMA3_DEST
121#define IRQ_EPPI0_CH0 BFIN_IRQ(98) /* DMA29 Data (EPPI0 Channel 0) */
122#define IRQ_EPPI0_CH1 BFIN_IRQ(99) /* DMA30 Data (EPPI0 Channel 1) */
123#define IRQ_EPPI0_STAT BFIN_IRQ(100) /* EPPI0 Status */
124#define IRQ_EPPI2_CH0 BFIN_IRQ(101) /* DMA31 Data (EPPI2 Channel 0) */
125#define IRQ_EPPI2_CH1 BFIN_IRQ(102) /* DMA32 Data (EPPI2 Channel 1) */
126#define IRQ_EPPI2_STAT BFIN_IRQ(103) /* EPPI2 Status */
127#define IRQ_EPPI1_CH0 BFIN_IRQ(104) /* DMA33 Data (EPPI1 Channel 0) */
128#define IRQ_EPPI1_CH1 BFIN_IRQ(105) /* DMA34 Data (EPPI1 Channel 1) */
129#define IRQ_EPPI1_STAT BFIN_IRQ(106) /* EPPI1 Status */
130#define IRQ_PIXC_CH0 BFIN_IRQ(107) /* DMA35 Data (PIXC Channel 0) */
131#define IRQ_PIXC_CH1 BFIN_IRQ(108) /* DMA36 Data (PIXC Channel 1) */
132#define IRQ_PIXC_CH2 BFIN_IRQ(109) /* DMA37 Data (PIXC Channel 2) */
133#define IRQ_PIXC_STAT BFIN_IRQ(110) /* PIXC Status */
134#define IRQ_PVP_CPDOB BFIN_IRQ(111) /* DMA38 Data (PVP0 Camera Pipe Data Out B) */
135#define IRQ_PVP_CPDOC BFIN_IRQ(112) /* DMA39 Data (PVP0 Camera Pipe Data Out C) */
136#define IRQ_PVP_CPSTAT BFIN_IRQ(113) /* DMA40 Data (PVP0 Camera Pipe Status Out) */
137#define IRQ_PVP_CPCI BFIN_IRQ(114) /* DMA41 Data (PVP0 Camera Pipe Control In) */
138#define IRQ_PVP_STAT0 BFIN_IRQ(115) /* PVP0 Status 0 */
139#define IRQ_PVP_MPDO BFIN_IRQ(116) /* DMA42 Data (PVP0 Memory Pipe Data Out) */
140#define IRQ_PVP_MPDI BFIN_IRQ(117) /* DMA43 Data (PVP0 Memory Pipe Data In) */
141#define IRQ_PVP_MPSTAT BFIN_IRQ(118) /* DMA44 Data (PVP0 Memory Pipe Status Out) */
142#define IRQ_PVP_MPCI BFIN_IRQ(119) /* DMA45 Data (PVP0 Memory Pipe Control In) */
143#define IRQ_PVP_CPDOA BFIN_IRQ(120) /* DMA46 Data (PVP0 Camera Pipe Data Out A) */
144#define IRQ_PVP_STAT1 BFIN_IRQ(121) /* PVP0 Status 1 */
145#define IRQ_USB_STAT BFIN_IRQ(122) /* USB Status Interrupt */
146#define IRQ_USB_DMA BFIN_IRQ(123) /* USB DMA Interrupt */
147#define IRQ_TRU_INT0 BFIN_IRQ(124) /* TRU0 Interrupt 0 */
148#define IRQ_TRU_INT1 BFIN_IRQ(125) /* TRU0 Interrupt 1 */
149#define IRQ_TRU_INT2 BFIN_IRQ(126) /* TRU0 Interrupt 2 */
150#define IRQ_TRU_INT3 BFIN_IRQ(127) /* TRU0 Interrupt 3 */
151#define IRQ_DMAC0_ERROR BFIN_IRQ(128) /* DMAC0 Status Interrupt */
152#define IRQ_CGU0_ERROR BFIN_IRQ(129) /* CGU0 Error */
153/* -- RESERVED -- 130 Reserved */
154#define IRQ_DPM BFIN_IRQ(131) /* DPM0 Event */
155/* -- RESERVED -- 132 Reserved */
156#define IRQ_SWU0 BFIN_IRQ(133) /* SWU0 */
157#define IRQ_SWU1 BFIN_IRQ(134) /* SWU1 */
158#define IRQ_SWU2 BFIN_IRQ(135) /* SWU2 */
159#define IRQ_SWU3 BFIN_IRQ(136) /* SWU3 */
160#define IRQ_SWU4 BFIN_IRQ(137) /* SWU4 */
161#define IRQ_SWU5 BFIN_IRQ(138) /* SWU5 */
162#define IRQ_SWU6 BFIN_IRQ(139) /* SWU6 */
163
164#define SYS_IRQS IRQ_SWU6
165
166#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
167#define IRQ_PA0 BFIN_PA_IRQ(0)
168#define IRQ_PA1 BFIN_PA_IRQ(1)
169#define IRQ_PA2 BFIN_PA_IRQ(2)
170#define IRQ_PA3 BFIN_PA_IRQ(3)
171#define IRQ_PA4 BFIN_PA_IRQ(4)
172#define IRQ_PA5 BFIN_PA_IRQ(5)
173#define IRQ_PA6 BFIN_PA_IRQ(6)
174#define IRQ_PA7 BFIN_PA_IRQ(7)
175#define IRQ_PA8 BFIN_PA_IRQ(8)
176#define IRQ_PA9 BFIN_PA_IRQ(9)
177#define IRQ_PA10 BFIN_PA_IRQ(10)
178#define IRQ_PA11 BFIN_PA_IRQ(11)
179#define IRQ_PA12 BFIN_PA_IRQ(12)
180#define IRQ_PA13 BFIN_PA_IRQ(13)
181#define IRQ_PA14 BFIN_PA_IRQ(14)
182#define IRQ_PA15 BFIN_PA_IRQ(15)
183
184#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
185#define IRQ_PB0 BFIN_PB_IRQ(0)
186#define IRQ_PB1 BFIN_PB_IRQ(1)
187#define IRQ_PB2 BFIN_PB_IRQ(2)
188#define IRQ_PB3 BFIN_PB_IRQ(3)
189#define IRQ_PB4 BFIN_PB_IRQ(4)
190#define IRQ_PB5 BFIN_PB_IRQ(5)
191#define IRQ_PB6 BFIN_PB_IRQ(6)
192#define IRQ_PB7 BFIN_PB_IRQ(7)
193#define IRQ_PB8 BFIN_PB_IRQ(8)
194#define IRQ_PB9 BFIN_PB_IRQ(9)
195#define IRQ_PB10 BFIN_PB_IRQ(10)
196#define IRQ_PB11 BFIN_PB_IRQ(11)
197#define IRQ_PB12 BFIN_PB_IRQ(12)
198#define IRQ_PB13 BFIN_PB_IRQ(13)
199#define IRQ_PB14 BFIN_PB_IRQ(14)
200#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
201
202#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
203#define IRQ_PC0 BFIN_PC_IRQ(0)
204#define IRQ_PC1 BFIN_PC_IRQ(1)
205#define IRQ_PC2 BFIN_PC_IRQ(2)
206#define IRQ_PC3 BFIN_PC_IRQ(3)
207#define IRQ_PC4 BFIN_PC_IRQ(4)
208#define IRQ_PC5 BFIN_PC_IRQ(5)
209#define IRQ_PC6 BFIN_PC_IRQ(6)
210#define IRQ_PC7 BFIN_PC_IRQ(7)
211#define IRQ_PC8 BFIN_PC_IRQ(8)
212#define IRQ_PC9 BFIN_PC_IRQ(9)
213#define IRQ_PC10 BFIN_PC_IRQ(10)
214#define IRQ_PC11 BFIN_PC_IRQ(11)
215#define IRQ_PC12 BFIN_PC_IRQ(12)
216#define IRQ_PC13 BFIN_PC_IRQ(13)
217#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
218#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
219
220#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
221#define IRQ_PD0 BFIN_PD_IRQ(0)
222#define IRQ_PD1 BFIN_PD_IRQ(1)
223#define IRQ_PD2 BFIN_PD_IRQ(2)
224#define IRQ_PD3 BFIN_PD_IRQ(3)
225#define IRQ_PD4 BFIN_PD_IRQ(4)
226#define IRQ_PD5 BFIN_PD_IRQ(5)
227#define IRQ_PD6 BFIN_PD_IRQ(6)
228#define IRQ_PD7 BFIN_PD_IRQ(7)
229#define IRQ_PD8 BFIN_PD_IRQ(8)
230#define IRQ_PD9 BFIN_PD_IRQ(9)
231#define IRQ_PD10 BFIN_PD_IRQ(10)
232#define IRQ_PD11 BFIN_PD_IRQ(11)
233#define IRQ_PD12 BFIN_PD_IRQ(12)
234#define IRQ_PD13 BFIN_PD_IRQ(13)
235#define IRQ_PD14 BFIN_PD_IRQ(14)
236#define IRQ_PD15 BFIN_PD_IRQ(15)
237
238#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
239#define IRQ_PE0 BFIN_PE_IRQ(0)
240#define IRQ_PE1 BFIN_PE_IRQ(1)
241#define IRQ_PE2 BFIN_PE_IRQ(2)
242#define IRQ_PE3 BFIN_PE_IRQ(3)
243#define IRQ_PE4 BFIN_PE_IRQ(4)
244#define IRQ_PE5 BFIN_PE_IRQ(5)
245#define IRQ_PE6 BFIN_PE_IRQ(6)
246#define IRQ_PE7 BFIN_PE_IRQ(7)
247#define IRQ_PE8 BFIN_PE_IRQ(8)
248#define IRQ_PE9 BFIN_PE_IRQ(9)
249#define IRQ_PE10 BFIN_PE_IRQ(10)
250#define IRQ_PE11 BFIN_PE_IRQ(11)
251#define IRQ_PE12 BFIN_PE_IRQ(12)
252#define IRQ_PE13 BFIN_PE_IRQ(13)
253#define IRQ_PE14 BFIN_PE_IRQ(14)
254#define IRQ_PE15 BFIN_PE_IRQ(15)
255
256#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
257#define IRQ_PF0 BFIN_PF_IRQ(0)
258#define IRQ_PF1 BFIN_PF_IRQ(1)
259#define IRQ_PF2 BFIN_PF_IRQ(2)
260#define IRQ_PF3 BFIN_PF_IRQ(3)
261#define IRQ_PF4 BFIN_PF_IRQ(4)
262#define IRQ_PF5 BFIN_PF_IRQ(5)
263#define IRQ_PF6 BFIN_PF_IRQ(6)
264#define IRQ_PF7 BFIN_PF_IRQ(7)
265#define IRQ_PF8 BFIN_PF_IRQ(8)
266#define IRQ_PF9 BFIN_PF_IRQ(9)
267#define IRQ_PF10 BFIN_PF_IRQ(10)
268#define IRQ_PF11 BFIN_PF_IRQ(11)
269#define IRQ_PF12 BFIN_PF_IRQ(12)
270#define IRQ_PF13 BFIN_PF_IRQ(13)
271#define IRQ_PF14 BFIN_PF_IRQ(14)
272#define IRQ_PF15 BFIN_PF_IRQ(15)
273
274#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
275#define IRQ_PG0 BFIN_PG_IRQ(0)
276#define IRQ_PG1 BFIN_PG_IRQ(1)
277#define IRQ_PG2 BFIN_PG_IRQ(2)
278#define IRQ_PG3 BFIN_PG_IRQ(3)
279#define IRQ_PG4 BFIN_PG_IRQ(4)
280#define IRQ_PG5 BFIN_PG_IRQ(5)
281#define IRQ_PG6 BFIN_PG_IRQ(6)
282#define IRQ_PG7 BFIN_PG_IRQ(7)
283#define IRQ_PG8 BFIN_PG_IRQ(8)
284#define IRQ_PG9 BFIN_PG_IRQ(9)
285#define IRQ_PG10 BFIN_PG_IRQ(10)
286#define IRQ_PG11 BFIN_PG_IRQ(11)
287#define IRQ_PG12 BFIN_PG_IRQ(12)
288#define IRQ_PG13 BFIN_PG_IRQ(13)
289#define IRQ_PG14 BFIN_PG_IRQ(14)
290#define IRQ_PG15 BFIN_PG_IRQ(15)
291
292#define GPIO_IRQ_BASE IRQ_PA0
293
294#define NR_MACH_IRQS (IRQ_PG15 + 1)
295
296#ifndef __ASSEMBLY__
297#include <linux/types.h>
298
299/*
300 * bfin pint registers layout
301 */
302struct bfin_pint_regs {
303 u32 mask_set;
304 u32 mask_clear;
305 u32 request;
306 u32 assign;
307 u32 edge_set;
308 u32 edge_clear;
309 u32 invert_set;
310 u32 invert_clear;
311 u32 pinstate;
312 u32 latch;
313 u32 __pad0[2];
314};
315
316#endif
317
318#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/mem_map.h b/arch/blackfin/mach-bf609/include/mach/mem_map.h
new file mode 100644
index 000000000000..9d71eb322ba9
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/mem_map.h
@@ -0,0 +1,86 @@
1/*
2 * BF60x memory map
3 *
4 * Copyright 2011 Analog Devices Inc.
5 * Licensed under the GPL-2 or later.
6 */
7
8#ifndef __BFIN_MACH_MEM_MAP_H__
9#define __BFIN_MACH_MEM_MAP_H__
10
11#ifndef __BFIN_MEM_MAP_H__
12# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
13#endif
14
15/* Async Memory Banks */
16#define ASYNC_BANK3_BASE 0xBC000000 /* Async Bank 3 */
17#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
18#define ASYNC_BANK2_BASE 0xB8000000 /* Async Bank 2 */
19#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
20#define ASYNC_BANK1_BASE 0xB4000000 /* Async Bank 1 */
21#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
22#define ASYNC_BANK0_BASE 0xB0000000 /* Async Bank 0 */
23#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
24
25/* Boot ROM Memory */
26
27#define BOOT_ROM_START 0xC8000000
28#define BOOT_ROM_LENGTH 0x8000
29
30/* Level 1 Memory */
31
32/* Memory Map for ADSP-BF60x processors */
33#ifdef CONFIG_BFIN_ICACHE
34#define BFIN_ICACHESIZE (16*1024)
35#define L1_CODE_LENGTH 0x10000
36#else
37#define BFIN_ICACHESIZE (0*1024)
38#define L1_CODE_LENGTH 0x14000
39#endif
40
41#define L1_CODE_START 0xFFA00000
42#define L1_DATA_A_START 0xFF800000
43#define L1_DATA_B_START 0xFF900000
44
45
46#define COREA_L1_SCRATCH_START 0xFFB00000
47#define COREB_L1_SCRATCH_START 0xFF700000
48
49#define COREB_L1_CODE_START 0xFF600000
50#define COREB_L1_DATA_A_START 0xFF400000
51#define COREB_L1_DATA_B_START 0xFF500000
52
53# define COREB_L1_CODE_LENGTH 0x14000
54# define COREB_L1_DATA_A_LENGTH 0x8000
55# define COREB_L1_DATA_B_LENGTH 0x8000
56
57
58#ifdef CONFIG_BFIN_DCACHE
59
60#ifdef CONFIG_BFIN_DCACHE_BANKA
61#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
62#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
63#define L1_DATA_B_LENGTH 0x8000
64#define BFIN_DCACHESIZE (16*1024)
65#define BFIN_DSUPBANKS 1
66#else
67#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
68#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
69#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
70#define BFIN_DCACHESIZE (32*1024)
71#define BFIN_DSUPBANKS 2
72#endif
73
74#else
75#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
76#define L1_DATA_A_LENGTH 0x8000
77#define L1_DATA_B_LENGTH 0x8000
78#define BFIN_DCACHESIZE (0*1024)
79#define BFIN_DSUPBANKS 0
80#endif /*CONFIG_BFIN_DCACHE*/
81
82/* Level 2 Memory */
83#define L2_START 0xC8080000
84#define L2_LENGTH 0x40000
85
86#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/pll.h b/arch/blackfin/mach-bf609/include/mach/pll.h
new file mode 100644
index 000000000000..1857a4a0f262
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/pll.h
@@ -0,0 +1 @@
/* #include <mach-common/pll.h> */
diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h
new file mode 100644
index 000000000000..2e1a51c25098
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/portmux.h
@@ -0,0 +1,347 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_
9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
11
12/* EMAC RMII Port Mux */
13#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
14#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
15#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
16#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
17#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
18#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
19#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
20#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
21#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
22#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
23#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
24
25#define P_RMII0 {\
26 P_MII0_ETxD0, \
27 P_MII0_ETxD1, \
28 P_MII0_ETxEN, \
29 P_MII0_ERxD0, \
30 P_MII0_ERxD1, \
31 P_MII0_ERxER, \
32 P_MII0_TxCLK, \
33 P_MII0_PHYINT, \
34 P_MII0_CRS, \
35 P_MII0_MDC, \
36 P_MII0_MDIO, 0}
37
38#define P_MII1_MDC (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
39#define P_MII1_MDIO (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
40#define P_MII1_ETxD0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
41#define P_MII1_ERxD0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
42#define P_MII1_ETxD1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
43#define P_MII1_ERxD1 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
44#define P_MII1_ETxEN (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
45#define P_MII1_PHYINT (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
46#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
47#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
48#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
49
50#define P_RMII1 {\
51 P_MII1_ETxD0, \
52 P_MII1_ETxD1, \
53 P_MII1_ETxEN, \
54 P_MII1_ERxD0, \
55 P_MII1_ERxD1, \
56 P_MII1_ERxER, \
57 P_MII1_TxCLK, \
58 P_MII1_PHYINT, \
59 P_MII1_CRS, \
60 P_MII1_MDC, \
61 P_MII1_MDIO, 0}
62
63/* PPI Port Mux */
64#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
65#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
66#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
67#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
68#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
69#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
70#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
71#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
72#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
73#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
74#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
75#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
76#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
77#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
78#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
79#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
80#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
81#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
82#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
83#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
84#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
85#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
86#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
87#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
88#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
89#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
90#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
91#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
92
93#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
94#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
95#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
96#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
97#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
98#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
99#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
100#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
101#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
102#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
103#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
104#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
105#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
106#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
107#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
108#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
109#define P_PPI1_D16 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
110#define P_PPI1_D17 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
111#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
112#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
113#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
114#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
115
116#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
117#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
118#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
119#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
120#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
121#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
122#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
123#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
124#define P_PPI2_D8 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
125#define P_PPI2_D9 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
126#define P_PPI2_D10 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
127#define P_PPI2_D11 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
128#define P_PPI2_D12 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
129#define P_PPI2_D13 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
130#define P_PPI2_D14 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
131#define P_PPI2_D15 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
132#define P_PPI2_D16 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
133#define P_PPI2_D17 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
134#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
135#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
136#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
137#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
138
139/* SPI Port Mux */
140#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
141#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
142#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
143#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
144#define P_SPI0_RDY (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
145#define P_SPI0_D2 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
146#define P_SPI0_D3 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
147
148#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
149#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
150#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
151#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
152#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
153#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
154#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
155
156#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
157#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
158#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
159#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
160#define P_SPI1_RDY (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
161#define P_SPI1_D2 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
162#define P_SPI1_D3 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
163
164#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
165#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
166#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
167#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
168#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
169#define P_SPI1_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
170#define P_SPI1_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
171
172#define GPIO_DEFAULT_BOOT_SPI_CS
173#define P_DEFAULT_BOOT_SPI_CS
174
175/* CORE IDLE */
176#define P_IDLEA (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
177#define P_IDLEB (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
178#define P_SLEEP (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
179
180/* UART Port Mux */
181#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
182#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
183#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
184#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
185
186#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
187#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
188#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
189#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
190
191/* Timer */
192#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
193#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
194#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
195#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
196#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
197#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
198#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
199#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
200#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
201
202/* RSI */
203#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
204#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
205#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
206#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
207#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
208#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
209#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
210#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
211#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
212#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
213
214/* PTP */
215#define P_PTP0_PPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
216#define P_PTP0_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
217#define P_PTP0_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
218
219#define P_PTP1_PPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
220#define P_PTP1_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
221#define P_PTP1_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
222
223/* SMC Port Mux */
224#define P_A3 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
225#define P_A4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
226#define P_A5 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
227#define P_A6 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
228#define P_A7 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
229#define P_A8 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
230#define P_A9 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
231#define P_A10 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
232#define P_A11 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
233#define P_A12 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
234#define P_A13 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
235#define P_A14 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
236#define P_A15 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
237#define P_A16 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
238#define P_A17 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
239#define P_A18 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
240#define P_A19 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
241#define P_A20 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
242#define P_A21 (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
243#define P_A22 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
244#define P_A23 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
245#define P_A24 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
246#define P_A25 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
247#define P_NORCK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
248
249#define P_AMS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
250#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
251#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
252
253/* CAN */
254#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
255#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
256
257/* SPORT */
258#define P_SPORT0_ACLK (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(2))
259#define P_SPORT0_AFS (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(2))
260#define P_SPORT0_AD0 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(2))
261#define P_SPORT0_AD1 (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(2))
262#define P_SPORT0_ATDV (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(1))
263#define P_SPORT0_BCLK (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(2))
264#define P_SPORT0_BFS (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(2))
265#define P_SPORT0_BD0 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(2))
266#define P_SPORT0_BD1 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(2))
267#define P_SPORT0_BTDV (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(1))
268
269#define P_SPORT1_ACLK (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(2))
270#define P_SPORT1_AFS (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(2))
271#define P_SPORT1_AD0 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
272#define P_SPORT1_AD1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
273#define P_SPORT1_ATDV (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
274#define P_SPORT1_BCLK (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(2))
275#define P_SPORT1_BFS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(2))
276#define P_SPORT1_BD0 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(2))
277#define P_SPORT1_BD1 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(2))
278#define P_SPORT1_BTDV (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
279
280#define P_SPORT2_ACLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
281#define P_SPORT2_AFS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
282#define P_SPORT2_AD0 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
283#define P_SPORT2_AD1 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
284#define P_SPORT2_ATDV (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(1))
285#define P_SPORT2_BCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
286#define P_SPORT2_BFS (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
287#define P_SPORT2_BD0 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
288#define P_SPORT2_BD1 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
289#define P_SPORT2_BTDV (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
290
291/* LINK PORT */
292#define P_LP0_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(2))
293#define P_LP0_ACK (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(2))
294#define P_LP0_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(2))
295#define P_LP0_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(2))
296#define P_LP0_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(2))
297#define P_LP0_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(2))
298#define P_LP0_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(2))
299#define P_LP0_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(2))
300#define P_LP0_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(2))
301#define P_LP0_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(2))
302
303#define P_LP1_CLK (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(2))
304#define P_LP1_ACK (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(2))
305#define P_LP1_D0 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(2))
306#define P_LP1_D1 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(2))
307#define P_LP1_D2 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(2))
308#define P_LP1_D3 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(2))
309#define P_LP1_D4 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(2))
310#define P_LP1_D5 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(2))
311#define P_LP1_D6 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(2))
312#define P_LP1_D7 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(2))
313
314#define P_LP2_CLK (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(2))
315#define P_LP2_ACK (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(2))
316#define P_LP2_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
317#define P_LP2_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
318#define P_LP2_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
319#define P_LP2_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
320#define P_LP2_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
321#define P_LP2_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
322#define P_LP2_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
323#define P_LP2_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
324
325#define P_LP3_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(2))
326#define P_LP3_ACK (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(2))
327#define P_LP3_D0 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
328#define P_LP3_D1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
329#define P_LP3_D2 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
330#define P_LP3_D3 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
331#define P_LP3_D4 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
332#define P_LP3_D5 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
333#define P_LP3_D6 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
334#define P_LP3_D7 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
335
336/* TWI */
337#define P_TWI0_SCL (P_DONTCARE)
338#define P_TWI0_SDA (P_DONTCARE)
339#define P_TWI1_SCL (P_DONTCARE)
340#define P_TWI1_SDA (P_DONTCARE)
341
342/* Rotary Encoder */
343#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(3))
344#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(3))
345#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(3))
346
347#endif /* _MACH_PORTMUX_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 12:20:36 -0500