diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-23 00:12:27 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-23 00:12:27 -0400 |
commit | 7f3883962870dd28b5f2322ac44a9d03640ef448 (patch) | |
tree | 01f7dd2ac2b7c61e5e6726c4fec4484aaca6e7b7 /arch/blackfin/mach-bf561 | |
parent | 10f2a2b0f68abf39c06cf519cbc1740fa50f900b (diff) | |
parent | b9ac41e314f0b43641bc01bd553fd2e0458ed832 (diff) |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (47 commits)
Blackfin: bfin_spi.h: add MMR peripheral layout
Blackfin: bfin_ppi.h: start a common PPI/EPPI header
Blackfin: bfin_can.h: add missing VERSION/VERSION2 MMRs
Blackfin: bf538: add missing SIC_RVECT define
Blackfin: bf561: rewrite SICA_xxx to just SIC_xxx
Blackfin: bf54x: add missing SIC_RVECT definition
Blackfin: H8606: move 8250 irqflags to platform resources
Blackfin: glue XIP/ROM kernel kconfigs
Blackfin: update sparse flags for latest upstream changes
Blackfin: coreb: update ioctl numbers
Blackfin: coreb: add gpl module license
Blackfin: bf518-ezkit: add ssm2603 codec resources
Blackfin: bf51x/bf52x: fix 16/32bit SPORT MMR helpers
Blackfin: tll6527m: new board port
Blackfin: bf526-ezbrd/bf527-ezkit: add NAND partition for u-boot
Blackfin: merge kernel init memory back into main memory region
Blackfin: gpio: add peripheral group check
Blackfin: dma: bf54x: add missing break for SPORT1 TX IRQ
Blackfin: add new cacheflush syscall
Blackfin: bf548-ezkit: increase u-boot partition size
...
Diffstat (limited to 'arch/blackfin/mach-bf561')
-rw-r--r-- | arch/blackfin/mach-bf561/boards/acvilon.c | 2 | ||||
-rw-r--r-- | arch/blackfin/mach-bf561/boards/cm_bf561.c | 10 | ||||
-rw-r--r-- | arch/blackfin/mach-bf561/boards/ezkit.c | 68 | ||||
-rw-r--r-- | arch/blackfin/mach-bf561/coreb.c | 11 | ||||
-rw-r--r-- | arch/blackfin/mach-bf561/include/mach/blackfin.h | 33 | ||||
-rw-r--r-- | arch/blackfin/mach-bf561/include/mach/cdefBF561.h | 76 | ||||
-rw-r--r-- | arch/blackfin/mach-bf561/include/mach/defBF561.h | 94 | ||||
-rw-r--r-- | arch/blackfin/mach-bf561/ints-priority.c | 16 | ||||
-rw-r--r-- | arch/blackfin/mach-bf561/smp.c | 24 |
9 files changed, 152 insertions, 182 deletions
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c index 35b6d124c1e3..0b1c20f14fe0 100644 --- a/arch/blackfin/mach-bf561/boards/acvilon.c +++ b/arch/blackfin/mach-bf561/boards/acvilon.c | |||
@@ -302,7 +302,7 @@ static struct platform_nand_data bfin_plat_nand_data = { | |||
302 | static struct resource bfin_plat_nand_resources = { | 302 | static struct resource bfin_plat_nand_resources = { |
303 | .start = 0x24000000, | 303 | .start = 0x24000000, |
304 | .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), | 304 | .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), |
305 | .flags = IORESOURCE_IO, | 305 | .flags = IORESOURCE_MEM, |
306 | }; | 306 | }; |
307 | 307 | ||
308 | static struct platform_device bfin_async_nand_device = { | 308 | static struct platform_device bfin_async_nand_device = { |
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index e127aedc1d7f..087b6b05cc73 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c | |||
@@ -72,7 +72,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { | |||
72 | }; | 72 | }; |
73 | #endif | 73 | #endif |
74 | 74 | ||
75 | #if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) | 75 | #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) |
76 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | 76 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { |
77 | .enable_dma = 0, | 77 | .enable_dma = 0, |
78 | .bits_per_word = 16, | 78 | .bits_per_word = 16, |
@@ -111,12 +111,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
111 | }, | 111 | }, |
112 | #endif | 112 | #endif |
113 | 113 | ||
114 | #if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) | 114 | #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) |
115 | { | 115 | { |
116 | .modalias = "ad1836", | 116 | .modalias = "ad183x", |
117 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 117 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
118 | .bus_num = 0, | 118 | .bus_num = 0, |
119 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 119 | .chip_select = 4, |
120 | .controller_data = &ad1836_spi_chip_info, | 120 | .controller_data = &ad1836_spi_chip_info, |
121 | }, | 121 | }, |
122 | #endif | 122 | #endif |
@@ -278,7 +278,7 @@ static struct resource isp1362_hcd_resources[] = { | |||
278 | }, { | 278 | }, { |
279 | .start = IRQ_PF47, | 279 | .start = IRQ_PF47, |
280 | .end = IRQ_PF47, | 280 | .end = IRQ_PF47, |
281 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | 281 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, |
282 | }, | 282 | }, |
283 | }; | 283 | }; |
284 | 284 | ||
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 9b93e2f95791..ab7a487975fd 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/spi/spi.h> | 14 | #include <linux/spi/spi.h> |
15 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
16 | #include <linux/interrupt.h> | 16 | #include <linux/interrupt.h> |
17 | #include <linux/delay.h> | ||
17 | #include <asm/dma.h> | 18 | #include <asm/dma.h> |
18 | #include <asm/bfin5xx_spi.h> | 19 | #include <asm/bfin5xx_spi.h> |
19 | #include <asm/portmux.h> | 20 | #include <asm/portmux.h> |
@@ -74,7 +75,7 @@ static struct resource isp1362_hcd_resources[] = { | |||
74 | }, { | 75 | }, { |
75 | .start = IRQ_PF8, | 76 | .start = IRQ_PF8, |
76 | .end = IRQ_PF8, | 77 | .end = IRQ_PF8, |
77 | .flags = IORESOURCE_IRQ, | 78 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, |
78 | }, | 79 | }, |
79 | }; | 80 | }; |
80 | 81 | ||
@@ -274,8 +275,8 @@ static struct platform_device ezkit_flash_device = { | |||
274 | }; | 275 | }; |
275 | #endif | 276 | #endif |
276 | 277 | ||
277 | #if defined(CONFIG_SND_BLACKFIN_AD183X) \ | 278 | #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ |
278 | || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) | 279 | || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) |
279 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | 280 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { |
280 | .enable_dma = 0, | 281 | .enable_dma = 0, |
281 | .bits_per_word = 16, | 282 | .bits_per_word = 16, |
@@ -328,14 +329,16 @@ static struct platform_device bfin_spi0_device = { | |||
328 | #endif | 329 | #endif |
329 | 330 | ||
330 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | 331 | static struct spi_board_info bfin_spi_board_info[] __initdata = { |
331 | #if defined(CONFIG_SND_BLACKFIN_AD183X) \ | 332 | #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ |
332 | || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) | 333 | || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) |
333 | { | 334 | { |
334 | .modalias = "ad1836", | 335 | .modalias = "ad183x", |
335 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | 336 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
336 | .bus_num = 0, | 337 | .bus_num = 0, |
337 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | 338 | .chip_select = 4, |
339 | .platform_data = "ad1836", /* only includes chip name for the moment */ | ||
338 | .controller_data = &ad1836_spi_chip_info, | 340 | .controller_data = &ad1836_spi_chip_info, |
341 | .mode = SPI_MODE_3, | ||
339 | }, | 342 | }, |
340 | #endif | 343 | #endif |
341 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | 344 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) |
@@ -377,8 +380,8 @@ static struct platform_device bfin_device_gpiokeys = { | |||
377 | #include <linux/i2c-gpio.h> | 380 | #include <linux/i2c-gpio.h> |
378 | 381 | ||
379 | static struct i2c_gpio_platform_data i2c_gpio_data = { | 382 | static struct i2c_gpio_platform_data i2c_gpio_data = { |
380 | .sda_pin = 1, | 383 | .sda_pin = GPIO_PF1, |
381 | .scl_pin = 0, | 384 | .scl_pin = GPIO_PF0, |
382 | .sda_is_open_drain = 0, | 385 | .sda_is_open_drain = 0, |
383 | .scl_is_open_drain = 0, | 386 | .scl_is_open_drain = 0, |
384 | .udelay = 40, | 387 | .udelay = 40, |
@@ -420,6 +423,30 @@ static struct platform_device bfin_dpmc = { | |||
420 | }, | 423 | }, |
421 | }; | 424 | }; |
422 | 425 | ||
426 | #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) | ||
427 | static struct platform_device bfin_i2s = { | ||
428 | .name = "bfin-i2s", | ||
429 | .id = CONFIG_SND_BF5XX_SPORT_NUM, | ||
430 | /* TODO: add platform data here */ | ||
431 | }; | ||
432 | #endif | ||
433 | |||
434 | #if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) | ||
435 | static struct platform_device bfin_tdm = { | ||
436 | .name = "bfin-tdm", | ||
437 | .id = CONFIG_SND_BF5XX_SPORT_NUM, | ||
438 | /* TODO: add platform data here */ | ||
439 | }; | ||
440 | #endif | ||
441 | |||
442 | #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) | ||
443 | static struct platform_device bfin_ac97 = { | ||
444 | .name = "bfin-ac97", | ||
445 | .id = CONFIG_SND_BF5XX_SPORT_NUM, | ||
446 | /* TODO: add platform data here */ | ||
447 | }; | ||
448 | #endif | ||
449 | |||
423 | static struct platform_device *ezkit_devices[] __initdata = { | 450 | static struct platform_device *ezkit_devices[] __initdata = { |
424 | 451 | ||
425 | &bfin_dpmc, | 452 | &bfin_dpmc, |
@@ -467,6 +494,18 @@ static struct platform_device *ezkit_devices[] __initdata = { | |||
467 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | 494 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
468 | &ezkit_flash_device, | 495 | &ezkit_flash_device, |
469 | #endif | 496 | #endif |
497 | |||
498 | #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) | ||
499 | &bfin_i2s, | ||
500 | #endif | ||
501 | |||
502 | #if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) | ||
503 | &bfin_tdm, | ||
504 | #endif | ||
505 | |||
506 | #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) | ||
507 | &bfin_ac97, | ||
508 | #endif | ||
470 | }; | 509 | }; |
471 | 510 | ||
472 | static int __init ezkit_init(void) | 511 | static int __init ezkit_init(void) |
@@ -484,6 +523,17 @@ static int __init ezkit_init(void) | |||
484 | SSYNC(); | 523 | SSYNC(); |
485 | #endif | 524 | #endif |
486 | 525 | ||
526 | #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) | ||
527 | bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15)); | ||
528 | bfin_write_FIO0_FLAG_S(1 << 15); | ||
529 | SSYNC(); | ||
530 | /* | ||
531 | * This initialization lasts for approximately 4500 MCLKs. | ||
532 | * MCLK = 12.288MHz | ||
533 | */ | ||
534 | udelay(400); | ||
535 | #endif | ||
536 | |||
487 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | 537 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); |
488 | return 0; | 538 | return 0; |
489 | } | 539 | } |
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c index c6a4c8f2d37b..78ecb50bafc8 100644 --- a/arch/blackfin/mach-bf561/coreb.c +++ b/arch/blackfin/mach-bf561/coreb.c | |||
@@ -18,9 +18,9 @@ | |||
18 | #include <linux/miscdevice.h> | 18 | #include <linux/miscdevice.h> |
19 | #include <linux/module.h> | 19 | #include <linux/module.h> |
20 | 20 | ||
21 | #define CMD_COREB_START 2 | 21 | #define CMD_COREB_START _IO('b', 0) |
22 | #define CMD_COREB_STOP 3 | 22 | #define CMD_COREB_STOP _IO('b', 1) |
23 | #define CMD_COREB_RESET 4 | 23 | #define CMD_COREB_RESET _IO('b', 2) |
24 | 24 | ||
25 | static long | 25 | static long |
26 | coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | 26 | coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
@@ -29,10 +29,10 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |||
29 | 29 | ||
30 | switch (cmd) { | 30 | switch (cmd) { |
31 | case CMD_COREB_START: | 31 | case CMD_COREB_START: |
32 | bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); | 32 | bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020); |
33 | break; | 33 | break; |
34 | case CMD_COREB_STOP: | 34 | case CMD_COREB_STOP: |
35 | bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); | 35 | bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020); |
36 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); | 36 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); |
37 | break; | 37 | break; |
38 | case CMD_COREB_RESET: | 38 | case CMD_COREB_RESET: |
@@ -74,3 +74,4 @@ module_exit(bf561_coreb_exit); | |||
74 | 74 | ||
75 | MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>"); | 75 | MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>"); |
76 | MODULE_DESCRIPTION("BF561 Core B Support"); | 76 | MODULE_DESCRIPTION("BF561 Core B Support"); |
77 | MODULE_LICENSE("GPL"); | ||
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h index 67d6bdcd3fa8..6c7dc58c018c 100644 --- a/arch/blackfin/mach-bf561/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h | |||
@@ -24,29 +24,16 @@ | |||
24 | #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() | 24 | #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() |
25 | #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) | 25 | #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) |
26 | 26 | ||
27 | #define SIC_IWR0 SICA_IWR0 | 27 | /* Weird muxer funcs which pick SIC regs from IMASK base */ |
28 | #define SIC_IWR1 SICA_IWR1 | 28 | #define __SIC_MUX(base, x) ((base) + ((x) << 2)) |
29 | #define SIC_IAR0 SICA_IAR0 | 29 | #define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x)) |
30 | #define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 | 30 | #define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val) |
31 | #define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 | 31 | #define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x)) |
32 | #define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0 | 32 | #define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val) |
33 | #define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1 | 33 | #define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x)) |
34 | 34 | #define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val) | |
35 | #define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0 | 35 | #define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x)) |
36 | #define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1 | 36 | #define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val) |
37 | #define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0 | ||
38 | #define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1 | ||
39 | #define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0 | ||
40 | #define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1 | ||
41 | |||
42 | #define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2)) | ||
43 | #define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val) | ||
44 | #define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2)) | ||
45 | #define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val) | ||
46 | #define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) | ||
47 | #define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) | ||
48 | #define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2)) | ||
49 | #define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val) | ||
50 | 37 | ||
51 | #define BFIN_UART_NR_PORTS 1 | 38 | #define BFIN_UART_NR_PORTS 1 |
52 | 39 | ||
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h index cc0416a5fa02..2bab99152495 100644 --- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h | |||
@@ -30,49 +30,41 @@ | |||
30 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) | 30 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) |
31 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | 31 | #define bfin_read_CHIPID() bfin_read32(CHIPID) |
32 | 32 | ||
33 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ | ||
34 | #define bfin_read_SWRST() bfin_read_SICA_SWRST() | ||
35 | #define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val) | ||
36 | #define bfin_read_SYSCR() bfin_read_SICA_SYSCR() | ||
37 | #define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val) | ||
38 | |||
39 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ | 33 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ |
40 | #define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) | 34 | #define bfin_read_SWRST() bfin_read16(SWRST) |
41 | #define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) | 35 | #define bfin_write_SWRST(val) bfin_write16(SWRST,val) |
42 | #define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) | 36 | #define bfin_read_SYSCR() bfin_read16(SYSCR) |
43 | #define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val) | 37 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) |
44 | #define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) | 38 | #define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) |
45 | #define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val) | 39 | #define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val) |
46 | #define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK) | 40 | #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) |
47 | #define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val) | 41 | #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val) |
48 | #define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) | 42 | #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) |
49 | #define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val) | 43 | #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val) |
50 | #define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) | 44 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) |
51 | #define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val) | 45 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) |
52 | #define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) | 46 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) |
53 | #define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val) | 47 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) |
54 | #define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) | 48 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) |
55 | #define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val) | 49 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) |
56 | #define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) | 50 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) |
57 | #define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val) | 51 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) |
58 | #define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) | 52 | #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) |
59 | #define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val) | 53 | #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val) |
60 | #define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) | 54 | #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) |
61 | #define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val) | 55 | #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val) |
62 | #define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) | 56 | #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) |
63 | #define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val) | 57 | #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val) |
64 | #define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) | 58 | #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) |
65 | #define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val) | 59 | #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val) |
66 | #define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) | 60 | #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) |
67 | #define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val) | 61 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val) |
68 | #define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) | 62 | #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) |
69 | #define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val) | 63 | #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val) |
70 | #define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) | 64 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) |
71 | #define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val) | 65 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val) |
72 | #define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) | 66 | #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) |
73 | #define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val) | 67 | #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val) |
74 | #define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1) | ||
75 | #define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val) | ||
76 | 68 | ||
77 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ | 69 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ |
78 | #define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) | 70 | #define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) |
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index 2674f0097576..79e048d452e0 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h | |||
@@ -28,32 +28,29 @@ | |||
28 | #define CHIPID 0xFFC00014 /* Chip ID Register */ | 28 | #define CHIPID 0xFFC00014 /* Chip ID Register */ |
29 | 29 | ||
30 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ | 30 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ |
31 | #define SWRST SICA_SWRST | ||
32 | #define SYSCR SICA_SYSCR | ||
33 | #define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) | 31 | #define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) |
34 | #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) | 32 | #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) |
35 | #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) | 33 | #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) |
36 | #define RESET_SOFTWARE (SWRST_OCCURRED) | 34 | #define RESET_SOFTWARE (SWRST_OCCURRED) |
37 | 35 | ||
38 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ | 36 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ |
39 | #define SICA_SWRST 0xFFC00100 /* Software Reset register */ | 37 | #define SWRST 0xFFC00100 /* Software Reset register */ |
40 | #define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ | 38 | #define SYSCR 0xFFC00104 /* System Reset Configuration register */ |
41 | #define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ | 39 | #define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ |
42 | #define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ | 40 | #define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ |
43 | #define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ | 41 | #define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ |
44 | #define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ | 42 | #define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ |
45 | #define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ | 43 | #define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ |
46 | #define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ | 44 | #define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ |
47 | #define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ | 45 | #define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ |
48 | #define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ | 46 | #define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ |
49 | #define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ | 47 | #define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ |
50 | #define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ | 48 | #define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ |
51 | #define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ | 49 | #define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ |
52 | #define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ | 50 | #define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ |
53 | #define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ | 51 | #define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ |
54 | #define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ | 52 | #define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ |
55 | #define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ | 53 | #define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ |
56 | #define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ | ||
57 | 54 | ||
58 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ | 55 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ |
59 | #define SICB_SWRST 0xFFC01100 /* reserved */ | 56 | #define SICB_SWRST 0xFFC01100 /* reserved */ |
@@ -1271,63 +1268,6 @@ | |||
1271 | #define PF14_P 14 | 1268 | #define PF14_P 14 |
1272 | #define PF15_P 15 | 1269 | #define PF15_P 15 |
1273 | 1270 | ||
1274 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ | ||
1275 | |||
1276 | /* SPI_CTL Masks */ | ||
1277 | #define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ | ||
1278 | #define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ | ||
1279 | #define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ | ||
1280 | #define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ | ||
1281 | #define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ | ||
1282 | #define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ | ||
1283 | #define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ | ||
1284 | #define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ | ||
1285 | #define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ | ||
1286 | #define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ | ||
1287 | #define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ | ||
1288 | #define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ | ||
1289 | |||
1290 | /* SPI_FLG Masks */ | ||
1291 | #define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
1292 | #define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
1293 | #define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
1294 | #define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
1295 | #define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
1296 | #define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
1297 | #define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
1298 | #define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
1299 | #define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
1300 | #define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
1301 | #define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
1302 | #define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
1303 | #define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
1304 | #define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
1305 | |||
1306 | /* SPI_FLG Bit Positions */ | ||
1307 | #define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
1308 | #define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
1309 | #define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
1310 | #define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
1311 | #define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
1312 | #define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
1313 | #define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
1314 | #define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
1315 | #define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
1316 | #define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
1317 | #define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
1318 | #define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
1319 | #define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
1320 | #define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
1321 | |||
1322 | /* SPI_STAT Masks */ | ||
1323 | #define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ | ||
1324 | #define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ | ||
1325 | #define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ | ||
1326 | #define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ | ||
1327 | #define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ | ||
1328 | #define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ | ||
1329 | #define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ | ||
1330 | |||
1331 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ | 1271 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ |
1332 | 1272 | ||
1333 | /* AMGCTL Masks */ | 1273 | /* AMGCTL Masks */ |
diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c index b4424172ad9e..7ee9262fe132 100644 --- a/arch/blackfin/mach-bf561/ints-priority.c +++ b/arch/blackfin/mach-bf561/ints-priority.c | |||
@@ -13,7 +13,7 @@ | |||
13 | void __init program_IAR(void) | 13 | void __init program_IAR(void) |
14 | { | 14 | { |
15 | /* Program the IAR0 Register with the configured priority */ | 15 | /* Program the IAR0 Register with the configured priority */ |
16 | bfin_write_SICA_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | | 16 | bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | |
17 | ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) | | 17 | ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) | |
18 | ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) | | 18 | ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) | |
19 | ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) | | 19 | ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) | |
@@ -22,7 +22,7 @@ void __init program_IAR(void) | |||
22 | ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | | 22 | ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | |
23 | ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS)); | 23 | ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS)); |
24 | 24 | ||
25 | bfin_write_SICA_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) | | 25 | bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) | |
26 | ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) | | 26 | ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) | |
27 | ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) | | 27 | ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) | |
28 | ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) | | 28 | ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) | |
@@ -31,7 +31,7 @@ void __init program_IAR(void) | |||
31 | ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) | | 31 | ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) | |
32 | ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS)); | 32 | ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS)); |
33 | 33 | ||
34 | bfin_write_SICA_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) | | 34 | bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) | |
35 | ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) | | 35 | ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) | |
36 | ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) | | 36 | ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) | |
37 | ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) | | 37 | ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) | |
@@ -40,7 +40,7 @@ void __init program_IAR(void) | |||
40 | ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) | | 40 | ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) | |
41 | ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS)); | 41 | ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS)); |
42 | 42 | ||
43 | bfin_write_SICA_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) | | 43 | bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) | |
44 | ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) | | 44 | ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) | |
45 | ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) | | 45 | ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) | |
46 | ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) | | 46 | ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) | |
@@ -49,7 +49,7 @@ void __init program_IAR(void) | |||
49 | ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) | | 49 | ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) | |
50 | ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS)); | 50 | ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS)); |
51 | 51 | ||
52 | bfin_write_SICA_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) | | 52 | bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) | |
53 | ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) | | 53 | ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) | |
54 | ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) | | 54 | ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) | |
55 | ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | | 55 | ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | |
@@ -58,7 +58,7 @@ void __init program_IAR(void) | |||
58 | ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | | 58 | ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | |
59 | ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS)); | 59 | ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS)); |
60 | 60 | ||
61 | bfin_write_SICA_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | | 61 | bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | |
62 | ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | | 62 | ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | |
63 | ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | | 63 | ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | |
64 | ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) | | 64 | ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) | |
@@ -67,7 +67,7 @@ void __init program_IAR(void) | |||
67 | ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) | | 67 | ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) | |
68 | ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS)); | 68 | ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS)); |
69 | 69 | ||
70 | bfin_write_SICA_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) | | 70 | bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) | |
71 | ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) | | 71 | ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) | |
72 | ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) | | 72 | ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) | |
73 | ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) | | 73 | ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) | |
@@ -76,7 +76,7 @@ void __init program_IAR(void) | |||
76 | ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) | | 76 | ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) | |
77 | ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS)); | 77 | ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS)); |
78 | 78 | ||
79 | bfin_write_SICA_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) | | 79 | bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) | |
80 | ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) | | 80 | ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) | |
81 | ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) | | 81 | ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) | |
82 | ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) | | 82 | ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) | |
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c index 3b9a4bf7dacc..f540ed1257d6 100644 --- a/arch/blackfin/mach-bf561/smp.c +++ b/arch/blackfin/mach-bf561/smp.c | |||
@@ -52,19 +52,19 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ | |||
52 | void __cpuinit platform_secondary_init(unsigned int cpu) | 52 | void __cpuinit platform_secondary_init(unsigned int cpu) |
53 | { | 53 | { |
54 | /* Clone setup for peripheral interrupt sources from CoreA. */ | 54 | /* Clone setup for peripheral interrupt sources from CoreA. */ |
55 | bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0()); | 55 | bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0()); |
56 | bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1()); | 56 | bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1()); |
57 | SSYNC(); | 57 | SSYNC(); |
58 | 58 | ||
59 | /* Clone setup for IARs from CoreA. */ | 59 | /* Clone setup for IARs from CoreA. */ |
60 | bfin_write_SICB_IAR0(bfin_read_SICA_IAR0()); | 60 | bfin_write_SICB_IAR0(bfin_read_SIC_IAR0()); |
61 | bfin_write_SICB_IAR1(bfin_read_SICA_IAR1()); | 61 | bfin_write_SICB_IAR1(bfin_read_SIC_IAR1()); |
62 | bfin_write_SICB_IAR2(bfin_read_SICA_IAR2()); | 62 | bfin_write_SICB_IAR2(bfin_read_SIC_IAR2()); |
63 | bfin_write_SICB_IAR3(bfin_read_SICA_IAR3()); | 63 | bfin_write_SICB_IAR3(bfin_read_SIC_IAR3()); |
64 | bfin_write_SICB_IAR4(bfin_read_SICA_IAR4()); | 64 | bfin_write_SICB_IAR4(bfin_read_SIC_IAR4()); |
65 | bfin_write_SICB_IAR5(bfin_read_SICA_IAR5()); | 65 | bfin_write_SICB_IAR5(bfin_read_SIC_IAR5()); |
66 | bfin_write_SICB_IAR6(bfin_read_SICA_IAR6()); | 66 | bfin_write_SICB_IAR6(bfin_read_SIC_IAR6()); |
67 | bfin_write_SICB_IAR7(bfin_read_SICA_IAR7()); | 67 | bfin_write_SICB_IAR7(bfin_read_SIC_IAR7()); |
68 | bfin_write_SICB_IWR0(IWR_DISABLE_ALL); | 68 | bfin_write_SICB_IWR0(IWR_DISABLE_ALL); |
69 | bfin_write_SICB_IWR1(IWR_DISABLE_ALL); | 69 | bfin_write_SICB_IWR1(IWR_DISABLE_ALL); |
70 | SSYNC(); | 70 | SSYNC(); |
@@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle | |||
86 | 86 | ||
87 | spin_lock(&boot_lock); | 87 | spin_lock(&boot_lock); |
88 | 88 | ||
89 | if ((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0) { | 89 | if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) { |
90 | /* CoreB already running, sending ipi to wakeup it */ | 90 | /* CoreB already running, sending ipi to wakeup it */ |
91 | platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); | 91 | platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); |
92 | } else { | 92 | } else { |
93 | /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ | 93 | /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ |
94 | bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT); | 94 | bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT); |
95 | SSYNC(); | 95 | SSYNC(); |
96 | } | 96 | } |
97 | 97 | ||