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authorMike Frysinger <vapier@gentoo.org>2010-10-27 10:06:32 -0400
committerMike Frysinger <vapier@gentoo.org>2011-01-10 07:18:10 -0500
commit94a038c2e6228727ae0549af75e97b9b634cd468 (patch)
tree2428073e580a236b3324e1459105d8a8f2498f34 /arch/blackfin/mach-bf561
parenta2ce077ab3ea30b61a39038cc8d14119c0b2e90a (diff)
Blackfin: bf561: update a few more SIC_SYSCR locations
Looks like I missed a few new spots when renaming the SICA macros. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/pll.h24
-rw-r--r--arch/blackfin/mach-bf561/smp.c4
2 files changed, 14 insertions, 14 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h
index f2b1fbdb8e72..5cdb655c4465 100644
--- a/arch/blackfin/mach-bf561/include/mach/pll.h
+++ b/arch/blackfin/mach-bf561/include/mach/pll.h
@@ -20,18 +20,18 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
20 20
21 flags = hard_local_irq_save(); 21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */ 22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SICA_IWR0); 23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SICA_IWR1); 24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */ 25 /* Only allow PPL Wakeup) */
26 bfin_write32(SICA_IWR0, IWR_ENABLE(0)); 26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SICA_IWR1, 0); 27 bfin_write32(SIC_IWR1, 0);
28 28
29 bfin_write16(PLL_CTL, val); 29 bfin_write16(PLL_CTL, val);
30 SSYNC(); 30 SSYNC();
31 asm("IDLE;"); 31 asm("IDLE;");
32 32
33 bfin_write32(SICA_IWR0, iwr0); 33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SICA_IWR1, iwr1); 34 bfin_write32(SIC_IWR1, iwr1);
35 hard_local_irq_restore(flags); 35 hard_local_irq_restore(flags);
36} 36}
37 37
@@ -45,18 +45,18 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
45 45
46 flags = hard_local_irq_save(); 46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */ 47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SICA_IWR0); 48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SICA_IWR1); 49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */ 50 /* Only allow PPL Wakeup) */
51 bfin_write32(SICA_IWR0, IWR_ENABLE(0)); 51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SICA_IWR1, 0); 52 bfin_write32(SIC_IWR1, 0);
53 53
54 bfin_write16(VR_CTL, val); 54 bfin_write16(VR_CTL, val);
55 SSYNC(); 55 SSYNC();
56 asm("IDLE;"); 56 asm("IDLE;");
57 57
58 bfin_write32(SICA_IWR0, iwr0); 58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SICA_IWR1, iwr1); 59 bfin_write32(SIC_IWR1, iwr1);
60 hard_local_irq_restore(flags); 60 hard_local_irq_restore(flags);
61} 61}
62 62
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index f540ed1257d6..be6083a7e42f 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
86 86
87 spin_lock(&boot_lock); 87 spin_lock(&boot_lock);
88 88
89 if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) { 89 if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
90 /* CoreB already running, sending ipi to wakeup it */ 90 /* CoreB already running, sending ipi to wakeup it */
91 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); 91 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
92 } else { 92 } else {
93 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ 93 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
94 bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT); 94 bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
95 SSYNC(); 95 SSYNC();
96 } 96 }
97 97