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authorMichael Hennerich <michael.hennerich@analog.com>2009-01-07 10:14:39 -0500
committerBryan Wu <cooloney@kernel.org>2009-01-07 10:14:39 -0500
commit73feb5c09dcf0d64beb67aa5e1f79e11a388e0ff (patch)
tree09fa1f153a2ca810ad72978736f85359205d64a3 /arch/blackfin/mach-bf561
parentc97618d3b7b8ef86a966c4b67b54e5ca15814905 (diff)
Blackfin arch: fix bugs and unify BFIN_KERNEL_CLOCK option
- remove duplicated code and headers - add option allowing arbitrary SDRAM/DDR Timing parameters. - mark automatically calculated timings as EXPERIMENTAL - fix comment header block Related to BUGs: - kernel boot up fails with CONFIG_BFIN_KERNEL_CLOCK item on. - kernel does not boot if re-program clocks [ Mike Frysinger <vapier.adi@gmail.com> - fix comment header - mark do_sync static - document the DMA shutdown - simplify SIC_IWR handling - fix ANOMALY_05000265 handling to work as intended ] Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
-rw-r--r--arch/blackfin/mach-bf561/Makefile2
-rw-r--r--arch/blackfin/mach-bf561/head.S136
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_init.h295
3 files changed, 0 insertions, 433 deletions
diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile
index c37f00c0edb5..59e18afe28c6 100644
--- a/arch/blackfin/mach-bf561/Makefile
+++ b/arch/blackfin/mach-bf561/Makefile
@@ -2,8 +2,6 @@
2# arch/blackfin/mach-bf561/Makefile 2# arch/blackfin/mach-bf561/Makefile
3# 3#
4 4
5extra-y := head.o
6
7obj-y := ints-priority.o dma.o 5obj-y := ints-priority.o dma.o
8 6
9obj-$(CONFIG_BF561_COREB) += coreb.o 7obj-$(CONFIG_BF561_COREB) += coreb.o
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
deleted file mode 100644
index 31a777a9e699..000000000000
--- a/arch/blackfin/mach-bf561/head.S
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf561/head.S
3 * Based on: arch/blackfin/mach-bf533/head.S
4 * Author:
5 *
6 * Created:
7 * Description: BF561 startup file
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <linux/init.h>
32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/clocks.h>
35#include <mach/mem_init.h>
36#endif
37
38.section .l1.text
39#ifdef CONFIG_BFIN_KERNEL_CLOCK
40ENTRY(_start_dma_code)
41 p0.h = hi(SICA_IWR0);
42 p0.l = lo(SICA_IWR0);
43 r0.l = 0x1;
44 [p0] = r0;
45 SSYNC;
46
47 /*
48 * Set PLL_CTL
49 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
50 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
51 * - [7] = output delay (add 200ps of delay to mem signals)
52 * - [6] = input delay (add 200ps of input delay to mem signals)
53 * - [5] = PDWN : 1=All Clocks off
54 * - [3] = STOPCK : 1=Core Clock off
55 * - [1] = PLL_OFF : 1=Disable Power to PLL
56 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
57 * all other bits set to zero
58 */
59
60 p0.h = hi(PLL_LOCKCNT);
61 p0.l = lo(PLL_LOCKCNT);
62 r0 = 0x300(Z);
63 w[p0] = r0.l;
64 ssync;
65
66 P2.H = hi(EBIU_SDGCTL);
67 P2.L = lo(EBIU_SDGCTL);
68 R0 = [P2];
69 BITSET (R0, 24);
70 [P2] = R0;
71 SSYNC;
72
73 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
74 r0 = r0 << 9; /* Shift it over, */
75 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
76 r0 = r1 | r0;
77 r1 = PLL_BYPASS; /* Bypass the PLL? */
78 r1 = r1 << 8; /* Shift it over */
79 r0 = r1 | r0; /* add them all together */
80#ifdef ANOMALY_05000265
81 BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
82#endif
83
84 p0.h = hi(PLL_CTL);
85 p0.l = lo(PLL_CTL); /* Load the address */
86 cli r2; /* Disable interrupts */
87 ssync;
88 w[p0] = r0.l; /* Set the value */
89 idle; /* Wait for the PLL to stablize */
90 sti r2; /* Enable interrupts */
91
92.Lcheck_again:
93 p0.h = hi(PLL_STAT);
94 p0.l = lo(PLL_STAT);
95 R0 = W[P0](Z);
96 CC = BITTST(R0,5);
97 if ! CC jump .Lcheck_again;
98
99 /* Configure SCLK & CCLK Dividers */
100 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
101 p0.h = hi(PLL_DIV);
102 p0.l = lo(PLL_DIV);
103 w[p0] = r0.l;
104 ssync;
105
106 p0.l = lo(EBIU_SDRRC);
107 p0.h = hi(EBIU_SDRRC);
108 r0 = mem_SDRRC;
109 w[p0] = r0.l;
110 ssync;
111
112 P2.H = hi(EBIU_SDGCTL);
113 P2.L = lo(EBIU_SDGCTL);
114 R0 = [P2];
115 BITCLR (R0, 24);
116 p0.h = hi(EBIU_SDSTAT);
117 p0.l = lo(EBIU_SDSTAT);
118 r2.l = w[p0];
119 cc = bittst(r2,3);
120 if !cc jump .Lskip;
121 NOP;
122 BITSET (R0, 23);
123.Lskip:
124 [P2] = R0;
125 SSYNC;
126
127 R0.L = lo(mem_SDGCTL);
128 R0.H = hi(mem_SDGCTL);
129 R1 = [p2];
130 R1 = R1 | R0;
131 [P2] = R1;
132 SSYNC;
133
134 RTS;
135ENDPROC(_start_dma_code)
136#endif /* CONFIG_BFIN_KERNEL_CLOCK */
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_init.h b/arch/blackfin/mach-bf561/include/mach/mem_init.h
deleted file mode 100644
index e163260bca18..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/mem_init.h
+++ /dev/null
@@ -1,295 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7)
32#if (CONFIG_SCLK_HZ > 119402985)
33#define SDRAM_tRP TRP_2
34#define SDRAM_tRP_num 2
35#define SDRAM_tRAS TRAS_7
36#define SDRAM_tRAS_num 7
37#define SDRAM_tRCD TRCD_2
38#define SDRAM_tWR TWR_2
39#endif
40#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
41#define SDRAM_tRP TRP_2
42#define SDRAM_tRP_num 2
43#define SDRAM_tRAS TRAS_6
44#define SDRAM_tRAS_num 6
45#define SDRAM_tRCD TRCD_2
46#define SDRAM_tWR TWR_2
47#endif
48#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
49#define SDRAM_tRP TRP_2
50#define SDRAM_tRP_num 2
51#define SDRAM_tRAS TRAS_5
52#define SDRAM_tRAS_num 5
53#define SDRAM_tRCD TRCD_2
54#define SDRAM_tWR TWR_2
55#endif
56#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
57#define SDRAM_tRP TRP_2
58#define SDRAM_tRP_num 2
59#define SDRAM_tRAS TRAS_4
60#define SDRAM_tRAS_num 4
61#define SDRAM_tRCD TRCD_2
62#define SDRAM_tWR TWR_2
63#endif
64#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
65#define SDRAM_tRP TRP_2
66#define SDRAM_tRP_num 2
67#define SDRAM_tRAS TRAS_3
68#define SDRAM_tRAS_num 3
69#define SDRAM_tRCD TRCD_2
70#define SDRAM_tWR TWR_2
71#endif
72#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
73#define SDRAM_tRP TRP_1
74#define SDRAM_tRP_num 1
75#define SDRAM_tRAS TRAS_4
76#define SDRAM_tRAS_num 3
77#define SDRAM_tRCD TRCD_1
78#define SDRAM_tWR TWR_2
79#endif
80#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
81#define SDRAM_tRP TRP_1
82#define SDRAM_tRP_num 1
83#define SDRAM_tRAS TRAS_3
84#define SDRAM_tRAS_num 3
85#define SDRAM_tRCD TRCD_1
86#define SDRAM_tWR TWR_2
87#endif
88#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
89#define SDRAM_tRP TRP_1
90#define SDRAM_tRP_num 1
91#define SDRAM_tRAS TRAS_2
92#define SDRAM_tRAS_num 2
93#define SDRAM_tRCD TRCD_1
94#define SDRAM_tWR TWR_2
95#endif
96#if (CONFIG_SCLK_HZ <= 29850746)
97#define SDRAM_tRP TRP_1
98#define SDRAM_tRP_num 1
99#define SDRAM_tRAS TRAS_1
100#define SDRAM_tRAS_num 1
101#define SDRAM_tRCD TRCD_1
102#define SDRAM_tWR TWR_2
103#endif
104#endif
105
106#if (CONFIG_MEM_MT48LC16M16A2TG_75)
107 /*SDRAM INFORMATION: */
108#define SDRAM_Tref 64 /* Refresh period in milliseconds */
109#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
110#define SDRAM_CL CL_3
111#endif
112
113#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
114 /*SDRAM INFORMATION: */
115#define SDRAM_Tref 64 /* Refresh period in milliseconds */
116#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
117#define SDRAM_CL CL_3
118#endif
119
120#if (CONFIG_MEM_MT48LC8M32B2B5_7)
121 /*SDRAM INFORMATION: */
122#define SDRAM_Tref 64 /* Refresh period in milliseconds */
123#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
124#define SDRAM_CL CL_3
125#endif
126
127#if (CONFIG_MEM_GENERIC_BOARD)
128 /*SDRAM INFORMATION: Modify this for your board */
129#define SDRAM_Tref 64 /* Refresh period in milliseconds */
130#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
131#define SDRAM_CL CL_3
132#endif
133
134/* Equation from section 17 (p17-46) of BF533 HRM */
135#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
136
137/* Enable SCLK Out */
138#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
139
140#if defined CONFIG_CLKIN_HALF
141#define CLKIN_HALF 1
142#else
143#define CLKIN_HALF 0
144#endif
145
146#if defined CONFIG_PLL_BYPASS
147#define PLL_BYPASS 1
148#else
149#define PLL_BYPASS 0
150#endif
151
152/***************************************Currently Not Being Used *********************************/
153#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
154#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
155#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
156#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
157#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
158
159#if (flash_EBIU_AMBCTL_TT > 3)
160#define flash_EBIU_AMBCTL0_TT B0TT_4
161#endif
162#if (flash_EBIU_AMBCTL_TT == 3)
163#define flash_EBIU_AMBCTL0_TT B0TT_3
164#endif
165#if (flash_EBIU_AMBCTL_TT == 2)
166#define flash_EBIU_AMBCTL0_TT B0TT_2
167#endif
168#if (flash_EBIU_AMBCTL_TT < 2)
169#define flash_EBIU_AMBCTL0_TT B0TT_1
170#endif
171
172#if (flash_EBIU_AMBCTL_ST > 3)
173#define flash_EBIU_AMBCTL0_ST B0ST_4
174#endif
175#if (flash_EBIU_AMBCTL_ST == 3)
176#define flash_EBIU_AMBCTL0_ST B0ST_3
177#endif
178#if (flash_EBIU_AMBCTL_ST == 2)
179#define flash_EBIU_AMBCTL0_ST B0ST_2
180#endif
181#if (flash_EBIU_AMBCTL_ST < 2)
182#define flash_EBIU_AMBCTL0_ST B0ST_1
183#endif
184
185#if (flash_EBIU_AMBCTL_HT > 2)
186#define flash_EBIU_AMBCTL0_HT B0HT_3
187#endif
188#if (flash_EBIU_AMBCTL_HT == 2)
189#define flash_EBIU_AMBCTL0_HT B0HT_2
190#endif
191#if (flash_EBIU_AMBCTL_HT == 1)
192#define flash_EBIU_AMBCTL0_HT B0HT_1
193#endif
194#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
195#define flash_EBIU_AMBCTL0_HT B0HT_0
196#endif
197#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
198#define flash_EBIU_AMBCTL0_HT B0HT_1
199#endif
200
201#if (flash_EBIU_AMBCTL_WAT > 14)
202#define flash_EBIU_AMBCTL0_WAT B0WAT_15
203#endif
204#if (flash_EBIU_AMBCTL_WAT == 14)
205#define flash_EBIU_AMBCTL0_WAT B0WAT_14
206#endif
207#if (flash_EBIU_AMBCTL_WAT == 13)
208#define flash_EBIU_AMBCTL0_WAT B0WAT_13
209#endif
210#if (flash_EBIU_AMBCTL_WAT == 12)
211#define flash_EBIU_AMBCTL0_WAT B0WAT_12
212#endif
213#if (flash_EBIU_AMBCTL_WAT == 11)
214#define flash_EBIU_AMBCTL0_WAT B0WAT_11
215#endif
216#if (flash_EBIU_AMBCTL_WAT == 10)
217#define flash_EBIU_AMBCTL0_WAT B0WAT_10
218#endif
219#if (flash_EBIU_AMBCTL_WAT == 9)
220#define flash_EBIU_AMBCTL0_WAT B0WAT_9
221#endif
222#if (flash_EBIU_AMBCTL_WAT == 8)
223#define flash_EBIU_AMBCTL0_WAT B0WAT_8
224#endif
225#if (flash_EBIU_AMBCTL_WAT == 7)
226#define flash_EBIU_AMBCTL0_WAT B0WAT_7
227#endif
228#if (flash_EBIU_AMBCTL_WAT == 6)
229#define flash_EBIU_AMBCTL0_WAT B0WAT_6
230#endif
231#if (flash_EBIU_AMBCTL_WAT == 5)
232#define flash_EBIU_AMBCTL0_WAT B0WAT_5
233#endif
234#if (flash_EBIU_AMBCTL_WAT == 4)
235#define flash_EBIU_AMBCTL0_WAT B0WAT_4
236#endif
237#if (flash_EBIU_AMBCTL_WAT == 3)
238#define flash_EBIU_AMBCTL0_WAT B0WAT_3
239#endif
240#if (flash_EBIU_AMBCTL_WAT == 2)
241#define flash_EBIU_AMBCTL0_WAT B0WAT_2
242#endif
243#if (flash_EBIU_AMBCTL_WAT == 1)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_1
245#endif
246
247#if (flash_EBIU_AMBCTL_RAT > 14)
248#define flash_EBIU_AMBCTL0_RAT B0RAT_15
249#endif
250#if (flash_EBIU_AMBCTL_RAT == 14)
251#define flash_EBIU_AMBCTL0_RAT B0RAT_14
252#endif
253#if (flash_EBIU_AMBCTL_RAT == 13)
254#define flash_EBIU_AMBCTL0_RAT B0RAT_13
255#endif
256#if (flash_EBIU_AMBCTL_RAT == 12)
257#define flash_EBIU_AMBCTL0_RAT B0RAT_12
258#endif
259#if (flash_EBIU_AMBCTL_RAT == 11)
260#define flash_EBIU_AMBCTL0_RAT B0RAT_11
261#endif
262#if (flash_EBIU_AMBCTL_RAT == 10)
263#define flash_EBIU_AMBCTL0_RAT B0RAT_10
264#endif
265#if (flash_EBIU_AMBCTL_RAT == 9)
266#define flash_EBIU_AMBCTL0_RAT B0RAT_9
267#endif
268#if (flash_EBIU_AMBCTL_RAT == 8)
269#define flash_EBIU_AMBCTL0_RAT B0RAT_8
270#endif
271#if (flash_EBIU_AMBCTL_RAT == 7)
272#define flash_EBIU_AMBCTL0_RAT B0RAT_7
273#endif
274#if (flash_EBIU_AMBCTL_RAT == 6)
275#define flash_EBIU_AMBCTL0_RAT B0RAT_6
276#endif
277#if (flash_EBIU_AMBCTL_RAT == 5)
278#define flash_EBIU_AMBCTL0_RAT B0RAT_5
279#endif
280#if (flash_EBIU_AMBCTL_RAT == 4)
281#define flash_EBIU_AMBCTL0_RAT B0RAT_4
282#endif
283#if (flash_EBIU_AMBCTL_RAT == 3)
284#define flash_EBIU_AMBCTL0_RAT B0RAT_3
285#endif
286#if (flash_EBIU_AMBCTL_RAT == 2)
287#define flash_EBIU_AMBCTL0_RAT B0RAT_2
288#endif
289#if (flash_EBIU_AMBCTL_RAT == 1)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_1
291#endif
292
293#define flash_EBIU_AMBCTL0 \
294 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
295 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 05:53:10 -0500