diff options
author | Mike Frysinger <michael.frysinger@analog.com> | 2007-10-10 12:22:35 -0400 |
---|---|---|
committer | Bryan Wu <bryan.wu@analog.com> | 2007-10-10 12:22:35 -0400 |
commit | 168f1212c098727f2509fe0f66bd30d7209a8159 (patch) | |
tree | e749898e8ab56131a12d8fc489081321abb3ff2f /arch/blackfin/mach-bf561 | |
parent | 27d875f2c134c4b26860ccdd03b4c52cce4efc2c (diff) |
Blackfin arch: rewrite our reboot code in C
rewrite our reboot code in C rather than assembly to be like
other architectures and to allow board maintainers to define
custom behavior
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf561')
-rw-r--r-- | arch/blackfin/mach-bf561/head.S | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S index 139f4cff801b..fd39891ae0fe 100644 --- a/arch/blackfin/mach-bf561/head.S +++ b/arch/blackfin/mach-bf561/head.S | |||
@@ -406,66 +406,6 @@ ENTRY(_start_dma_code) | |||
406 | ENDPROC(_start_dma_code) | 406 | ENDPROC(_start_dma_code) |
407 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | 407 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ |
408 | 408 | ||
409 | ENTRY(_bfin_reset) | ||
410 | /* No more interrupts to be handled*/ | ||
411 | CLI R6; | ||
412 | SSYNC; | ||
413 | |||
414 | #if defined(CONFIG_BFIN_SHARED_FLASH_ENET) | ||
415 | p0.h = hi(FIO_INEN); | ||
416 | p0.l = lo(FIO_INEN); | ||
417 | r0.l = ~(PF1 | PF0); | ||
418 | w[p0] = r0.l; | ||
419 | |||
420 | p0.h = hi(FIO_DIR); | ||
421 | p0.l = lo(FIO_DIR); | ||
422 | r0.l = (PF1 | PF0); | ||
423 | w[p0] = r0.l; | ||
424 | |||
425 | p0.h = hi(FIO_FLAG_C); | ||
426 | p0.l = lo(FIO_FLAG_C); | ||
427 | r0.l = (PF1 | PF0); | ||
428 | w[p0] = r0.l; | ||
429 | #endif | ||
430 | |||
431 | /* Clear the IMASK register */ | ||
432 | p0.h = hi(IMASK); | ||
433 | p0.l = lo(IMASK); | ||
434 | r0 = 0x0; | ||
435 | [p0] = r0; | ||
436 | |||
437 | /* Clear the ILAT register */ | ||
438 | p0.h = hi(ILAT); | ||
439 | p0.l = lo(ILAT); | ||
440 | r0 = [p0]; | ||
441 | [p0] = r0; | ||
442 | SSYNC; | ||
443 | |||
444 | /* make sure SYSCR is set to use BMODE */ | ||
445 | P0.h = hi(SYSCR); | ||
446 | P0.l = lo(SYSCR); | ||
447 | R0.l = 0x20; /* on BF561, disable core b */ | ||
448 | W[P0] = R0.l; | ||
449 | SSYNC; | ||
450 | |||
451 | /* issue a system soft reset */ | ||
452 | P1.h = hi(SWRST); | ||
453 | P1.l = lo(SWRST); | ||
454 | R1.l = 0x0007; | ||
455 | W[P1] = R1; | ||
456 | SSYNC; | ||
457 | |||
458 | /* clear system soft reset */ | ||
459 | R0.l = 0x0000; | ||
460 | W[P0] = R0; | ||
461 | SSYNC; | ||
462 | |||
463 | /* issue core reset */ | ||
464 | raise 1; | ||
465 | |||
466 | RTS; | ||
467 | ENDPROC(_bfin_reset) | ||
468 | |||
469 | .data | 409 | .data |
470 | 410 | ||
471 | /* | 411 | /* |