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authorMike Frysinger <vapier.adi@gmail.com>2008-08-06 05:17:10 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-06 05:17:10 -0400
commit7e64acabfdb530b1b7d3db2592d75d102827baf3 (patch)
tree9cd5d29f86a700fa474f063462bad928d292b567 /arch/blackfin/mach-bf561
parent1375204611f417541e55ee09e248acdbbb94356d (diff)
Blackfin arch: move async memory programming into common setup_arch() as the banks dont really need to be setup fully as early as head.S
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
-rw-r--r--arch/blackfin/mach-bf561/head.S22
1 files changed, 0 insertions, 22 deletions
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 553b2d149d71..c541b312c25d 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -161,28 +161,6 @@ ENTRY(__start)
161 call _start_dma_code; 161 call _start_dma_code;
162#endif 162#endif
163 163
164 /* Code for initializing Async memory banks */
165
166 p2.h = hi(EBIU_AMBCTL1);
167 p2.l = lo(EBIU_AMBCTL1);
168 r0.h = hi(AMBCTL1VAL);
169 r0.l = lo(AMBCTL1VAL);
170 [p2] = r0;
171 ssync;
172
173 p2.h = hi(EBIU_AMBCTL0);
174 p2.l = lo(EBIU_AMBCTL0);
175 r0.h = hi(AMBCTL0VAL);
176 r0.l = lo(AMBCTL0VAL);
177 [p2] = r0;
178 ssync;
179
180 p2.h = hi(EBIU_AMGCTL);
181 p2.l = lo(EBIU_AMGCTL);
182 r0 = AMGCTLVAL;
183 w[p2] = r0;
184 ssync;
185
186 /* This section keeps the processor in supervisor mode 164 /* This section keeps the processor in supervisor mode
187 * during kernel boot. Switches to user mode at end of boot. 165 * during kernel boot. Switches to user mode at end of boot.
188 * See page 3-9 of Hardware Reference manual for documentation. 166 * See page 3-9 of Hardware Reference manual for documentation.