[Blackfin] arch: Resolve the clash issue of UART defines between blackfin headers and include/linux/serial_reg.

Signed-off-by: Graf Yang <graf.yang@analog.com>
Cc: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

1 files changed, 8 insertions, 8 deletions

diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 96a3d456fb6d..279e2e812a27 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -139,26 +139,26 @@ ENTRY(__start)
 
         /* Initialise UART - when booting from u-boot, the UART is not disabled
          * so if we dont initalize here, our serial console gets hosed */
-        p0.h = hi(UART_LCR);
-        p0.l = lo(UART_LCR);
+        p0.h = hi(BFIN_UART_LCR);
+        p0.l = lo(BFIN_UART_LCR);
         r0 = 0x0(Z);
         w[p0] = r0.L;   /* To enable DLL writes */
         ssync;
 
-        p0.h = hi(UART_DLL);
-        p0.l = lo(UART_DLL);
+        p0.h = hi(BFIN_UART_DLL);
+        p0.l = lo(BFIN_UART_DLL);
         r0 = 0x0(Z);
         w[p0] = r0.L;
         ssync;
 
-        p0.h = hi(UART_DLH);
-        p0.l = lo(UART_DLH);
+        p0.h = hi(BFIN_UART_DLH);
+        p0.l = lo(BFIN_UART_DLH);
         r0 = 0x00(Z);
         w[p0] = r0.L;
         ssync;
 
-        p0.h = hi(UART_GCTL);
-        p0.l = lo(UART_GCTL);
+        p0.h = hi(BFIN_UART_GCTL);
+        p0.l = lo(BFIN_UART_GCTL);
         r0 = 0x0(Z);
         w[p0] = r0.L;   /* To enable UART clock */
         ssync;