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authorMike Frysinger <vapier@gentoo.org>2009-09-27 23:16:01 -0400
committerMike Frysinger <vapier@gentoo.org>2011-01-10 07:18:02 -0500
commitb1524e29e318e79b2d04bcbd651a7af8dff32bb3 (patch)
tree7e138995fa0f8727b61fdada567cbda3f95e1670 /arch/blackfin/mach-bf561
parent709465d6ea0466454ef547e7d1065db2b23033a9 (diff)
Blackfin: bfin_serial.h: unify heavily duplicated serial code
Each Blackfin port has been duplicating UART structures and defines when there really is no need for it. So start a new bfin_serial.h header to unify all these pieces and give ourselves a fresh start. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h74
-rw-r--r--arch/blackfin/mach-bf561/include/mach/blackfin.h15
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h77
4 files changed, 16 insertions, 164 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..08072c86d5dc
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 1
13
14#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
index e33e158bc16d..3a6947456cf1 100644
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
20#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
21#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
22#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
25#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
26#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#ifdef CONFIG_BFIN_UART0_CTSRTS 10#ifdef CONFIG_BFIN_UART0_CTSRTS
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39# ifndef CONFIG_UART0_CTS_PIN 12# ifndef CONFIG_UART0_CTS_PIN
@@ -44,51 +17,6 @@
44# endif 17# endif
45#endif 18#endif
46 19
47#define BFIN_UART_TX_FIFO_SIZE 2
48
49struct bfin_serial_port {
50 struct uart_port port;
51 unsigned int old_status;
52 int status_irq;
53 unsigned int lsr;
54#ifdef CONFIG_SERIAL_BFIN_DMA
55 int tx_done;
56 int tx_count;
57 struct circ_buf rx_dma_buf;
58 struct timer_list rx_dma_timer;
59 int rx_dma_nrows;
60 unsigned int tx_dma_channel;
61 unsigned int rx_dma_channel;
62 struct work_struct tx_dma_workqueue;
63#else
64# if ANOMALY_05000363
65 unsigned int anomaly_threshold;
66# endif
67#endif
68#ifdef CONFIG_SERIAL_BFIN_CTSRTS
69 struct timer_list cts_timer;
70 int cts_pin;
71 int rts_pin;
72#endif
73};
74
75/* The hardware clears the LSR bits upon read, so we need to cache
76 * some of the more fun bits in software so they don't get lost
77 * when checking the LSR in other code paths (TX).
78 */
79static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
80{
81 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
82 uart->lsr |= (lsr & (BI|FE|PE|OE));
83 return lsr | uart->lsr;
84}
85
86static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
87{
88 uart->lsr = 0;
89 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
90}
91
92struct bfin_serial_res { 20struct bfin_serial_res {
93 unsigned long uart_base_addr; 21 unsigned long uart_base_addr;
94 int uart_irq; 22 int uart_irq;
@@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
120}; 48};
121 49
122#define DRIVER_NAME "bfin-uart" 50#define DRIVER_NAME "bfin-uart"
51
52#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 6c7dc58c018c..891cb599aa63 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -35,19 +35,4 @@
35#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x)) 35#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
36#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val) 36#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
37 37
38#define BFIN_UART_NR_PORTS 1
39
40#define OFFSET_THR 0x00 /* Transmit Holding register */
41#define OFFSET_RBR 0x00 /* Receive Buffer register */
42#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
43#define OFFSET_IER 0x04 /* Interrupt Enable Register */
44#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
45#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
46#define OFFSET_LCR 0x0C /* Line Control Register */
47#define OFFSET_MCR 0x10 /* Modem Control Register */
48#define OFFSET_LSR 0x14 /* Line Status Register */
49#define OFFSET_MSR 0x18 /* Modem Status Register */
50#define OFFSET_SCR 0x1C /* SCR Scratch Register */
51#define OFFSET_GCTL 0x24 /* Global Control Register */
52
53#endif /* _MACH_BLACKFIN_H_ */ 38#endif /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 79e048d452e0..bfc9180695fe 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -927,83 +927,6 @@
927#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 927#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
928#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ 928#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
929 929
930/* ***************************** UART CONTROLLER MASKS ********************** */
931
932/* UART_LCR Register */
933
934#define DLAB 0x80
935#define SB 0x40
936#define STP 0x20
937#define EPS 0x10
938#define PEN 0x08
939#define STB 0x04
940#define WLS(x) ((x-5) & 0x03)
941
942#define DLAB_P 0x07
943#define SB_P 0x06
944#define STP_P 0x05
945#define EPS_P 0x04
946#define PEN_P 0x03
947#define STB_P 0x02
948#define WLS_P1 0x01
949#define WLS_P0 0x00
950
951/* UART_MCR Register */
952#define LOOP_ENA 0x10
953#define LOOP_ENA_P 0x04
954
955/* UART_LSR Register */
956#define TEMT 0x40
957#define THRE 0x20
958#define BI 0x10
959#define FE 0x08
960#define PE 0x04
961#define OE 0x02
962#define DR 0x01
963
964#define TEMP_P 0x06
965#define THRE_P 0x05
966#define BI_P 0x04
967#define FE_P 0x03
968#define PE_P 0x02
969#define OE_P 0x01
970#define DR_P 0x00
971
972/* UART_IER Register */
973#define ELSI 0x04
974#define ETBEI 0x02
975#define ERBFI 0x01
976
977#define ELSI_P 0x02
978#define ETBEI_P 0x01
979#define ERBFI_P 0x00
980
981/* UART_IIR Register */
982#define STATUS(x) ((x << 1) & 0x06)
983#define NINT 0x01
984#define STATUS_P1 0x02
985#define STATUS_P0 0x01
986#define NINT_P 0x00
987#define IIR_TX_READY 0x02 /* UART_THR empty */
988#define IIR_RX_READY 0x04 /* Receive data ready */
989#define IIR_LINE_CHANGE 0x06 /* Receive line status */
990#define IIR_STATUS 0x06
991
992/* UART_GCTL Register */
993#define FFE 0x20
994#define FPE 0x10
995#define RPOLC 0x08
996#define TPOLC 0x04
997#define IREN 0x02
998#define UCEN 0x01
999
1000#define FFE_P 0x05
1001#define FPE_P 0x04
1002#define RPOLC_P 0x03
1003#define TPOLC_P 0x02
1004#define IREN_P 0x01
1005#define UCEN_P 0x00
1006
1007/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 930/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1008 931
1009/* PPI_CONTROL Masks */ 932/* PPI_CONTROL Masks */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-04 13:07:26 -0500