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authorMike Frysinger <vapier@gentoo.org>2010-05-27 17:47:31 -0400
committerMike Frysinger <vapier@gentoo.org>2010-08-06 12:55:46 -0400
commitdc7101bbaed644e61aa0056ff572b8d7a58e1ef0 (patch)
tree5fb562e5ab4fa556c37ea89f066c4a10cd1559e0 /arch/blackfin/mach-bf561
parent5369fba13611118bc380674a410bede0863566f2 (diff)
Blackfin: update anomaly lists to latest public info
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h13
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 5ddc981e9937..4c108c99cb6e 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -5,7 +5,7 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
@@ -152,8 +152,8 @@
152#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) 152#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
153/* NMI Event at Boot Time Results in Unpredictable State */ 153/* NMI Event at Boot Time Results in Unpredictable State */
154#define ANOMALY_05000219 (__SILICON_REVISION__ < 5) 154#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
155/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ 155/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
156#define ANOMALY_05000220 (__SILICON_REVISION__ < 5) 156#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
157/* Incorrect Pulse-Width of UART Start Bit */ 157/* Incorrect Pulse-Width of UART Start Bit */
158#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) 158#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
159/* Scratchpad Memory Bank Reads May Return Incorrect Data */ 159/* Scratchpad Memory Bank Reads May Return Incorrect Data */
@@ -290,10 +290,14 @@
290#define ANOMALY_05000461 (1) 290#define ANOMALY_05000461 (1)
291/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 291/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
292#define ANOMALY_05000473 (1) 292#define ANOMALY_05000473 (1)
293/* Core Hang With L2/L3 Configured in Writeback Cache Mode */ 293/* Possible Lockup Condition whem Modifying PLL from External Memory */
294#define ANOMALY_05000475 (__SILICON_REVISION__ < 4) 294#define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
295/* TESTSET Instruction Cannot Be Interrupted */ 295/* TESTSET Instruction Cannot Be Interrupted */
296#define ANOMALY_05000477 (1) 296#define ANOMALY_05000477 (1)
297/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
298#define ANOMALY_05000481 (1)
299/* IFLUSH sucks at life */
300#define ANOMALY_05000491 (1)
297 301
298/* Anomalies that don't exist on this proc */ 302/* Anomalies that don't exist on this proc */
299#define ANOMALY_05000119 (0) 303#define ANOMALY_05000119 (0)
@@ -319,5 +323,6 @@
319#define ANOMALY_05000465 (0) 323#define ANOMALY_05000465 (0)
320#define ANOMALY_05000467 (0) 324#define ANOMALY_05000467 (0)
321#define ANOMALY_05000474 (0) 325#define ANOMALY_05000474 (0)
326#define ANOMALY_05000485 (0)
322 327
323#endif 328#endif