diff options
author | Yi Li <yi.li@analog.com> | 2009-08-05 06:02:14 -0400 |
---|---|---|
committer | Mike Frysinger <vapier@gentoo.org> | 2009-09-16 22:10:16 -0400 |
commit | bd411b15cc4b3f31f67d15e1afffbd1ec650d5b8 (patch) | |
tree | 658a99ef56dbd2c20a7a46a00c181f87059bb753 /arch/blackfin/mach-bf561 | |
parent | f1cb64625c4f5309747b8067a309e0bcc630b303 (diff) |
Blackfin: update anomaly lists
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
-rw-r--r-- | arch/blackfin/mach-bf561/include/mach/anomaly.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index a5312b2d267e..70da495c9665 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h | |||
@@ -262,6 +262,8 @@ | |||
262 | #define ANOMALY_05000366 (1) | 262 | #define ANOMALY_05000366 (1) |
263 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | 263 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
264 | #define ANOMALY_05000371 (1) | 264 | #define ANOMALY_05000371 (1) |
265 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ | ||
266 | #define ANOMALY_05000402 (__SILICON_REVISION__ == 4) | ||
265 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | 267 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
266 | #define ANOMALY_05000403 (1) | 268 | #define ANOMALY_05000403 (1) |
267 | /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ | 269 | /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ |