diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2011-03-30 03:59:00 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-05-25 08:13:42 -0400 |
| commit | 3dd666067d2b285724c828946e83100ea4c43d4b (patch) | |
| tree | bb0e0c060013e12a7d6674f8139a5fec59cf6fbc /arch/blackfin/mach-bf561 | |
| parent | 6adc521e7127732512ebd7fcfd3926d7970a82e1 (diff) | |
Blackfin: clean up style in irq defines
These files had a lot of whitespace damage, mostly due to copying and
pasting original files that had damage.
The BF561 header also had a lot of unused CONFIG_DEF_xxx defines, so
punt them all.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/irq.h | 379 |
1 files changed, 154 insertions, 225 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h index aa8f5953a1ac..391091efcfe3 100644 --- a/arch/blackfin/mach-bf561/include/mach/irq.h +++ b/arch/blackfin/mach-bf561/include/mach/irq.h | |||
| @@ -9,106 +9,97 @@ | |||
| 9 | 9 | ||
| 10 | #include <mach-common/irq.h> | 10 | #include <mach-common/irq.h> |
| 11 | 11 | ||
| 12 | #define SYS_IRQS 71 | 12 | #define NR_PERI_INTS (2 * 32) |
| 13 | #define NR_PERI_INTS 64 | ||
| 14 | 13 | ||
| 15 | #define IVG_BASE 7 | 14 | #define IVG_BASE 7 |
| 16 | /* IVG 7 */ | 15 | #define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */ |
| 17 | #define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */ | 16 | #define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */ |
| 18 | #define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */ | 17 | #define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */ |
| 19 | #define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */ | 18 | #define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */ |
| 20 | #define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */ | 19 | #define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */ |
| 21 | #define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */ | 20 | #define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */ |
| 22 | #define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */ | 21 | #define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */ |
| 23 | #define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */ | 22 | #define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */ |
| 24 | #define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */ | 23 | #define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */ |
| 25 | #define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */ | 24 | #define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */ |
| 26 | #define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */ | 25 | #define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */ |
| 27 | #define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */ | 26 | #define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */ |
| 28 | #define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */ | 27 | #define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed */ |
| 29 | #define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */ | 28 | #define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */ |
| 30 | /* IVG 8 */ | 29 | #define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ |
| 31 | #define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */ | 30 | #define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ |
| 32 | #define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ | 31 | #define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */ |
| 33 | #define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ | 32 | #define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */ |
| 34 | #define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */ | 33 | #define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */ |
| 35 | #define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */ | 34 | #define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */ |
| 36 | #define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */ | 35 | #define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */ |
| 37 | #define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */ | 36 | #define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */ |
| 38 | #define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */ | 37 | #define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */ |
| 39 | #define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */ | 38 | #define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */ |
| 40 | #define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */ | 39 | #define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */ |
| 41 | #define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */ | 40 | #define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */ |
| 42 | #define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */ | 41 | #define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */ |
| 43 | #define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */ | 42 | #define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */ |
| 44 | #define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */ | 43 | #define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */ |
| 45 | #define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */ | 44 | #define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */ |
| 46 | /* IVG 9 */ | 45 | #define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */ |
| 47 | #define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */ | 46 | #define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */ |
| 48 | #define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */ | 47 | #define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */ |
| 49 | #define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */ | 48 | #define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */ |
| 50 | #define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */ | 49 | #define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */ |
| 51 | #define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */ | 50 | #define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */ |
| 52 | #define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */ | 51 | #define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */ |
| 53 | #define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */ | 52 | #define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */ |
| 54 | #define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */ | 53 | #define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */ |
| 55 | #define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */ | 54 | #define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */ |
| 56 | #define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */ | 55 | #define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */ |
| 57 | #define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */ | 56 | #define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */ |
| 58 | #define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */ | 57 | #define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */ |
| 59 | #define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */ | 58 | #define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */ |
| 60 | #define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */ | 59 | #define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */ |
| 61 | #define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */ | 60 | #define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */ |
| 62 | #define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */ | 61 | #define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */ |
| 63 | #define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */ | 62 | #define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */ |
| 64 | #define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */ | 63 | #define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */ |
| 65 | #define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */ | 64 | #define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */ |
| 66 | /* IVG 10 */ | 65 | #define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */ |
| 67 | #define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */ | 66 | #define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */ |
| 68 | #define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */ | 67 | #define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */ |
| 69 | #define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */ | 68 | #define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */ |
| 70 | #define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */ | 69 | #define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */ |
| 71 | #define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */ | 70 | #define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */ |
| 72 | #define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */ | 71 | #define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */ |
| 73 | #define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */ | 72 | #define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */ |
| 74 | #define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */ | 73 | #define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */ |
| 75 | #define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */ | 74 | #define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */ |
| 76 | #define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */ | 75 | #define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */ |
| 77 | #define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */ | 76 | #define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */ |
| 78 | #define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */ | 77 | #define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */ |
| 79 | /* IVG 11 */ | 78 | #define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */ |
| 80 | #define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */ | 79 | #define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */ |
| 81 | #define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */ | 80 | #define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */ |
| 82 | #define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */ | 81 | #define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */ |
| 83 | #define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */ | 82 | #define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */ |
| 84 | #define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */ | 83 | #define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */ |
| 85 | #define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */ | ||
| 86 | #define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */ | ||
| 87 | #define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */ | ||
| 88 | /* IVG 8 */ | ||
| 89 | #define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */ | ||
| 90 | #define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */ | ||
| 91 | #define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0 | 84 | #define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0 |
| 92 | #define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */ | 85 | #define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */ |
| 93 | #define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */ | 86 | #define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */ |
| 94 | #define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1 | 87 | #define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1 |
| 95 | /* IVG 9 */ | 88 | #define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */ |
| 96 | #define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */ | ||
| 97 | #define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0 | 89 | #define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0 |
| 98 | #define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */ | 90 | #define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */ |
| 99 | #define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1 | 91 | #define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1 |
| 100 | /* IVG 12 */ | 92 | #define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */ |
| 101 | #define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */ | ||
| 102 | #define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0 | 93 | #define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0 |
| 103 | #define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */ | 94 | #define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */ |
| 104 | #define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1 | 95 | #define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1 |
| 105 | /* IVG 13 */ | 96 | #define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */ |
| 106 | #define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */ | 97 | #define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */ |
| 107 | /* IVG 7 */ | 98 | #define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */ |
| 108 | #define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */ | ||
| 109 | #define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */ | ||
| 110 | #define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ | 99 | #define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ |
| 111 | #define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */ | 100 | #define IRQ_SUPPLE_1 (IVG_BASE + 63) /* Supplemental interrupt 1 */ |
| 101 | |||
| 102 | #define SYS_IRQS 71 | ||
| 112 | 103 | ||
| 113 | #define IRQ_PF0 73 | 104 | #define IRQ_PF0 73 |
| 114 | #define IRQ_PF1 74 | 105 | #define IRQ_PF1 74 |
| @@ -163,146 +154,84 @@ | |||
| 163 | 154 | ||
| 164 | #define NR_MACH_IRQS (IRQ_PF47 + 1) | 155 | #define NR_MACH_IRQS (IRQ_PF47 + 1) |
| 165 | 156 | ||
| 166 | /* | ||
| 167 | * DEFAULT PRIORITIES: | ||
| 168 | */ | ||
| 169 | |||
| 170 | #define CONFIG_DEF_PLL_WAKEUP 7 | ||
| 171 | #define CONFIG_DEF_DMA1_ERROR 7 | ||
| 172 | #define CONFIG_DEF_DMA2_ERROR 7 | ||
| 173 | #define CONFIG_DEF_IMDMA_ERROR 7 | ||
| 174 | #define CONFIG_DEF_PPI1_ERROR 7 | ||
| 175 | #define CONFIG_DEF_PPI2_ERROR 7 | ||
| 176 | #define CONFIG_DEF_SPORT0_ERROR 7 | ||
| 177 | #define CONFIG_DEF_SPORT1_ERROR 7 | ||
| 178 | #define CONFIG_DEF_SPI_ERROR 7 | ||
| 179 | #define CONFIG_DEF_UART_ERROR 7 | ||
| 180 | #define CONFIG_DEF_RESERVED_ERROR 7 | ||
| 181 | #define CONFIG_DEF_DMA1_0 8 | ||
| 182 | #define CONFIG_DEF_DMA1_1 8 | ||
| 183 | #define CONFIG_DEF_DMA1_2 8 | ||
| 184 | #define CONFIG_DEF_DMA1_3 8 | ||
| 185 | #define CONFIG_DEF_DMA1_4 8 | ||
| 186 | #define CONFIG_DEF_DMA1_5 8 | ||
| 187 | #define CONFIG_DEF_DMA1_6 8 | ||
| 188 | #define CONFIG_DEF_DMA1_7 8 | ||
| 189 | #define CONFIG_DEF_DMA1_8 8 | ||
| 190 | #define CONFIG_DEF_DMA1_9 8 | ||
| 191 | #define CONFIG_DEF_DMA1_10 8 | ||
| 192 | #define CONFIG_DEF_DMA1_11 8 | ||
| 193 | #define CONFIG_DEF_DMA2_0 9 | ||
| 194 | #define CONFIG_DEF_DMA2_1 9 | ||
| 195 | #define CONFIG_DEF_DMA2_2 9 | ||
| 196 | #define CONFIG_DEF_DMA2_3 9 | ||
| 197 | #define CONFIG_DEF_DMA2_4 9 | ||
| 198 | #define CONFIG_DEF_DMA2_5 9 | ||
| 199 | #define CONFIG_DEF_DMA2_6 9 | ||
| 200 | #define CONFIG_DEF_DMA2_7 9 | ||
| 201 | #define CONFIG_DEF_DMA2_8 9 | ||
| 202 | #define CONFIG_DEF_DMA2_9 9 | ||
| 203 | #define CONFIG_DEF_DMA2_10 9 | ||
| 204 | #define CONFIG_DEF_DMA2_11 9 | ||
| 205 | #define CONFIG_DEF_TIMER0 10 | ||
| 206 | #define CONFIG_DEF_TIMER1 10 | ||
| 207 | #define CONFIG_DEF_TIMER2 10 | ||
| 208 | #define CONFIG_DEF_TIMER3 10 | ||
| 209 | #define CONFIG_DEF_TIMER4 10 | ||
| 210 | #define CONFIG_DEF_TIMER5 10 | ||
| 211 | #define CONFIG_DEF_TIMER6 10 | ||
| 212 | #define CONFIG_DEF_TIMER7 10 | ||
| 213 | #define CONFIG_DEF_TIMER8 10 | ||
| 214 | #define CONFIG_DEF_TIMER9 10 | ||
| 215 | #define CONFIG_DEF_TIMER10 10 | ||
| 216 | #define CONFIG_DEF_TIMER11 10 | ||
| 217 | #define CONFIG_DEF_PROG0_INTA 11 | ||
| 218 | #define CONFIG_DEF_PROG0_INTB 11 | ||
| 219 | #define CONFIG_DEF_PROG1_INTA 11 | ||
| 220 | #define CONFIG_DEF_PROG1_INTB 11 | ||
| 221 | #define CONFIG_DEF_PROG2_INTA 11 | ||
| 222 | #define CONFIG_DEF_PROG2_INTB 11 | ||
| 223 | #define CONFIG_DEF_DMA1_WRRD0 8 | ||
| 224 | #define CONFIG_DEF_DMA1_WRRD1 8 | ||
| 225 | #define CONFIG_DEF_DMA2_WRRD0 9 | ||
| 226 | #define CONFIG_DEF_DMA2_WRRD1 9 | ||
| 227 | #define CONFIG_DEF_IMDMA_WRRD0 12 | ||
| 228 | #define CONFIG_DEF_IMDMA_WRRD1 12 | ||
| 229 | #define CONFIG_DEF_WATCH 13 | ||
| 230 | #define CONFIG_DEF_RESERVED_1 7 | ||
| 231 | #define CONFIG_DEF_RESERVED_2 7 | ||
| 232 | #define CONFIG_DEF_SUPPLE_0 7 | ||
| 233 | #define CONFIG_DEF_SUPPLE_1 7 | ||
| 234 | |||
| 235 | /* IAR0 BIT FIELDS */ | 157 | /* IAR0 BIT FIELDS */ |
| 236 | #define IRQ_PLL_WAKEUP_POS 0 | 158 | #define IRQ_PLL_WAKEUP_POS 0 |
| 237 | #define IRQ_DMA1_ERROR_POS 4 | 159 | #define IRQ_DMA1_ERROR_POS 4 |
| 238 | #define IRQ_DMA2_ERROR_POS 8 | 160 | #define IRQ_DMA2_ERROR_POS 8 |
| 239 | #define IRQ_IMDMA_ERROR_POS 12 | 161 | #define IRQ_IMDMA_ERROR_POS 12 |
| 240 | #define IRQ_PPI0_ERROR_POS 16 | 162 | #define IRQ_PPI0_ERROR_POS 16 |
| 241 | #define IRQ_PPI1_ERROR_POS 20 | 163 | #define IRQ_PPI1_ERROR_POS 20 |
| 242 | #define IRQ_SPORT0_ERROR_POS 24 | 164 | #define IRQ_SPORT0_ERROR_POS 24 |
| 243 | #define IRQ_SPORT1_ERROR_POS 28 | 165 | #define IRQ_SPORT1_ERROR_POS 28 |
| 166 | |||
| 244 | /* IAR1 BIT FIELDS */ | 167 | /* IAR1 BIT FIELDS */ |
| 245 | #define IRQ_SPI_ERROR_POS 0 | 168 | #define IRQ_SPI_ERROR_POS 0 |
| 246 | #define IRQ_UART_ERROR_POS 4 | 169 | #define IRQ_UART_ERROR_POS 4 |
| 247 | #define IRQ_RESERVED_ERROR_POS 8 | 170 | #define IRQ_RESERVED_ERROR_POS 8 |
| 248 | #define IRQ_DMA1_0_POS 12 | 171 | #define IRQ_DMA1_0_POS 12 |
| 249 | #define IRQ_DMA1_1_POS 16 | 172 | #define IRQ_DMA1_1_POS 16 |
| 250 | #define IRQ_DMA1_2_POS 20 | 173 | #define IRQ_DMA1_2_POS 20 |
| 251 | #define IRQ_DMA1_3_POS 24 | 174 | #define IRQ_DMA1_3_POS 24 |
| 252 | #define IRQ_DMA1_4_POS 28 | 175 | #define IRQ_DMA1_4_POS 28 |
| 176 | |||
| 253 | /* IAR2 BIT FIELDS */ | 177 | /* IAR2 BIT FIELDS */ |
| 254 | #define IRQ_DMA1_5_POS 0 | 178 | #define IRQ_DMA1_5_POS 0 |
| 255 | #define IRQ_DMA1_6_POS 4 | 179 | #define IRQ_DMA1_6_POS 4 |
| 256 | #define IRQ_DMA1_7_POS 8 | 180 | #define IRQ_DMA1_7_POS 8 |
| 257 | #define IRQ_DMA1_8_POS 12 | 181 | #define IRQ_DMA1_8_POS 12 |
| 258 | #define IRQ_DMA1_9_POS 16 | 182 | #define IRQ_DMA1_9_POS 16 |
| 259 | #define IRQ_DMA1_10_POS 20 | 183 | #define IRQ_DMA1_10_POS 20 |
| 260 | #define IRQ_DMA1_11_POS 24 | 184 | #define IRQ_DMA1_11_POS 24 |
| 261 | #define IRQ_DMA2_0_POS 28 | 185 | #define IRQ_DMA2_0_POS 28 |
| 186 | |||
| 262 | /* IAR3 BIT FIELDS */ | 187 | /* IAR3 BIT FIELDS */ |
| 263 | #define IRQ_DMA2_1_POS 0 | 188 | #define IRQ_DMA2_1_POS 0 |
| 264 | #define IRQ_DMA2_2_POS 4 | 189 | #define IRQ_DMA2_2_POS 4 |
| 265 | #define IRQ_DMA2_3_POS 8 | 190 | #define IRQ_DMA2_3_POS 8 |
| 266 | #define IRQ_DMA2_4_POS 12 | 191 | #define IRQ_DMA2_4_POS 12 |
| 267 | #define IRQ_DMA2_5_POS 16 | 192 | #define IRQ_DMA2_5_POS 16 |
| 268 | #define IRQ_DMA2_6_POS 20 | 193 | #define IRQ_DMA2_6_POS 20 |
| 269 | #define IRQ_DMA2_7_POS 24 | 194 | #define IRQ_DMA2_7_POS 24 |
| 270 | #define IRQ_DMA2_8_POS 28 | 195 | #define IRQ_DMA2_8_POS 28 |
| 196 | |||
| 271 | /* IAR4 BIT FIELDS */ | 197 | /* IAR4 BIT FIELDS */ |
| 272 | #define IRQ_DMA2_9_POS 0 | 198 | #define IRQ_DMA2_9_POS 0 |
| 273 | #define IRQ_DMA2_10_POS 4 | 199 | #define IRQ_DMA2_10_POS 4 |
| 274 | #define IRQ_DMA2_11_POS 8 | 200 | #define IRQ_DMA2_11_POS 8 |
| 275 | #define IRQ_TIMER0_POS 12 | 201 | #define IRQ_TIMER0_POS 12 |
| 276 | #define IRQ_TIMER1_POS 16 | 202 | #define IRQ_TIMER1_POS 16 |
| 277 | #define IRQ_TIMER2_POS 20 | 203 | #define IRQ_TIMER2_POS 20 |
| 278 | #define IRQ_TIMER3_POS 24 | 204 | #define IRQ_TIMER3_POS 24 |
| 279 | #define IRQ_TIMER4_POS 28 | 205 | #define IRQ_TIMER4_POS 28 |
| 206 | |||
| 280 | /* IAR5 BIT FIELDS */ | 207 | /* IAR5 BIT FIELDS */ |
| 281 | #define IRQ_TIMER5_POS 0 | 208 | #define IRQ_TIMER5_POS 0 |
| 282 | #define IRQ_TIMER6_POS 4 | 209 | #define IRQ_TIMER6_POS 4 |
| 283 | #define IRQ_TIMER7_POS 8 | 210 | #define IRQ_TIMER7_POS 8 |
| 284 | #define IRQ_TIMER8_POS 12 | 211 | #define IRQ_TIMER8_POS 12 |
| 285 | #define IRQ_TIMER9_POS 16 | 212 | #define IRQ_TIMER9_POS 16 |
| 286 | #define IRQ_TIMER10_POS 20 | 213 | #define IRQ_TIMER10_POS 20 |
| 287 | #define IRQ_TIMER11_POS 24 | 214 | #define IRQ_TIMER11_POS 24 |
| 288 | #define IRQ_PROG0_INTA_POS 28 | 215 | #define IRQ_PROG0_INTA_POS 28 |
| 216 | |||
| 289 | /* IAR6 BIT FIELDS */ | 217 | /* IAR6 BIT FIELDS */ |
| 290 | #define IRQ_PROG0_INTB_POS 0 | 218 | #define IRQ_PROG0_INTB_POS 0 |
| 291 | #define IRQ_PROG1_INTA_POS 4 | 219 | #define IRQ_PROG1_INTA_POS 4 |
| 292 | #define IRQ_PROG1_INTB_POS 8 | 220 | #define IRQ_PROG1_INTB_POS 8 |
| 293 | #define IRQ_PROG2_INTA_POS 12 | 221 | #define IRQ_PROG2_INTA_POS 12 |
| 294 | #define IRQ_PROG2_INTB_POS 16 | 222 | #define IRQ_PROG2_INTB_POS 16 |
| 295 | #define IRQ_DMA1_WRRD0_POS 20 | 223 | #define IRQ_DMA1_WRRD0_POS 20 |
| 296 | #define IRQ_DMA1_WRRD1_POS 24 | 224 | #define IRQ_DMA1_WRRD1_POS 24 |
| 297 | #define IRQ_DMA2_WRRD0_POS 28 | 225 | #define IRQ_DMA2_WRRD0_POS 28 |
| 226 | |||
| 298 | /* IAR7 BIT FIELDS */ | 227 | /* IAR7 BIT FIELDS */ |
| 299 | #define IRQ_DMA2_WRRD1_POS 0 | 228 | #define IRQ_DMA2_WRRD1_POS 0 |
| 300 | #define IRQ_IMDMA_WRRD0_POS 4 | 229 | #define IRQ_IMDMA_WRRD0_POS 4 |
| 301 | #define IRQ_IMDMA_WRRD1_POS 8 | 230 | #define IRQ_IMDMA_WRRD1_POS 8 |
| 302 | #define IRQ_WDTIMER_POS 12 | 231 | #define IRQ_WDTIMER_POS 12 |
| 303 | #define IRQ_RESERVED_1_POS 16 | 232 | #define IRQ_RESERVED_1_POS 16 |
| 304 | #define IRQ_RESERVED_2_POS 20 | 233 | #define IRQ_RESERVED_2_POS 20 |
| 305 | #define IRQ_SUPPLE_0_POS 24 | 234 | #define IRQ_SUPPLE_0_POS 24 |
| 306 | #define IRQ_SUPPLE_1_POS 28 | 235 | #define IRQ_SUPPLE_1_POS 28 |
| 307 | 236 | ||
| 308 | #endif /* _BF561_IRQ_H_ */ | 237 | #endif |