Blackfin: bf561: rewrite SICA_xxx to just SIC_xxx

This matches all the other Blackfin ports and keep us from having to write
bf561-specific code in many places.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

1 files changed, 12 insertions, 12 deletions

diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 3b9a4bf7dacc..f540ed1257d6 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -52,19 +52,19 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
         /* Clone setup for peripheral interrupt sources from CoreA. */
-        bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
-        bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
+        bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
+        bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
         SSYNC();
 
         /* Clone setup for IARs from CoreA. */
-        bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
-        bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
-        bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
-        bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
-        bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
-        bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
-        bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
-        bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
+        bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
+        bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
+        bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
+        bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
+        bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
+        bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
+        bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
+        bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
         bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
         bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
         SSYNC();
@@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
 
         spin_lock(&boot_lock);
 
-        if ((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0) {
+        if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) {
                 /* CoreB already running, sending ipi to wakeup it */
                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
         } else {
                 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
-                bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT);
+                bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT);
                 SSYNC();
         }