Blackfin: bf561: update a few more SIC_SYSCR locations

Looks like I missed a few new spots when renaming the SICA macros.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index f540ed1257d6..be6083a7e42f 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
 
         spin_lock(&boot_lock);
 
-        if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) {
+        if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
                 /* CoreB already running, sending ipi to wakeup it */
                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
         } else {
                 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
-                bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT);
+                bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
                 SSYNC();
         }