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authorMike Frysinger <vapier.adi@gmail.com>2009-01-07 10:14:38 -0500
committerBryan Wu <cooloney@kernel.org>2009-01-07 10:14:38 -0500
commit6651ece9e257302ee695ee76e69a4427f7033235 (patch)
treeee9862184884b179ec89a0a2527a7b56279c1402 /arch/blackfin/mach-bf561/include
parenta0dcfb16e606ca095eb1e9e789aff5e41e9adb1a (diff)
Blackfin arch: update anomaly headers to match latest sheets
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf561/include')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h13
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 4d4884b3c636..1a9e17562821 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List 10 * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -264,6 +264,16 @@
264#define ANOMALY_05000371 (1) 264#define ANOMALY_05000371 (1)
265/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 265/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
266#define ANOMALY_05000403 (1) 266#define ANOMALY_05000403 (1)
267/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
268#define ANOMALY_05000412 (1)
269/* Speculative Fetches Can Cause Undesired External FIFO Operations */
270#define ANOMALY_05000416 (1)
271/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
272#define ANOMALY_05000425 (1)
273/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
274#define ANOMALY_05000426 (1)
275/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
276#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
267/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 277/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
268#define ANOMALY_05000443 (1) 278#define ANOMALY_05000443 (1)
269 279
@@ -274,6 +284,7 @@
274#define ANOMALY_05000311 (0) 284#define ANOMALY_05000311 (0)
275#define ANOMALY_05000353 (1) 285#define ANOMALY_05000353 (1)
276#define ANOMALY_05000386 (1) 286#define ANOMALY_05000386 (1)
287#define ANOMALY_05000432 (0)
277#define ANOMALY_05000435 (0) 288#define ANOMALY_05000435 (0)
278 289
279#endif 290#endif