aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin/mach-bf561/include
diff options
context:
space:
mode:
authorMike Frysinger <vapier@gentoo.org>2010-10-19 14:44:23 -0400
committerMike Frysinger <vapier@gentoo.org>2010-10-22 16:30:02 -0400
commit39c999697bf43a97b877fa43cbc9c2a4d1a3a461 (patch)
treed0f2432e89f7f36f9f2a39aed80527d072273bb0 /arch/blackfin/mach-bf561/include
parent9ebcaa47ba831b6ad5cc414b3c3ff310a9d5d582 (diff)
Blackfin: bf561: rewrite SICA_xxx to just SIC_xxx
This matches all the other Blackfin ports and keep us from having to write bf561-specific code in many places. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561/include')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/blackfin.h33
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h76
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h37
3 files changed, 61 insertions, 85 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 67d6bdcd3fa8..6c7dc58c018c 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -24,29 +24,16 @@
24#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() 24#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
25#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) 25#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
26 26
27#define SIC_IWR0 SICA_IWR0 27/* Weird muxer funcs which pick SIC regs from IMASK base */
28#define SIC_IWR1 SICA_IWR1 28#define __SIC_MUX(base, x) ((base) + ((x) << 2))
29#define SIC_IAR0 SICA_IAR0 29#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))
30#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 30#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
31#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 31#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
32#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0 32#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
33#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1 33#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
34 34#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
35#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0 35#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
36#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1 36#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
37#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
38#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
39#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
40#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
41
42#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
43#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
44#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2))
45#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val)
46#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
47#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
48#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2))
49#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val)
50 37
51#define BFIN_UART_NR_PORTS 1 38#define BFIN_UART_NR_PORTS 1
52 39
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index cc0416a5fa02..2bab99152495 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -30,49 +30,41 @@
30#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) 30#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
31#define bfin_read_CHIPID() bfin_read32(CHIPID) 31#define bfin_read_CHIPID() bfin_read32(CHIPID)
32 32
33/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
34#define bfin_read_SWRST() bfin_read_SICA_SWRST()
35#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
36#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
37#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
38
39/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 33/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
40#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) 34#define bfin_read_SWRST() bfin_read16(SWRST)
41#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) 35#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
42#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) 36#define bfin_read_SYSCR() bfin_read16(SYSCR)
43#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val) 37#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
44#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) 38#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
45#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val) 39#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
46#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK) 40#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
47#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val) 41#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
48#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) 42#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
49#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val) 43#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
50#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) 44#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
51#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val) 45#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
52#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) 46#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
53#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val) 47#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
54#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) 48#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
55#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val) 49#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
56#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) 50#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
57#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val) 51#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
58#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) 52#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
59#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val) 53#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
60#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) 54#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
61#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val) 55#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
62#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) 56#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
63#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val) 57#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
64#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) 58#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
65#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val) 59#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
66#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) 60#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
67#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val) 61#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
68#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) 62#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
69#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val) 63#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val)
70#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) 64#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
71#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val) 65#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
72#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) 66#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
73#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val) 67#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val)
74#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)
75#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val)
76 68
77/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ 69/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
78#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) 70#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 6f59ac669f10..79e048d452e0 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -28,32 +28,29 @@
28#define CHIPID 0xFFC00014 /* Chip ID Register */ 28#define CHIPID 0xFFC00014 /* Chip ID Register */
29 29
30/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ 30/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
31#define SWRST SICA_SWRST
32#define SYSCR SICA_SYSCR
33#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) 31#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
34#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) 32#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
35#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) 33#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
36#define RESET_SOFTWARE (SWRST_OCCURRED) 34#define RESET_SOFTWARE (SWRST_OCCURRED)
37 35
38/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 36/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
39#define SICA_SWRST 0xFFC00100 /* Software Reset register */ 37#define SWRST 0xFFC00100 /* Software Reset register */
40#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ 38#define SYSCR 0xFFC00104 /* System Reset Configuration register */
41#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ 39#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
42#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ 40#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
43#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ 41#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
44#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ 42#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
45#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ 43#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
46#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ 44#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
47#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ 45#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
48#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ 46#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
49#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ 47#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
50#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ 48#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
51#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ 49#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
52#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ 50#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
53#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ 51#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
54#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ 52#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
55#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ 53#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
56#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
57 54
58/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ 55/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
59#define SICB_SWRST 0xFFC01100 /* reserved */ 56#define SICB_SWRST 0xFFC01100 /* reserved */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-13 00:02:17 -0400