diff options
author | Mike Frysinger <vapier@gentoo.org> | 2010-10-19 14:44:23 -0400 |
---|---|---|
committer | Mike Frysinger <vapier@gentoo.org> | 2010-10-22 16:30:02 -0400 |
commit | 39c999697bf43a97b877fa43cbc9c2a4d1a3a461 (patch) | |
tree | d0f2432e89f7f36f9f2a39aed80527d072273bb0 /arch/blackfin/mach-bf561/include/mach/cdefBF561.h | |
parent | 9ebcaa47ba831b6ad5cc414b3c3ff310a9d5d582 (diff) |
Blackfin: bf561: rewrite SICA_xxx to just SIC_xxx
This matches all the other Blackfin ports and keep us from having to write
bf561-specific code in many places.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561/include/mach/cdefBF561.h')
-rw-r--r-- | arch/blackfin/mach-bf561/include/mach/cdefBF561.h | 76 |
1 files changed, 34 insertions, 42 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h index cc0416a5fa02..2bab99152495 100644 --- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h | |||
@@ -30,49 +30,41 @@ | |||
30 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) | 30 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) |
31 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | 31 | #define bfin_read_CHIPID() bfin_read32(CHIPID) |
32 | 32 | ||
33 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ | ||
34 | #define bfin_read_SWRST() bfin_read_SICA_SWRST() | ||
35 | #define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val) | ||
36 | #define bfin_read_SYSCR() bfin_read_SICA_SYSCR() | ||
37 | #define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val) | ||
38 | |||
39 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ | 33 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ |
40 | #define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) | 34 | #define bfin_read_SWRST() bfin_read16(SWRST) |
41 | #define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) | 35 | #define bfin_write_SWRST(val) bfin_write16(SWRST,val) |
42 | #define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) | 36 | #define bfin_read_SYSCR() bfin_read16(SYSCR) |
43 | #define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val) | 37 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) |
44 | #define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) | 38 | #define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) |
45 | #define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val) | 39 | #define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val) |
46 | #define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK) | 40 | #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) |
47 | #define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val) | 41 | #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val) |
48 | #define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) | 42 | #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) |
49 | #define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val) | 43 | #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val) |
50 | #define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) | 44 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) |
51 | #define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val) | 45 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) |
52 | #define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) | 46 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) |
53 | #define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val) | 47 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) |
54 | #define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) | 48 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) |
55 | #define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val) | 49 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) |
56 | #define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) | 50 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) |
57 | #define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val) | 51 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) |
58 | #define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) | 52 | #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) |
59 | #define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val) | 53 | #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val) |
60 | #define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) | 54 | #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) |
61 | #define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val) | 55 | #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val) |
62 | #define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) | 56 | #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) |
63 | #define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val) | 57 | #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val) |
64 | #define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) | 58 | #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) |
65 | #define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val) | 59 | #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val) |
66 | #define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) | 60 | #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) |
67 | #define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val) | 61 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val) |
68 | #define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) | 62 | #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) |
69 | #define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val) | 63 | #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val) |
70 | #define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) | 64 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) |
71 | #define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val) | 65 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val) |
72 | #define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) | 66 | #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) |
73 | #define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val) | 67 | #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val) |
74 | #define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1) | ||
75 | #define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val) | ||
76 | 68 | ||
77 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ | 69 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ |
78 | #define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) | 70 | #define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) |