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authorMike Frysinger <vapier.adi@gmail.com>2008-08-06 05:23:50 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-06 05:23:50 -0400
commit17e89bcfa12f71b840361da07fe6c2f9c48d0605 (patch)
treec5ab94b397bcdfc5ffe0363f24ff83e012e8801a /arch/blackfin/mach-bf561/head.S
parent67618fd8748a5d83f6bdcd578c8e748c3f47c4d4 (diff)
Blackfin arch: unify the duplicated portions of __start and split mach-specific pieces into _mach_early_start where they will be easier to trim over time
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf561/head.S')
-rw-r--r--arch/blackfin/mach-bf561/head.S136
1 files changed, 5 insertions, 131 deletions
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index c541b312c25d..fe6f979947c6 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -30,93 +30,16 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h> 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34
35#if CONFIG_BFIN_KERNEL_CLOCK
36#include <asm/mach-common/clocks.h> 34#include <asm/mach-common/clocks.h>
37#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
38#endif 36#endif
39 37
40.extern ___bss_stop
41.extern ___bss_start
42.extern _bf53x_relocate_l1_mem 38.extern _bf53x_relocate_l1_mem
43 39
44#define INITIAL_STACK 0xFFB01000
45
46__INIT 40__INIT
47 41
48ENTRY(__start) 42ENTRY(_mach_early_start)
49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0;
51 /* Enable Cycle Counter and Nesting Of Interrupts */
52#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
53 R0 = SYSCFG_SNEN;
54#else
55 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
56#endif
57 SYSCFG = R0;
58 R0 = 0;
59
60 /* Clear Out All the data and pointer Registers */
61 R1 = R0;
62 R2 = R0;
63 R3 = R0;
64 R4 = R0;
65 R5 = R0;
66 R6 = R0;
67
68 P0 = R0;
69 P1 = R0;
70 P2 = R0;
71 P3 = R0;
72 P4 = R0;
73 P5 = R0;
74
75 LC0 = r0;
76 LC1 = r0;
77 L0 = r0;
78 L1 = r0;
79 L2 = r0;
80 L3 = r0;
81
82 /* Clear Out All the DAG Registers */
83 B0 = r0;
84 B1 = r0;
85 B2 = r0;
86 B3 = r0;
87
88 I0 = r0;
89 I1 = r0;
90 I2 = r0;
91 I3 = r0;
92
93 M0 = r0;
94 M1 = r0;
95 M2 = r0;
96 M3 = r0;
97
98 trace_buffer_init(p0,r0);
99 P0 = R1;
100 R0 = R1;
101
102 /* Turn off the icache */
103 p0.l = LO(IMEM_CONTROL);
104 p0.h = HI(IMEM_CONTROL);
105 R1 = [p0];
106 R0 = ~ENICPLB;
107 R0 = R0 & R1;
108 [p0] = R0;
109 SSYNC;
110
111 /* Turn off the dcache */
112 p0.l = LO(DMEM_CONTROL);
113 p0.h = HI(DMEM_CONTROL);
114 R1 = [p0];
115 R0 = ~ENDCPLB;
116 R0 = R0 & R1;
117 [p0] = R0;
118 SSYNC;
119
120 /* Initialise UART - when booting from u-boot, the UART is not disabled 43 /* Initialise UART - when booting from u-boot, the UART is not disabled
121 * so if we dont initalize here, our serial console gets hosed */ 44 * so if we dont initalize here, our serial console gets hosed */
122 p0.h = hi(BFIN_UART_LCR); 45 p0.h = hi(BFIN_UART_LCR);
@@ -143,62 +66,13 @@ ENTRY(__start)
143 w[p0] = r0.L; /* To enable UART clock */ 66 w[p0] = r0.L; /* To enable UART clock */
144 ssync; 67 ssync;
145 68
146 /* Initialize stack pointer */ 69 rts;
147 sp.l = lo(INITIAL_STACK); 70ENDPROC(_mach_early_start)
148 sp.h = hi(INITIAL_STACK);
149 fp = sp;
150 usp = sp;
151
152#ifdef CONFIG_EARLY_PRINTK
153 SP += -12;
154 call _init_early_exception_vectors;
155 SP += 12;
156#endif
157
158 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
159 call _bf53x_relocate_l1_mem;
160#if CONFIG_BFIN_KERNEL_CLOCK
161 call _start_dma_code;
162#endif
163
164 /* This section keeps the processor in supervisor mode
165 * during kernel boot. Switches to user mode at end of boot.
166 * See page 3-9 of Hardware Reference manual for documentation.
167 */
168
169 /* EVT15 = _real_start */
170
171 p0.l = lo(EVT15);
172 p0.h = hi(EVT15);
173 p1.l = _real_start;
174 p1.h = _real_start;
175 [p0] = p1;
176 csync;
177
178 p0.l = lo(IMASK);
179 p0.h = hi(IMASK);
180 p1.l = IMASK_IVG15;
181 p1.h = 0x0;
182 [p0] = p1;
183 csync;
184
185 raise 15;
186 p0.l = .LWAIT_HERE;
187 p0.h = .LWAIT_HERE;
188 reti = p0;
189#if ANOMALY_05000281
190 nop; nop; nop;
191#endif
192 rti;
193
194.LWAIT_HERE:
195 jump .LWAIT_HERE;
196ENDPROC(__start)
197 71
198__FINIT 72__FINIT
199 73
200.section .l1.text 74.section .l1.text
201#if CONFIG_BFIN_KERNEL_CLOCK 75#ifdef CONFIG_BFIN_KERNEL_CLOCK
202ENTRY(_start_dma_code) 76ENTRY(_start_dma_code)
203 p0.h = hi(SICA_IWR0); 77 p0.h = hi(SICA_IWR0);
204 p0.l = lo(SICA_IWR0); 78 p0.l = lo(SICA_IWR0);