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authorMike Frysinger <vapier@gentoo.org>2009-09-27 23:16:01 -0400
committerMike Frysinger <vapier@gentoo.org>2011-01-10 07:18:02 -0500
commitb1524e29e318e79b2d04bcbd651a7af8dff32bb3 (patch)
tree7e138995fa0f8727b61fdada567cbda3f95e1670 /arch/blackfin/mach-bf548
parent709465d6ea0466454ef547e7d1065db2b23033a9 (diff)
Blackfin: bfin_serial.h: unify heavily duplicated serial code
Each Blackfin port has been duplicating UART structures and defines when there really is no need for it. So start a new bfin_serial.h header to unify all these pieces and give ourselves a fresh start. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548')
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_serial.h16
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h60
-rw-r--r--arch/blackfin/mach-bf548/include/mach/blackfin.h15
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h71
4 files changed, 18 insertions, 144 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..a77109f99720
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
@@ -0,0 +1,16 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 4
13
14#define BFIN_UART_BF54X_STYLE
15
16#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
index dd44aa75fe72..0d94edaaaa2e 100644
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
@@ -4,72 +4,14 @@
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
14#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
15#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
16#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18#define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR))
19#define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR))
20
21#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
22#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
23#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
24#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
25#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
26#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
27#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
28#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
29#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
30#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
31#define UART_CLEAR_SCTS(uart) bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS)
32
33#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
34#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
35
36#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
37#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS))
38#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
39#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
40#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
41
42#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \ 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
43 defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS) 11 defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
44# define CONFIG_SERIAL_BFIN_HARD_CTSRTS 12# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
45#endif 13#endif
46 14
47#define BFIN_UART_TX_FIFO_SIZE 2
48
49/*
50 * The pin configuration is different from schematic
51 */
52struct bfin_serial_port {
53 struct uart_port port;
54 unsigned int old_status;
55 int status_irq;
56#ifdef CONFIG_SERIAL_BFIN_DMA
57 int tx_done;
58 int tx_count;
59 struct circ_buf rx_dma_buf;
60 struct timer_list rx_dma_timer;
61 int rx_dma_nrows;
62 unsigned int tx_dma_channel;
63 unsigned int rx_dma_channel;
64 struct work_struct tx_dma_workqueue;
65#endif
66#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
67 int scts;
68 int cts_pin;
69 int rts_pin;
70#endif
71};
72
73struct bfin_serial_res { 15struct bfin_serial_res {
74 unsigned long uart_base_addr; 16 unsigned long uart_base_addr;
75 int uart_irq; 17 int uart_irq;
@@ -148,3 +90,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
148}; 90};
149 91
150#define DRIVER_NAME "bfin-uart" 92#define DRIVER_NAME "bfin-uart"
93
94#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index 5684030ccc21..bbdcde48d050 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -49,19 +49,4 @@
49 49
50#endif 50#endif
51 51
52#define BFIN_UART_NR_PORTS 4
53
54#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
55#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
56#define OFFSET_GCTL 0x08 /* Global Control Register */
57#define OFFSET_LCR 0x0C /* Line Control Register */
58#define OFFSET_MCR 0x10 /* Modem Control Register */
59#define OFFSET_LSR 0x14 /* Line Status Register */
60#define OFFSET_MSR 0x18 /* Modem Status Register */
61#define OFFSET_SCR 0x1C /* SCR Scratch Register */
62#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
63#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
64#define OFFSET_THR 0x28 /* Transmit Holding register */
65#define OFFSET_RBR 0x2C /* Receive Buffer register */
66
67#endif 52#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 78f91103f175..3d751f134b7e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -2172,68 +2172,6 @@
2172 2172
2173#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */ 2173#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
2174 2174
2175/* Bit masks for UARTx_LCR */
2176
2177#if 0
2178/* conflicts with legacy one in last section */
2179#define WLS 0x3 /* Word Length Select */
2180#endif
2181#define STB 0x4 /* Stop Bits */
2182#define PEN 0x8 /* Parity Enable */
2183#define EPS 0x10 /* Even Parity Select */
2184#define STP 0x20 /* Sticky Parity */
2185#define SB 0x40 /* Set Break */
2186
2187/* Bit masks for UARTx_MCR */
2188
2189#define XOFF 0x1 /* Transmitter Off */
2190#define MRTS 0x2 /* Manual Request To Send */
2191#define RFIT 0x4 /* Receive FIFO IRQ Threshold */
2192#define RFRT 0x8 /* Receive FIFO RTS Threshold */
2193#define LOOP_ENA 0x10 /* Loopback Mode Enable */
2194#define FCPOL 0x20 /* Flow Control Pin Polarity */
2195#define ARTS 0x40 /* Automatic Request To Send */
2196#define ACTS 0x80 /* Automatic Clear To Send */
2197
2198/* Bit masks for UARTx_LSR */
2199
2200#define DR 0x1 /* Data Ready */
2201#define OE 0x2 /* Overrun Error */
2202#define PE 0x4 /* Parity Error */
2203#define FE 0x8 /* Framing Error */
2204#define BI 0x10 /* Break Interrupt */
2205#define THRE 0x20 /* THR Empty */
2206#define TEMT 0x40 /* Transmitter Empty */
2207#define TFI 0x80 /* Transmission Finished Indicator */
2208
2209/* Bit masks for UARTx_MSR */
2210
2211#define SCTS 0x1 /* Sticky CTS */
2212#define CTS 0x10 /* Clear To Send */
2213#define RFCS 0x20 /* Receive FIFO Count Status */
2214
2215/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
2216
2217#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */
2218#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */
2219#define ELSI 0x4 /* Enable Receive Status Interrupt */
2220#define EDSSI 0x8 /* Enable Modem Status Interrupt */
2221#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
2222#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
2223#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
2224
2225/* Bit masks for UARTx_GCTL */
2226
2227#define UCEN 0x1 /* UART Enable */
2228#define IREN 0x2 /* IrDA Mode Enable */
2229#define TPOLC 0x4 /* IrDA TX Polarity Change */
2230#define RPOLC 0x8 /* IrDA RX Polarity Change */
2231#define FPE 0x10 /* Force Parity Error */
2232#define FFE 0x20 /* Force Framing Error */
2233#define EDBO 0x40 /* Enable Divide-by-One */
2234#define EGLSI 0x80 /* Enable Global LS Interrupt */
2235
2236
2237/* ******************************************* */ 2175/* ******************************************* */
2238/* MULTI BIT MACRO ENUMERATIONS */ 2176/* MULTI BIT MACRO ENUMERATIONS */
2239/* ******************************************* */ 2177/* ******************************************* */
@@ -2251,13 +2189,6 @@
2251#define WDTH_CAP 0x0002 2189#define WDTH_CAP 0x0002
2252#define EXT_CLK 0x0003 2190#define EXT_CLK 0x0003
2253 2191
2254/* UARTx_LCR bit field options */
2255
2256#define WLS_5 0x0000 /* 5 data bits */
2257#define WLS_6 0x0001 /* 6 data bits */
2258#define WLS_7 0x0002 /* 7 data bits */
2259#define WLS_8 0x0003 /* 8 data bits */
2260
2261/* PINTx Register Bit Definitions */ 2192/* PINTx Register Bit Definitions */
2262 2193
2263#define PIQ0 0x00000001 2194#define PIQ0 0x00000001
@@ -2706,8 +2637,6 @@ PORTJ_FER registers
2706 2637
2707/* for legacy compatibility */ 2638/* for legacy compatibility */
2708 2639
2709#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
2710#define W1LMAX_MAX W1LMAX_MIN
2711#define EBIU_AMCBCTL0 EBIU_AMBCTL0 2640#define EBIU_AMCBCTL0 EBIU_AMBCTL0
2712#define EBIU_AMCBCTL1 EBIU_AMBCTL1 2641#define EBIU_AMCBCTL1 EBIU_AMBCTL1
2713#define PINT0_IRQ PINT0_REQUEST 2642#define PINT0_IRQ PINT0_REQUEST
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 22:23:22 -0500