diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2010-07-28 22:04:42 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-08-06 12:55:55 -0400 |
| commit | 2b73a19f2d3391b070d9d9270a9c9d502fe357ce (patch) | |
| tree | 848160deecb40270d08cf11a5739dedca043d7cd /arch/blackfin/mach-bf548 | |
| parent | ba3f5973ce3eb7ef4894ccd3df78c5cb410b17cc (diff) | |
Blackfin: BF54x: tweak DMAC MMR naming to match other ports
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h | 16 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF54x_base.h | 8 |
2 files changed, 12 insertions, 12 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h index 32f71e6a7c15..ea3ec4ea9e2b 100644 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h | |||
| @@ -301,10 +301,10 @@ | |||
| 301 | 301 | ||
| 302 | /* DMAC0 Registers */ | 302 | /* DMAC0 Registers */ |
| 303 | 303 | ||
| 304 | #define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) | 304 | #define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER) |
| 305 | #define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) | 305 | #define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val) |
| 306 | #define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) | 306 | #define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT) |
| 307 | #define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) | 307 | #define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val) |
| 308 | 308 | ||
| 309 | /* DMA Channel 0 Registers */ | 309 | /* DMA Channel 0 Registers */ |
| 310 | 310 | ||
| @@ -1155,10 +1155,10 @@ | |||
| 1155 | 1155 | ||
| 1156 | /* DMAC1 Registers */ | 1156 | /* DMAC1 Registers */ |
| 1157 | 1157 | ||
| 1158 | #define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) | 1158 | #define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER) |
| 1159 | #define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) | 1159 | #define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val) |
| 1160 | #define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) | 1160 | #define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT) |
| 1161 | #define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) | 1161 | #define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val) |
| 1162 | 1162 | ||
| 1163 | /* DMA Channel 12 Registers */ | 1163 | /* DMA Channel 12 Registers */ |
| 1164 | 1164 | ||
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index 01d52fade45e..4b33b18de0bb 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h | |||
| @@ -198,8 +198,8 @@ | |||
| 198 | 198 | ||
| 199 | /* DMAC0 Registers */ | 199 | /* DMAC0 Registers */ |
| 200 | 200 | ||
| 201 | #define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */ | 201 | #define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */ |
| 202 | #define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */ | 202 | #define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */ |
| 203 | 203 | ||
| 204 | /* DMA Channel 0 Registers */ | 204 | /* DMA Channel 0 Registers */ |
| 205 | 205 | ||
| @@ -688,8 +688,8 @@ | |||
| 688 | 688 | ||
| 689 | /* DMAC1 Registers */ | 689 | /* DMAC1 Registers */ |
| 690 | 690 | ||
| 691 | #define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */ | 691 | #define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */ |
| 692 | #define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */ | 692 | #define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */ |
| 693 | 693 | ||
| 694 | /* DMA Channel 12 Registers */ | 694 | /* DMA Channel 12 Registers */ |
| 695 | 695 | ||