diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2009-12-15 08:33:19 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-05-21 09:34:37 -0400 |
| commit | def282d61578e157ed6362eaffafef8a13af10be (patch) | |
| tree | 367a23ba8246aff274cb4464cded3899c909c3d0 /arch/blackfin/mach-bf548 | |
| parent | d012ce22a492a38977ba727b02bcd216ed571710 (diff) | |
Blackfin: punt duplicated CAN MMRs
Now that there's a common header with everything unified, drop the defines
from the global namespace. Pollution sucks.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF54x_base.h | 671 |
1 files changed, 0 insertions, 671 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index ab04d137fd8b..0ed06c2366fe 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h | |||
| @@ -2104,677 +2104,6 @@ | |||
| 2104 | 2104 | ||
| 2105 | #define ECCCNT 0x3ff /* Transfer Count */ | 2105 | #define ECCCNT 0x3ff /* Transfer Count */ |
| 2106 | 2106 | ||
| 2107 | /* Bit masks for CAN0_CONTROL */ | ||
| 2108 | |||
| 2109 | #define SRS 0x1 /* Software Reset */ | ||
| 2110 | #define DNM 0x2 /* DeviceNet Mode */ | ||
| 2111 | #define ABO 0x4 /* Auto Bus On */ | ||
| 2112 | #define WBA 0x10 /* Wakeup On CAN Bus Activity */ | ||
| 2113 | #define SMR 0x20 /* Sleep Mode Request */ | ||
| 2114 | #define CSR 0x40 /* CAN Suspend Mode Request */ | ||
| 2115 | #define CCR 0x80 /* CAN Configuration Mode Request */ | ||
| 2116 | |||
| 2117 | /* Bit masks for CAN0_STATUS */ | ||
| 2118 | |||
| 2119 | #define WT 0x1 /* CAN Transmit Warning Flag */ | ||
| 2120 | #define WR 0x2 /* CAN Receive Warning Flag */ | ||
| 2121 | #define EP 0x4 /* CAN Error Passive Mode */ | ||
| 2122 | #define EBO 0x8 /* CAN Error Bus Off Mode */ | ||
| 2123 | #define CSA 0x40 /* CAN Suspend Mode Acknowledge */ | ||
| 2124 | #define CCA 0x80 /* CAN Configuration Mode Acknowledge */ | ||
| 2125 | #define MBPTR 0x1f00 /* Mailbox Pointer */ | ||
| 2126 | #define TRM 0x4000 /* Transmit Mode Status */ | ||
| 2127 | #define REC 0x8000 /* Receive Mode Status */ | ||
| 2128 | |||
| 2129 | /* Bit masks for CAN0_DEBUG */ | ||
| 2130 | |||
| 2131 | #define DEC 0x1 /* Disable Transmit/Receive Error Counters */ | ||
| 2132 | #define DRI 0x2 /* Disable CANRX Input Pin */ | ||
| 2133 | #define DTO 0x4 /* Disable CANTX Output Pin */ | ||
| 2134 | #define DIL 0x8 /* Disable Internal Loop */ | ||
| 2135 | #define MAA 0x10 /* Mode Auto-Acknowledge */ | ||
| 2136 | #define MRB 0x20 /* Mode Read Back */ | ||
| 2137 | #define CDE 0x8000 /* CAN Debug Mode Enable */ | ||
| 2138 | |||
| 2139 | /* Bit masks for CAN0_CLOCK */ | ||
| 2140 | |||
| 2141 | #define BRP 0x3ff /* CAN Bit Rate Prescaler */ | ||
| 2142 | |||
| 2143 | /* Bit masks for CAN0_TIMING */ | ||
| 2144 | |||
| 2145 | #define SJW 0x300 /* Synchronization Jump Width */ | ||
| 2146 | #define SAM 0x80 /* Sampling */ | ||
| 2147 | #define TSEG2 0x70 /* Time Segment 2 */ | ||
| 2148 | #define TSEG1 0xf /* Time Segment 1 */ | ||
| 2149 | |||
| 2150 | /* Bit masks for CAN0_INTR */ | ||
| 2151 | |||
| 2152 | #define CANRX 0x80 /* Serial Input From Transceiver */ | ||
| 2153 | #define CANTX 0x40 /* Serial Output To Transceiver */ | ||
| 2154 | #define SMACK 0x8 /* Sleep Mode Acknowledge */ | ||
| 2155 | #define GIRQ 0x4 /* Global Interrupt Request Status */ | ||
| 2156 | #define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ | ||
| 2157 | #define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ | ||
| 2158 | |||
| 2159 | /* Bit masks for CAN0_GIM */ | ||
| 2160 | |||
| 2161 | #define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ | ||
| 2162 | #define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ | ||
| 2163 | #define EPIM 0x4 /* Error Passive Interrupt Mask */ | ||
| 2164 | #define BOIM 0x8 /* Bus Off Interrupt Mask */ | ||
| 2165 | #define WUIM 0x10 /* Wakeup Interrupt Mask */ | ||
| 2166 | #define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ | ||
| 2167 | #define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ | ||
| 2168 | #define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ | ||
| 2169 | #define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ | ||
| 2170 | #define ADIM 0x400 /* Access Denied Interrupt Mask */ | ||
| 2171 | |||
| 2172 | /* Bit masks for CAN0_GIS */ | ||
| 2173 | |||
| 2174 | #define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ | ||
| 2175 | #define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ | ||
| 2176 | #define EPIS 0x4 /* Error Passive Interrupt Status */ | ||
| 2177 | #define BOIS 0x8 /* Bus Off Interrupt Status */ | ||
| 2178 | #define WUIS 0x10 /* Wakeup Interrupt Status */ | ||
| 2179 | #define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ | ||
| 2180 | #define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ | ||
| 2181 | #define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ | ||
| 2182 | #define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ | ||
| 2183 | #define ADIS 0x400 /* Access Denied Interrupt Status */ | ||
| 2184 | |||
| 2185 | /* Bit masks for CAN0_GIF */ | ||
| 2186 | |||
| 2187 | #define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ | ||
| 2188 | #define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ | ||
| 2189 | #define EPIF 0x4 /* Error Passive Interrupt Flag */ | ||
| 2190 | #define BOIF 0x8 /* Bus Off Interrupt Flag */ | ||
| 2191 | #define WUIF 0x10 /* Wakeup Interrupt Flag */ | ||
| 2192 | #define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ | ||
| 2193 | #define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ | ||
| 2194 | #define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ | ||
| 2195 | #define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ | ||
| 2196 | #define ADIF 0x400 /* Access Denied Interrupt Flag */ | ||
| 2197 | |||
| 2198 | /* Bit masks for CAN0_MBTD */ | ||
| 2199 | |||
| 2200 | #define TDR 0x80 /* Temporary Disable Request */ | ||
| 2201 | #define TDA 0x40 /* Temporary Disable Acknowledge */ | ||
| 2202 | #define TDPTR 0x1f /* Temporary Disable Pointer */ | ||
| 2203 | |||
| 2204 | /* Bit masks for CAN0_UCCNF */ | ||
| 2205 | |||
| 2206 | #define UCCNF 0xf /* Universal Counter Configuration */ | ||
| 2207 | #define UCRC 0x20 /* Universal Counter Reload/Clear */ | ||
| 2208 | #define UCCT 0x40 /* Universal Counter CAN Trigger */ | ||
| 2209 | #define UCE 0x80 /* Universal Counter Enable */ | ||
| 2210 | |||
| 2211 | /* Bit masks for CAN0_CEC */ | ||
| 2212 | |||
| 2213 | #define RXECNT 0xff /* Receive Error Counter */ | ||
| 2214 | #define TXECNT 0xff00 /* Transmit Error Counter */ | ||
| 2215 | |||
| 2216 | /* Bit masks for CAN0_ESR */ | ||
| 2217 | |||
| 2218 | #define FER 0x80 /* Form Error */ | ||
| 2219 | #define BEF 0x40 /* Bit Error Flag */ | ||
| 2220 | #define SA0 0x20 /* Stuck At Dominant */ | ||
| 2221 | #define CRCE 0x10 /* CRC Error */ | ||
| 2222 | #define SER 0x8 /* Stuff Bit Error */ | ||
| 2223 | #define ACKE 0x4 /* Acknowledge Error */ | ||
| 2224 | |||
| 2225 | /* Bit masks for CAN0_EWR */ | ||
| 2226 | |||
| 2227 | #define EWLTEC 0xff00 /* Transmit Error Warning Limit */ | ||
| 2228 | #define EWLREC 0xff /* Receive Error Warning Limit */ | ||
| 2229 | |||
| 2230 | /* Bit masks for CAN0_AMxx_H */ | ||
| 2231 | |||
| 2232 | #define FDF 0x8000 /* Filter On Data Field */ | ||
| 2233 | #define FMD 0x4000 /* Full Mask Data */ | ||
| 2234 | #define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ | ||
| 2235 | #define BASEID 0x1ffc /* Base Identifier */ | ||
| 2236 | #define EXTID_HI 0x3 /* Extended Identifier High Bits */ | ||
| 2237 | |||
| 2238 | /* Bit masks for CAN0_AMxx_L */ | ||
| 2239 | |||
| 2240 | #define EXTID_LO 0xffff /* Extended Identifier Low Bits */ | ||
| 2241 | #define DFM 0xffff /* Data Field Mask */ | ||
| 2242 | |||
| 2243 | /* Bit masks for CAN0_MBxx_ID1 */ | ||
| 2244 | |||
| 2245 | #define AME 0x8000 /* Acceptance Mask Enable */ | ||
| 2246 | #define RTR 0x4000 /* Remote Transmission Request */ | ||
| 2247 | #define IDE 0x2000 /* Identifier Extension */ | ||
| 2248 | #define BASEID 0x1ffc /* Base Identifier */ | ||
| 2249 | #define EXTID_HI 0x3 /* Extended Identifier High Bits */ | ||
| 2250 | |||
| 2251 | /* Bit masks for CAN0_MBxx_ID0 */ | ||
| 2252 | |||
| 2253 | #define EXTID_LO 0xffff /* Extended Identifier Low Bits */ | ||
| 2254 | #define DFM 0xffff /* Data Field Mask */ | ||
| 2255 | |||
| 2256 | /* Bit masks for CAN0_MBxx_TIMESTAMP */ | ||
| 2257 | |||
| 2258 | #define TSV 0xffff /* Time Stamp Value */ | ||
| 2259 | |||
| 2260 | /* Bit masks for CAN0_MBxx_LENGTH */ | ||
| 2261 | |||
| 2262 | #define DLC 0xf /* Data Length Code */ | ||
| 2263 | |||
| 2264 | /* Bit masks for CAN0_MBxx_DATA3 */ | ||
| 2265 | |||
| 2266 | #define CAN_BYTE0 0xff00 /* Data Field Byte 0 */ | ||
| 2267 | #define CAN_BYTE1 0xff /* Data Field Byte 1 */ | ||
| 2268 | |||
| 2269 | /* Bit masks for CAN0_MBxx_DATA2 */ | ||
| 2270 | |||
| 2271 | #define CAN_BYTE2 0xff00 /* Data Field Byte 2 */ | ||
| 2272 | #define CAN_BYTE3 0xff /* Data Field Byte 3 */ | ||
| 2273 | |||
| 2274 | /* Bit masks for CAN0_MBxx_DATA1 */ | ||
| 2275 | |||
| 2276 | #define CAN_BYTE4 0xff00 /* Data Field Byte 4 */ | ||
| 2277 | #define CAN_BYTE5 0xff /* Data Field Byte 5 */ | ||
| 2278 | |||
| 2279 | /* Bit masks for CAN0_MBxx_DATA0 */ | ||
| 2280 | |||
| 2281 | #define CAN_BYTE6 0xff00 /* Data Field Byte 6 */ | ||
| 2282 | #define CAN_BYTE7 0xff /* Data Field Byte 7 */ | ||
| 2283 | |||
| 2284 | /* Bit masks for CAN0_MC1 */ | ||
| 2285 | |||
| 2286 | #define MC0 0x1 /* Mailbox 0 Enable */ | ||
| 2287 | #define MC1 0x2 /* Mailbox 1 Enable */ | ||
| 2288 | #define MC2 0x4 /* Mailbox 2 Enable */ | ||
| 2289 | #define MC3 0x8 /* Mailbox 3 Enable */ | ||
| 2290 | #define MC4 0x10 /* Mailbox 4 Enable */ | ||
| 2291 | #define MC5 0x20 /* Mailbox 5 Enable */ | ||
| 2292 | #define MC6 0x40 /* Mailbox 6 Enable */ | ||
| 2293 | #define MC7 0x80 /* Mailbox 7 Enable */ | ||
| 2294 | #define MC8 0x100 /* Mailbox 8 Enable */ | ||
| 2295 | #define MC9 0x200 /* Mailbox 9 Enable */ | ||
| 2296 | #define MC10 0x400 /* Mailbox 10 Enable */ | ||
| 2297 | #define MC11 0x800 /* Mailbox 11 Enable */ | ||
| 2298 | #define MC12 0x1000 /* Mailbox 12 Enable */ | ||
| 2299 | #define MC13 0x2000 /* Mailbox 13 Enable */ | ||
| 2300 | #define MC14 0x4000 /* Mailbox 14 Enable */ | ||
| 2301 | #define MC15 0x8000 /* Mailbox 15 Enable */ | ||
| 2302 | |||
| 2303 | /* Bit masks for CAN0_MC2 */ | ||
| 2304 | |||
| 2305 | #define MC16 0x1 /* Mailbox 16 Enable */ | ||
| 2306 | #define MC17 0x2 /* Mailbox 17 Enable */ | ||
| 2307 | #define MC18 0x4 /* Mailbox 18 Enable */ | ||
| 2308 | #define MC19 0x8 /* Mailbox 19 Enable */ | ||
| 2309 | #define MC20 0x10 /* Mailbox 20 Enable */ | ||
| 2310 | #define MC21 0x20 /* Mailbox 21 Enable */ | ||
| 2311 | #define MC22 0x40 /* Mailbox 22 Enable */ | ||
| 2312 | #define MC23 0x80 /* Mailbox 23 Enable */ | ||
| 2313 | #define MC24 0x100 /* Mailbox 24 Enable */ | ||
| 2314 | #define MC25 0x200 /* Mailbox 25 Enable */ | ||
| 2315 | #define MC26 0x400 /* Mailbox 26 Enable */ | ||
| 2316 | #define MC27 0x800 /* Mailbox 27 Enable */ | ||
| 2317 | #define MC28 0x1000 /* Mailbox 28 Enable */ | ||
| 2318 | #define MC29 0x2000 /* Mailbox 29 Enable */ | ||
| 2319 | #define MC30 0x4000 /* Mailbox 30 Enable */ | ||
| 2320 | #define MC31 0x8000 /* Mailbox 31 Enable */ | ||
| 2321 | |||
| 2322 | /* Bit masks for CAN0_MD1 */ | ||
| 2323 | |||
| 2324 | #define MD0 0x1 /* Mailbox 0 Receive Enable */ | ||
| 2325 | #define MD1 0x2 /* Mailbox 1 Receive Enable */ | ||
| 2326 | #define MD2 0x4 /* Mailbox 2 Receive Enable */ | ||
| 2327 | #define MD3 0x8 /* Mailbox 3 Receive Enable */ | ||
| 2328 | #define MD4 0x10 /* Mailbox 4 Receive Enable */ | ||
| 2329 | #define MD5 0x20 /* Mailbox 5 Receive Enable */ | ||
| 2330 | #define MD6 0x40 /* Mailbox 6 Receive Enable */ | ||
| 2331 | #define MD7 0x80 /* Mailbox 7 Receive Enable */ | ||
| 2332 | #define MD8 0x100 /* Mailbox 8 Receive Enable */ | ||
| 2333 | #define MD9 0x200 /* Mailbox 9 Receive Enable */ | ||
| 2334 | #define MD10 0x400 /* Mailbox 10 Receive Enable */ | ||
| 2335 | #define MD11 0x800 /* Mailbox 11 Receive Enable */ | ||
| 2336 | #define MD12 0x1000 /* Mailbox 12 Receive Enable */ | ||
| 2337 | #define MD13 0x2000 /* Mailbox 13 Receive Enable */ | ||
| 2338 | #define MD14 0x4000 /* Mailbox 14 Receive Enable */ | ||
| 2339 | #define MD15 0x8000 /* Mailbox 15 Receive Enable */ | ||
| 2340 | |||
| 2341 | /* Bit masks for CAN0_MD2 */ | ||
| 2342 | |||
| 2343 | #define MD16 0x1 /* Mailbox 16 Receive Enable */ | ||
| 2344 | #define MD17 0x2 /* Mailbox 17 Receive Enable */ | ||
| 2345 | #define MD18 0x4 /* Mailbox 18 Receive Enable */ | ||
| 2346 | #define MD19 0x8 /* Mailbox 19 Receive Enable */ | ||
| 2347 | #define MD20 0x10 /* Mailbox 20 Receive Enable */ | ||
| 2348 | #define MD21 0x20 /* Mailbox 21 Receive Enable */ | ||
| 2349 | #define MD22 0x40 /* Mailbox 22 Receive Enable */ | ||
| 2350 | #define MD23 0x80 /* Mailbox 23 Receive Enable */ | ||
| 2351 | #define MD24 0x100 /* Mailbox 24 Receive Enable */ | ||
| 2352 | #define MD25 0x200 /* Mailbox 25 Receive Enable */ | ||
| 2353 | #define MD26 0x400 /* Mailbox 26 Receive Enable */ | ||
| 2354 | #define MD27 0x800 /* Mailbox 27 Receive Enable */ | ||
| 2355 | #define MD28 0x1000 /* Mailbox 28 Receive Enable */ | ||
| 2356 | #define MD29 0x2000 /* Mailbox 29 Receive Enable */ | ||
| 2357 | #define MD30 0x4000 /* Mailbox 30 Receive Enable */ | ||
| 2358 | #define MD31 0x8000 /* Mailbox 31 Receive Enable */ | ||
| 2359 | |||
| 2360 | /* Bit masks for CAN0_RMP1 */ | ||
| 2361 | |||
| 2362 | #define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ | ||
| 2363 | #define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ | ||
| 2364 | #define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ | ||
| 2365 | #define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ | ||
| 2366 | #define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ | ||
| 2367 | #define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ | ||
| 2368 | #define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ | ||
| 2369 | #define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ | ||
| 2370 | #define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ | ||
| 2371 | #define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ | ||
| 2372 | #define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ | ||
| 2373 | #define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ | ||
| 2374 | #define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ | ||
| 2375 | #define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ | ||
| 2376 | #define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ | ||
| 2377 | #define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ | ||
| 2378 | |||
| 2379 | /* Bit masks for CAN0_RMP2 */ | ||
| 2380 | |||
| 2381 | #define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ | ||
| 2382 | #define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ | ||
| 2383 | #define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ | ||
| 2384 | #define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ | ||
| 2385 | #define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ | ||
| 2386 | #define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ | ||
| 2387 | #define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ | ||
| 2388 | #define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ | ||
| 2389 | #define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ | ||
| 2390 | #define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ | ||
| 2391 | #define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ | ||
| 2392 | #define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ | ||
| 2393 | #define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ | ||
| 2394 | #define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ | ||
| 2395 | #define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ | ||
| 2396 | #define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ | ||
| 2397 | |||
| 2398 | /* Bit masks for CAN0_RML1 */ | ||
| 2399 | |||
| 2400 | #define RML0 0x1 /* Mailbox 0 Receive Message Lost */ | ||
| 2401 | #define RML1 0x2 /* Mailbox 1 Receive Message Lost */ | ||
| 2402 | #define RML2 0x4 /* Mailbox 2 Receive Message Lost */ | ||
| 2403 | #define RML3 0x8 /* Mailbox 3 Receive Message Lost */ | ||
| 2404 | #define RML4 0x10 /* Mailbox 4 Receive Message Lost */ | ||
| 2405 | #define RML5 0x20 /* Mailbox 5 Receive Message Lost */ | ||
| 2406 | #define RML6 0x40 /* Mailbox 6 Receive Message Lost */ | ||
| 2407 | #define RML7 0x80 /* Mailbox 7 Receive Message Lost */ | ||
| 2408 | #define RML8 0x100 /* Mailbox 8 Receive Message Lost */ | ||
| 2409 | #define RML9 0x200 /* Mailbox 9 Receive Message Lost */ | ||
| 2410 | #define RML10 0x400 /* Mailbox 10 Receive Message Lost */ | ||
| 2411 | #define RML11 0x800 /* Mailbox 11 Receive Message Lost */ | ||
| 2412 | #define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ | ||
| 2413 | #define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ | ||
| 2414 | #define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ | ||
| 2415 | #define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ | ||
| 2416 | |||
| 2417 | /* Bit masks for CAN0_RML2 */ | ||
| 2418 | |||
| 2419 | #define RML16 0x1 /* Mailbox 16 Receive Message Lost */ | ||
| 2420 | #define RML17 0x2 /* Mailbox 17 Receive Message Lost */ | ||
| 2421 | #define RML18 0x4 /* Mailbox 18 Receive Message Lost */ | ||
| 2422 | #define RML19 0x8 /* Mailbox 19 Receive Message Lost */ | ||
| 2423 | #define RML20 0x10 /* Mailbox 20 Receive Message Lost */ | ||
| 2424 | #define RML21 0x20 /* Mailbox 21 Receive Message Lost */ | ||
| 2425 | #define RML22 0x40 /* Mailbox 22 Receive Message Lost */ | ||
| 2426 | #define RML23 0x80 /* Mailbox 23 Receive Message Lost */ | ||
| 2427 | #define RML24 0x100 /* Mailbox 24 Receive Message Lost */ | ||
| 2428 | #define RML25 0x200 /* Mailbox 25 Receive Message Lost */ | ||
| 2429 | #define RML26 0x400 /* Mailbox 26 Receive Message Lost */ | ||
| 2430 | #define RML27 0x800 /* Mailbox 27 Receive Message Lost */ | ||
| 2431 | #define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ | ||
| 2432 | #define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ | ||
| 2433 | #define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ | ||
| 2434 | #define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ | ||
| 2435 | |||
| 2436 | /* Bit masks for CAN0_OPSS1 */ | ||
| 2437 | |||
| 2438 | #define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2439 | #define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2440 | #define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2441 | #define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2442 | #define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2443 | #define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2444 | #define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2445 | #define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2446 | #define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2447 | #define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2448 | #define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2449 | #define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2450 | #define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2451 | #define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2452 | #define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2453 | #define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2454 | |||
| 2455 | /* Bit masks for CAN0_OPSS2 */ | ||
| 2456 | |||
| 2457 | #define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2458 | #define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2459 | #define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2460 | #define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2461 | #define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2462 | #define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2463 | #define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2464 | #define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2465 | #define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2466 | #define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2467 | #define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2468 | #define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2469 | #define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2470 | #define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2471 | #define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2472 | #define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ | ||
| 2473 | |||
| 2474 | /* Bit masks for CAN0_TRS1 */ | ||
| 2475 | |||
| 2476 | #define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ | ||
| 2477 | #define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ | ||
| 2478 | #define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ | ||
| 2479 | #define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ | ||
| 2480 | #define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ | ||
| 2481 | #define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ | ||
| 2482 | #define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ | ||
| 2483 | #define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ | ||
| 2484 | #define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ | ||
| 2485 | #define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ | ||
| 2486 | #define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ | ||
| 2487 | #define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ | ||
| 2488 | #define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ | ||
| 2489 | #define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ | ||
| 2490 | #define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ | ||
| 2491 | #define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ | ||
| 2492 | |||
| 2493 | /* Bit masks for CAN0_TRS2 */ | ||
| 2494 | |||
| 2495 | #define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ | ||
| 2496 | #define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ | ||
| 2497 | #define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ | ||
| 2498 | #define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ | ||
| 2499 | #define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ | ||
| 2500 | #define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ | ||
| 2501 | #define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ | ||
| 2502 | #define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ | ||
| 2503 | #define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ | ||
| 2504 | #define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ | ||
| 2505 | #define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ | ||
| 2506 | #define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ | ||
| 2507 | #define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ | ||
| 2508 | #define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ | ||
| 2509 | #define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ | ||
| 2510 | #define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ | ||
| 2511 | |||
| 2512 | /* Bit masks for CAN0_TRR1 */ | ||
| 2513 | |||
| 2514 | #define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ | ||
| 2515 | #define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ | ||
| 2516 | #define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ | ||
| 2517 | #define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ | ||
| 2518 | #define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ | ||
| 2519 | #define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ | ||
| 2520 | #define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ | ||
| 2521 | #define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ | ||
| 2522 | #define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ | ||
| 2523 | #define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ | ||
| 2524 | #define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ | ||
| 2525 | #define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ | ||
| 2526 | #define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ | ||
| 2527 | #define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ | ||
| 2528 | #define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ | ||
| 2529 | #define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ | ||
| 2530 | |||
| 2531 | /* Bit masks for CAN0_TRR2 */ | ||
| 2532 | |||
| 2533 | #define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ | ||
| 2534 | #define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ | ||
| 2535 | #define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ | ||
| 2536 | #define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ | ||
| 2537 | #define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ | ||
| 2538 | #define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ | ||
| 2539 | #define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ | ||
| 2540 | #define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ | ||
| 2541 | #define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ | ||
| 2542 | #define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ | ||
| 2543 | #define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ | ||
| 2544 | #define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ | ||
| 2545 | #define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ | ||
| 2546 | #define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ | ||
| 2547 | #define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ | ||
| 2548 | #define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ | ||
| 2549 | |||
| 2550 | /* Bit masks for CAN0_AA1 */ | ||
| 2551 | |||
| 2552 | #define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ | ||
| 2553 | #define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ | ||
| 2554 | #define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ | ||
| 2555 | #define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ | ||
| 2556 | #define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ | ||
| 2557 | #define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ | ||
| 2558 | #define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ | ||
| 2559 | #define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ | ||
| 2560 | #define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ | ||
| 2561 | #define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ | ||
| 2562 | #define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ | ||
| 2563 | #define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ | ||
| 2564 | #define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ | ||
| 2565 | #define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ | ||
| 2566 | #define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ | ||
| 2567 | #define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ | ||
| 2568 | |||
| 2569 | /* Bit masks for CAN0_AA2 */ | ||
| 2570 | |||
| 2571 | #define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ | ||
| 2572 | #define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ | ||
| 2573 | #define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ | ||
| 2574 | #define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ | ||
| 2575 | #define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ | ||
| 2576 | #define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ | ||
| 2577 | #define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ | ||
| 2578 | #define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ | ||
| 2579 | #define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ | ||
| 2580 | #define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ | ||
| 2581 | #define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ | ||
| 2582 | #define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ | ||
| 2583 | #define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ | ||
| 2584 | #define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ | ||
| 2585 | #define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ | ||
| 2586 | #define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ | ||
| 2587 | |||
| 2588 | /* Bit masks for CAN0_TA1 */ | ||
| 2589 | |||
| 2590 | #define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ | ||
| 2591 | #define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ | ||
| 2592 | #define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ | ||
| 2593 | #define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ | ||
| 2594 | #define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ | ||
| 2595 | #define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ | ||
| 2596 | #define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ | ||
| 2597 | #define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ | ||
| 2598 | #define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ | ||
| 2599 | #define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ | ||
| 2600 | #define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ | ||
| 2601 | #define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ | ||
| 2602 | #define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ | ||
| 2603 | #define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ | ||
| 2604 | #define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ | ||
| 2605 | #define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ | ||
| 2606 | |||
| 2607 | /* Bit masks for CAN0_TA2 */ | ||
| 2608 | |||
| 2609 | #define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ | ||
| 2610 | #define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ | ||
| 2611 | #define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ | ||
| 2612 | #define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ | ||
| 2613 | #define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ | ||
| 2614 | #define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ | ||
| 2615 | #define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ | ||
| 2616 | #define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ | ||
| 2617 | #define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ | ||
| 2618 | #define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ | ||
| 2619 | #define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ | ||
| 2620 | #define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ | ||
| 2621 | #define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ | ||
| 2622 | #define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ | ||
| 2623 | #define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ | ||
| 2624 | #define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ | ||
| 2625 | |||
| 2626 | /* Bit masks for CAN0_RFH1 */ | ||
| 2627 | |||
| 2628 | #define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ | ||
| 2629 | #define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ | ||
| 2630 | #define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ | ||
| 2631 | #define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ | ||
| 2632 | #define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ | ||
| 2633 | #define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ | ||
| 2634 | #define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ | ||
| 2635 | #define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ | ||
| 2636 | #define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ | ||
| 2637 | #define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ | ||
| 2638 | #define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ | ||
| 2639 | #define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ | ||
| 2640 | #define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ | ||
| 2641 | #define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ | ||
| 2642 | #define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ | ||
| 2643 | #define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ | ||
| 2644 | |||
| 2645 | /* Bit masks for CAN0_RFH2 */ | ||
| 2646 | |||
| 2647 | #define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ | ||
| 2648 | #define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ | ||
| 2649 | #define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ | ||
| 2650 | #define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ | ||
| 2651 | #define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ | ||
| 2652 | #define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ | ||
| 2653 | #define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ | ||
| 2654 | #define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ | ||
| 2655 | #define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ | ||
| 2656 | #define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ | ||
| 2657 | #define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ | ||
| 2658 | #define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ | ||
| 2659 | #define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ | ||
| 2660 | #define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ | ||
| 2661 | #define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ | ||
| 2662 | #define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ | ||
| 2663 | |||
| 2664 | /* Bit masks for CAN0_MBIM1 */ | ||
| 2665 | |||
| 2666 | #define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ | ||
| 2667 | #define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ | ||
| 2668 | #define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ | ||
| 2669 | #define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ | ||
| 2670 | #define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ | ||
| 2671 | #define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ | ||
| 2672 | #define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ | ||
| 2673 | #define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ | ||
| 2674 | #define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ | ||
| 2675 | #define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ | ||
| 2676 | #define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ | ||
| 2677 | #define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ | ||
| 2678 | #define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ | ||
| 2679 | #define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ | ||
| 2680 | #define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ | ||
| 2681 | #define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ | ||
| 2682 | |||
| 2683 | /* Bit masks for CAN0_MBIM2 */ | ||
| 2684 | |||
| 2685 | #define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ | ||
| 2686 | #define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ | ||
| 2687 | #define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ | ||
| 2688 | #define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ | ||
| 2689 | #define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ | ||
| 2690 | #define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ | ||
| 2691 | #define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ | ||
| 2692 | #define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ | ||
| 2693 | #define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ | ||
| 2694 | #define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ | ||
| 2695 | #define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ | ||
| 2696 | #define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ | ||
| 2697 | #define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ | ||
| 2698 | #define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ | ||
| 2699 | #define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ | ||
| 2700 | #define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ | ||
| 2701 | |||
| 2702 | /* Bit masks for CAN0_MBTIF1 */ | ||
| 2703 | |||
| 2704 | #define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ | ||
| 2705 | #define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ | ||
| 2706 | #define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ | ||
| 2707 | #define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ | ||
| 2708 | #define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ | ||
| 2709 | #define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ | ||
| 2710 | #define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ | ||
| 2711 | #define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ | ||
| 2712 | #define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ | ||
| 2713 | #define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ | ||
| 2714 | #define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ | ||
| 2715 | #define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ | ||
| 2716 | #define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ | ||
| 2717 | #define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ | ||
| 2718 | #define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ | ||
| 2719 | #define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ | ||
| 2720 | |||
| 2721 | /* Bit masks for CAN0_MBTIF2 */ | ||
| 2722 | |||
| 2723 | #define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ | ||
| 2724 | #define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ | ||
| 2725 | #define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ | ||
| 2726 | #define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ | ||
| 2727 | #define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ | ||
| 2728 | #define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ | ||
| 2729 | #define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ | ||
| 2730 | #define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ | ||
| 2731 | #define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ | ||
| 2732 | #define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ | ||
| 2733 | #define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ | ||
| 2734 | #define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ | ||
| 2735 | #define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ | ||
| 2736 | #define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ | ||
| 2737 | #define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ | ||
| 2738 | #define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ | ||
| 2739 | |||
| 2740 | /* Bit masks for CAN0_MBRIF1 */ | ||
| 2741 | |||
| 2742 | #define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ | ||
| 2743 | #define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ | ||
| 2744 | #define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ | ||
| 2745 | #define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ | ||
| 2746 | #define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ | ||
| 2747 | #define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ | ||
| 2748 | #define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ | ||
| 2749 | #define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ | ||
| 2750 | #define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ | ||
| 2751 | #define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ | ||
| 2752 | #define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ | ||
| 2753 | #define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ | ||
| 2754 | #define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ | ||
| 2755 | #define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ | ||
| 2756 | #define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ | ||
| 2757 | #define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ | ||
| 2758 | |||
| 2759 | /* Bit masks for CAN0_MBRIF2 */ | ||
| 2760 | |||
| 2761 | #define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ | ||
| 2762 | #define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ | ||
| 2763 | #define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ | ||
| 2764 | #define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ | ||
| 2765 | #define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ | ||
| 2766 | #define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ | ||
| 2767 | #define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ | ||
| 2768 | #define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ | ||
| 2769 | #define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ | ||
| 2770 | #define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ | ||
| 2771 | #define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ | ||
| 2772 | #define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ | ||
| 2773 | #define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ | ||
| 2774 | #define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ | ||
| 2775 | #define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ | ||
| 2776 | #define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ | ||
| 2777 | |||
| 2778 | /* Bit masks for EPPIx_STATUS */ | 2107 | /* Bit masks for EPPIx_STATUS */ |
| 2779 | 2108 | ||
| 2780 | #define CFIFO_ERR 0x1 /* Chroma FIFO Error */ | 2109 | #define CFIFO_ERR 0x1 /* Chroma FIFO Error */ |