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authorRoy Huang <roy.huang@analog.com>2007-07-12 10:41:45 -0400
committerBryan Wu <bryan.wu@analog.com>2007-07-12 10:41:45 -0400
commit24a07a124198153540f8f43d9e91d16227aba66e (patch)
tree917b2011e67e224515830833b1151e276b6c6137 /arch/blackfin/mach-bf548
parent088eec1192a0ae60fc218796027e622008af36c0 (diff)
Blackfin arch: initial supporting for BF548-EZKIT
The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia applications where system performance and cost are essential ingredients. The integration of multimedia, human interface, and connectivity peripherals combined with increased system bandwidth and on-chip memory provides customers a platform to design the most demanding applications. Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will be submitted later. Please enjoy the show. Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf548')
-rw-r--r--arch/blackfin/mach-bf548/Kconfig282
-rw-r--r--arch/blackfin/mach-bf548/Makefile9
-rw-r--r--arch/blackfin/mach-bf548/boards/Makefile5
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c114
-rw-r--r--arch/blackfin/mach-bf548/boards/led.S172
-rw-r--r--arch/blackfin/mach-bf548/cpu.c159
-rw-r--r--arch/blackfin/mach-bf548/dma.c156
-rw-r--r--arch/blackfin/mach-bf548/gpio.c175
-rw-r--r--arch/blackfin/mach-bf548/head.S507
-rw-r--r--arch/blackfin/mach-bf548/ints-priority.c137
10 files changed, 1716 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
new file mode 100644
index 000000000000..b28625e921be
--- /dev/null
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -0,0 +1,282 @@
1if (BF54x)
2
3menu "BF548 Specific Configuration"
4
5comment "Interrupt Priority Assignment"
6menu "Priority"
7
8config IRQ_PLL_WAKEUP
9 int "IRQ_PLL_WAKEUP"
10 default 7
11config IRQ_DMAC0_ERR
12 int "IRQ_DMAC0_ERR"
13 default 7
14config IRQ_EPPI0_ERR
15 int "IRQ_EPPI0_ERR"
16 default 7
17config IRQ_SPORT0_ERR
18 int "IRQ_SPORT0_ERR"
19 default 7
20config IRQ_SPORT1_ERR
21 int "IRQ_SPORT1_ERR"
22 default 7
23config IRQ_SPI0_ERR
24 int "IRQ_SPI0_ERR"
25 default 7
26config IRQ_UART0_ERR
27 int "IRQ_UART0_ERR"
28 default 7
29config IRQ_RTC
30 int "IRQ_RTC"
31 default 8
32config IRQ_EPPI0
33 int "IRQ_EPPI0"
34 default 8
35config IRQ_SPORT0_RX
36 int "IRQ_SPORT0_RX"
37 default 9
38config IRQ_SPORT0_TX
39 int "IRQ_SPORT0_TX"
40 default 9
41config IRQ_SPORT1_RX
42 int "IRQ_SPORT1_RX"
43 default 9
44config IRQ_SPORT1_TX
45 int "IRQ_SPORT1_TX"
46 default 9
47config IRQ_SPI0
48 int "IRQ_SPI0"
49 default 10
50config IRQ_UART0_RX
51 int "IRQ_UART0_RX"
52 default 10
53config IRQ_UART0_TX
54 int "IRQ_UART0_TX"
55 default 10
56config IRQ_TIMER8
57 int "IRQ_TIMER8"
58 default 11
59config IRQ_TIMER9
60 int "IRQ_TIMER9"
61 default 11
62config IRQ_TIMER10
63 int "IRQ_TIMER10"
64 default 11
65config IRQ_PINT0
66 int "IRQ_PINT0"
67 default 12
68config IRQ_PINT1
69 int "IRQ_PINT0"
70 default 12
71config IRQ_MDMAS0
72 int "IRQ_MDMAS0"
73 default 13
74config IRQ_MDMAS1
75 int "IRQ_DMDMAS1"
76 default 13
77config IRQ_WATCHDOG
78 int "IRQ_WATCHDOG"
79 default 13
80config IRQ_DMAC1_ERR
81 int "IRQ_DMAC1_ERR"
82 default 7
83config IRQ_SPORT2_ERR
84 int "IRQ_SPORT2_ERR"
85 default 7
86config IRQ_SPORT3_ERR
87 int "IRQ_SPORT3_ERR"
88 default 7
89config IRQ_MXVR_DATA
90 int "IRQ MXVR Data"
91 default 7
92config IRQ_SPI1_ERR
93 int "IRQ_SPI1_ERR"
94 default 7
95config IRQ_SPI2_ERR
96 int "IRQ_SPI2_ERR"
97 default 7
98config IRQ_UART1_ERR
99 int "IRQ_UART1_ERR"
100 default 7
101config IRQ_UART2_ERR
102 int "IRQ_UART2_ERR"
103 default 7
104config IRQ_CAN0_ERR
105 int "IRQ_CAN0_ERR"
106 default 7
107config IRQ_SPORT2_RX
108 int "IRQ_SPORT2_RX"
109 default 9
110config IRQ_SPORT2_TX
111 int "IRQ_SPORT2_TX"
112 default 9
113config IRQ_SPORT3_RX
114 int "IRQ_SPORT3_RX"
115 default 9
116config IRQ_SPORT3_TX
117 int "IRQ_SPORT3_TX"
118 default 9
119config IRQ_EPPI1
120 int "IRQ_EPPI1"
121 default 9
122config IRQ_EPPI2
123 int "IRQ_EPPI2"
124 default 9
125config IRQ_SPI1
126 int "IRQ_SPI1"
127 default 10
128config IRQ_SPI2
129 int "IRQ_SPI2"
130 default 10
131config IRQ_UART1_RX
132 int "IRQ_UART1_RX"
133 default 10
134config IRQ_UART1_TX
135 int "IRQ_UART1_TX"
136 default 10
137config IRQ_ATAPI_RX
138 int "IRQ_ATAPI_RX"
139 default 10
140config IRQ_ATAPI_TX
141 int "IRQ_ATAPI_TX"
142 default 10
143config IRQ_TWI0
144 int "IRQ_TWI0"
145 default 11
146config IRQ_TWI1
147 int "IRQ_TWI1"
148 default 11
149config IRQ_CAN0_RX
150 int "IRQ_CAN_RX"
151 default 11
152config IRQ_CAN0_TX
153 int "IRQ_CAN_TX"
154 default 11
155config IRQ_MDMAS2
156 int "IRQ_MDMAS2"
157 default 13
158config IRQ_MDMAS3
159 int "IRQ_DMMAS3"
160 default 13
161config IRQ_MXVR_ERR
162 int "IRQ_MXVR_ERR"
163 default 11
164config IRQ_MXVR_MSG
165 int "IRQ_MXVR_MSG"
166 default 11
167config IRQ_MXVR_PKT
168 int "IRQ_MXVR_PKT"
169 default 11
170config IRQ_EPPI1_ERR
171 int "IRQ_EPPI1_ERR"
172 default 7
173config IRQ_EPPI2_ERR
174 int "IRQ_EPPI2_ERR"
175 default 7
176config IRQ_UART3_ERR
177 int "IRQ_UART3_ERR"
178 default 7
179config IRQ_HOST_ERR
180 int "IRQ_HOST_ERR"
181 default 7
182config IRQ_PIXC_ERR
183 int "IRQ_PIXC_ERR"
184 default 7
185config IRQ_NFC_ERR
186 int "IRQ_NFC_ERR"
187 default 7
188config IRQ_ATAPI_ERR
189 int "IRQ_ATAPI_ERR"
190 default 7
191config IRQ_CAN1_ERR
192 int "IRQ_CAN1_ERR"
193 default 7
194config IRQ_HS_DMA_ERR
195 int "IRQ Handshake DMA Status"
196 default 7
197config IRQ_PIXC_IN0
198 int "IRQ PIXC IN0"
199 default 8
200config IRQ_PIXC_IN1
201 int "IRQ PIXC IN1"
202 default 8
203config IRQ_PIXC_OUT
204 int "IRQ PIXC OUT"
205 default 8
206config IRQ_SDH
207 int "IRQ SDH"
208 default 8
209config IRQ_CNT
210 int "IRQ CNT"
211 default 8
212config IRQ_KEY
213 int "IRQ KEY"
214 default 8
215config IRQ_CAN1_RX
216 int "IRQ CAN1 RX"
217 default 11
218config IRQ_CAN1_TX
219 int "IRQ_CAN1_TX"
220 default 11
221config IRQ_SDH_MASK0
222 int "IRQ_SDH_MASK0"
223 default 11
224config IRQ_SDH_MASK1
225 int "IRQ_SDH_MASK1"
226 default 11
227config IRQ_USB_INT0
228 int "IRQ USB INT0"
229 default 11
230config IRQ_USB_INT1
231 int "IRQ USB INT1"
232 default 11
233config IRQ_USB_INT2
234 int "IRQ USB INT2"
235 default 11
236config IRQ_USB_DMA
237 int "IRQ USB DMA"
238 default 11
239config IRQ_OTPSEC
240 int "IRQ OPTSEC"
241 default 11
242config IRQ_TIMER0
243 int "IRQ_TIMER0"
244 default 11
245config IRQ_TIMER1
246 int "IRQ_TIMER1"
247 default 11
248config IRQ_TIMER2
249 int "IRQ_TIMER2"
250 default 11
251config IRQ_TIMER3
252 int "IRQ_TIMER3"
253 default 11
254config IRQ_TIMER4
255 int "IRQ_TIMER4"
256 default 11
257config IRQ_TIMER5
258 int "IRQ_TIMER5"
259 default 11
260config IRQ_TIMER6
261 int "IRQ_TIMER6"
262 default 11
263config IRQ_TIMER7
264 int "IRQ_TIMER7"
265 default 11
266config IRQ_PINT2
267 int "IRQ_PIN2"
268 default 11
269config IRQ_PINT3
270 int "IRQ_PIN3"
271 default 11
272
273 help
274 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
275 This applies to all the above. It is not recommended to assign the
276 highest priority number 7 to UART or any other device.
277
278endmenu
279
280endmenu
281
282endif
diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile
new file mode 100644
index 000000000000..060ad78ebf1d
--- /dev/null
+++ b/arch/blackfin/mach-bf548/Makefile
@@ -0,0 +1,9 @@
1#
2# arch/blackfin/mach-bf537/Makefile
3#
4
5extra-y := head.o
6
7obj-y := ints-priority.o dma.o gpio.o
8
9obj-$(CONFIG_CPU_FREQ) += cpu.o
diff --git a/arch/blackfin/mach-bf548/boards/Makefile b/arch/blackfin/mach-bf548/boards/Makefile
new file mode 100644
index 000000000000..486e07c99a51
--- /dev/null
+++ b/arch/blackfin/mach-bf548/boards/Makefile
@@ -0,0 +1,5 @@
1#
2# arch/blackfin/mach-bf548/boards/Makefile
3#
4
5obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o led.o
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
new file mode 100644
index 000000000000..100379c4b926
--- /dev/null
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -0,0 +1,114 @@
1/*
2 * File: arch/blackfin/mach-bf548/boards/ezkit.c
3 * Based on: arch/blackfin/mach-bf537/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2007 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h>
37#include <asm/irq.h>
38#include <linux/irq.h>
39#include <linux/interrupt.h>
40#include <asm/bfin5xx_spi.h>
41
42/*
43 * Name the Board for the /proc/cpuinfo
44 */
45char *bfin_board_name = "ADSP-BF548-EZKIT";
46
47/*
48 * Driver needs to know address, irq and flag pin.
49 */
50
51#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
52static struct platform_device rtc_device = {
53 .name = "rtc-bfin",
54 .id = -1,
55};
56#endif
57
58#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
59static struct resource bfin_uart_resources[] = {
60#ifdef CONFIG_SERIAL_BFIN_UART0
61 {
62 .start = 0xFFC00400,
63 .end = 0xFFC004FF,
64 .flags = IORESOURCE_MEM,
65 },
66#endif
67#ifdef CONFIG_SERIAL_BFIN_UART1
68 {
69 .start = 0xFFC02000,
70 .end = 0xFFC020FF,
71 .flags = IORESOURCE_MEM,
72 },
73#endif
74#ifdef CONFIG_SERIAL_BFIN_UART2
75 {
76 .start = 0xFFC02100,
77 .end = 0xFFC021FF,
78 .flags = IORESOURCE_MEM,
79 },
80#endif
81#ifdef CONFIG_SERIAL_BFIN_UART3
82 {
83 .start = 0xFFC03100,
84 .end = 0xFFC031FF,
85 },
86#endif
87};
88
89static struct platform_device bfin_uart_device = {
90 .name = "bfin-uart",
91 .id = 1,
92 .num_resources = ARRAY_SIZE(bfin_uart_resources),
93 .resource = bfin_uart_resources,
94};
95#endif
96
97static struct platform_device *ezkit_devices[] __initdata = {
98#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
99 &rtc_device,
100#endif
101
102#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
103 &bfin_uart_device,
104#endif
105};
106
107static int __init stamp_init(void)
108{
109 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
110 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
111 return 0;
112}
113
114arch_initcall(stamp_init);
diff --git a/arch/blackfin/mach-bf548/boards/led.S b/arch/blackfin/mach-bf548/boards/led.S
new file mode 100644
index 000000000000..f47daf3770d0
--- /dev/null
+++ b/arch/blackfin/mach-bf548/boards/led.S
@@ -0,0 +1,172 @@
1/****************************************************
2 * LED1 ---- PG6 LED2 ---- PG7 *
3 * LED3 ---- PG8 LED4 ---- PG9 *
4 * LED5 ---- PG10 LED6 ---- PG11 *
5 ****************************************************/
6
7#include <linux/linkage.h>
8#include <asm/blackfin.h>
9
10/* All functions in this file save the registers they uses.
11 So there is no need to save any registers before calling them. */
12
13 .text;
14
15/* Initialize LEDs. */
16
17ENTRY(_led_init)
18 LINK 0;
19 [--SP] = P0;
20 [--SP] = R0;
21 [--SP] = R1;
22 [--SP] = R2;
23 R1 = (PG6|PG7|PG8|PG9|PG10|PG11)(Z);
24 R2 = ~R1;
25
26 P0.H = hi(PORTG_FER);
27 P0.L = lo(PORTG_FER);
28 R0 = W[P0](Z);
29 SSYNC;
30 R0 = R0 & R2;
31 W[P0] = R0.L;
32 SSYNC;
33
34 P0.H = hi(PORTG_DIR_SET);
35 P0.L = lo(PORTG_DIR_SET);
36 W[P0] = R1.L;
37 SSYNC;
38
39 P0.H = hi(PORTG_INEN);
40 P0.L = lo(PORTG_INEN);
41 R0 = W[P0](Z);
42 SSYNC;
43 R0 = R0 & R2;
44 W[P0] = R0.L;
45 SSYNC;
46
47 R2 = [SP++];
48 R1 = [SP++];
49 R0 = [SP++];
50 P0 = [SP++];
51 RTS;
52 .size _led_init, .-_led_init
53
54/* Set one LED on. Leave other LEDs unchanged.
55 It expects the LED number passed through R0. */
56
57ENTRY(_led_on)
58 LINK 0;
59 [--SP] = P0;
60 [--SP] = R1;
61 CALL _led_init;
62 R1 = 1;
63 R0 += 5;
64 R1 <<= R0;
65 P0.H = hi(PORTG_SET);
66 P0.L = lo(PORTG_SET);
67 W[P0] = R1.L;
68 SSYNC;
69 R1 = [SP++];
70 P0 = [SP++];
71 UNLINK;
72 RTS;
73 .size _led_on, .-_led_on
74
75/* Set one LED off. Leave other LEDs unchanged. */
76
77ENTRY(_led_off)
78 LINK 0;
79 [--SP] = P0;
80 [--SP] = R1;
81 CALL _led_init;
82 R1 = 1;
83 R0 += 5;
84 R1 <<= R0;
85 P0.H = hi(PORTG_CLEAR);
86 P0.L = lo(PORTG_CLEAR);
87 W[P0] = R1.L;
88 SSYNC;
89 R1 = [SP++];
90 P0 = [SP++];
91 UNLINK;
92 RTS;
93 .size _led_off, .-_led_off
94
95/* Toggle one LED. Leave other LEDs unchanged. */
96
97ENTRY(_led_toggle)
98 LINK 0;
99 [--SP] = P0;
100 [--SP] = R1;
101 CALL _led_init;
102 R1 = 1;
103 R0 += 5;
104 R1 <<= R0;
105 P0.H = hi(PORTG);
106 P0.L = lo(PORTG);
107 R0 = W[P0](Z);
108 SSYNC;
109 R0 = R0 ^ R1;
110 W[P0] = R0.L;
111 SSYNC;
112 R1 = [SP++];
113 P0 = [SP++];
114 UNLINK;
115 RTS;
116 .size _led_toggle, .-_led_toggle
117
118/* Display the number using LEDs in binary format. */
119
120ENTRY(_led_disp_num)
121 LINK 0;
122 [--SP] = P0;
123 [--SP] = R1;
124 [--SP] = R2;
125 CALL _led_init;
126 R1 = 0x3f(X);
127 R0 = R0 & R1;
128 R2 = 6(X);
129 R0 <<= R2;
130 R1 <<= R2;
131 P0.H = hi(PORTG);
132 P0.L = lo(PORTG);
133 R2 = W[P0](Z);
134 SSYNC;
135 R1 = ~R1;
136 R2 = R2 & R1;
137 R2 = R2 | R0;
138 W[P0] = R2.L;
139 SSYNC;
140 R2 = [SP++];
141 R1 = [SP++];
142 P0 = [SP++];
143 UNLINK;
144 RTS;
145 .size _led_disp_num, .-_led_disp_num
146
147/* Toggle the number using LEDs in binary format. */
148
149ENTRY(_led_toggle_num)
150 LINK 0;
151 [--SP] = P0;
152 [--SP] = R1;
153 [--SP] = R2;
154 CALL _led_init;
155 R1 = 0x3f(X);
156 R0 = R0 & R1;
157 R1 = 6(X);
158 R0 <<= R1;
159 P0.H = hi(PORTG);
160 P0.L = lo(PORTG);
161 R1 = W[P0](Z);
162 SSYNC;
163 R1 = R1 ^ R0;
164 W[P0] = R1.L;
165 SSYNC;
166 R2 = [SP++];
167 R1 = [SP++];
168 P0 = [SP++];
169 UNLINK;
170 RTS;
171 .size _led_toggle_num, .-_led_toggle_num
172
diff --git a/arch/blackfin/mach-bf548/cpu.c b/arch/blackfin/mach-bf548/cpu.c
new file mode 100644
index 000000000000..4298a3ccfbfc
--- /dev/null
+++ b/arch/blackfin/mach-bf548/cpu.c
@@ -0,0 +1,159 @@
1/*
2 * File: arch/blackfin/mach-bf548/cpu.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: clock scaling for the bf54x
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/init.h>
33#include <linux/cpufreq.h>
34#include <asm/dpmc.h>
35#include <linux/fs.h>
36#include <asm/bfin-global.h>
37
38/* CONFIG_CLKIN_HZ=25000000 */
39#define VCO5 (CONFIG_CLKIN_HZ*45)
40#define VCO4 (CONFIG_CLKIN_HZ*36)
41#define VCO3 (CONFIG_CLKIN_HZ*27)
42#define VCO2 (CONFIG_CLKIN_HZ*18)
43#define VCO1 (CONFIG_CLKIN_HZ*9)
44#define VCO(x) VCO##x
45
46#define MFREQ(x) {VCO(x),VCO(x)/4},{VCO(x),VCO(x)/2},{VCO(x),VCO(x)}
47/* frequency */
48static struct cpufreq_frequency_table bf548_freq_table[] = {
49 MFREQ(1),
50 MFREQ(3),
51 {VCO4, VCO4 / 2}, {VCO4, VCO4},
52 MFREQ(5),
53 {0, CPUFREQ_TABLE_END},
54};
55
56/*
57 * dpmc_fops->ioctl()
58 * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
59 */
60static int bf548_getfreq(unsigned int cpu)
61{
62 unsigned long cclk_mhz;
63
64 /* The driver only support single cpu */
65 if (cpu == 0)
66 dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz);
67 else
68 cclk_mhz = -1;
69
70 return cclk_mhz;
71}
72
73static int bf548_target(struct cpufreq_policy *policy,
74 unsigned int target_freq, unsigned int relation)
75{
76 unsigned long cclk_mhz;
77 unsigned long vco_mhz;
78 unsigned long flags;
79 unsigned int index;
80 struct cpufreq_freqs freqs;
81
82 if (cpufreq_frequency_table_target(policy, bf548_freq_table, target_freq, relation, &index))
83 return -EINVAL;
84
85 cclk_mhz = bf548_freq_table[index].frequency;
86 vco_mhz = bf548_freq_table[index].index;
87
88 dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz);
89 freqs.old = bf548_getfreq(0);
90 freqs.new = cclk_mhz;
91 freqs.cpu = 0;
92
93 pr_debug("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n",
94 cclk_mhz, vco_mhz, index, target_freq, freqs.old);
95
96 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
97 local_irq_save(flags);
98 dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz);
99 local_irq_restore(flags);
100 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
101
102 vco_mhz = get_vco();
103 cclk_mhz = get_cclk();
104 return 0;
105}
106
107/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
108 * this platform, anyway.
109 */
110static int bf548_verify_speed(struct cpufreq_policy *policy)
111{
112 return cpufreq_frequency_table_verify(policy, &bf548_freq_table);
113}
114
115static int __init __bf548_cpu_init(struct cpufreq_policy *policy)
116{
117 if (policy->cpu != 0)
118 return -EINVAL;
119
120 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
121
122 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
123 /*Now ,only support one cpu */
124 policy->cur = bf548_getfreq(0);
125 cpufreq_frequency_table_get_attr(bf548_freq_table, policy->cpu);
126 return cpufreq_frequency_table_cpuinfo(policy, bf548_freq_table);
127}
128
129static struct freq_attr *bf548_freq_attr[] = {
130 &cpufreq_freq_attr_scaling_available_freqs,
131 NULL,
132};
133
134static struct cpufreq_driver bf548_driver = {
135 .verify = bf548_verify_speed,
136 .target = bf548_target,
137 .get = bf548_getfreq,
138 .init = __bf548_cpu_init,
139 .name = "bf548",
140 .owner = THIS_MODULE,
141 .attr = bf548_freq_attr,
142};
143
144static int __init bf548_cpu_init(void)
145{
146 return cpufreq_register_driver(&bf548_driver);
147}
148
149static void __exit bf548_cpu_exit(void)
150{
151 cpufreq_unregister_driver(&bf548_driver);
152}
153
154MODULE_AUTHOR("Mickael Kang");
155MODULE_DESCRIPTION("cpufreq driver for BF548 CPU");
156MODULE_LICENSE("GPL");
157
158module_init(bf548_cpu_init);
159module_exit(bf548_cpu_exit);
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
new file mode 100644
index 000000000000..a8184113be48
--- /dev/null
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -0,0 +1,156 @@
1/*
2 * File: arch/blackfin/mach-bf561/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <asm/blackfin.h>
31#include <asm/dma.h>
32
33 struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
34 (struct dma_register *) DMA0_NEXT_DESC_PTR,
35 (struct dma_register *) DMA1_NEXT_DESC_PTR,
36 (struct dma_register *) DMA2_NEXT_DESC_PTR,
37 (struct dma_register *) DMA3_NEXT_DESC_PTR,
38 (struct dma_register *) DMA4_NEXT_DESC_PTR,
39 (struct dma_register *) DMA5_NEXT_DESC_PTR,
40 (struct dma_register *) DMA6_NEXT_DESC_PTR,
41 (struct dma_register *) DMA7_NEXT_DESC_PTR,
42 (struct dma_register *) DMA8_NEXT_DESC_PTR,
43 (struct dma_register *) DMA9_NEXT_DESC_PTR,
44 (struct dma_register *) DMA10_NEXT_DESC_PTR,
45 (struct dma_register *) DMA11_NEXT_DESC_PTR,
46 (struct dma_register *) DMA12_NEXT_DESC_PTR,
47 (struct dma_register *) DMA13_NEXT_DESC_PTR,
48 (struct dma_register *) DMA14_NEXT_DESC_PTR,
49 (struct dma_register *) DMA15_NEXT_DESC_PTR,
50 (struct dma_register *) DMA16_NEXT_DESC_PTR,
51 (struct dma_register *) DMA17_NEXT_DESC_PTR,
52 (struct dma_register *) DMA18_NEXT_DESC_PTR,
53 (struct dma_register *) DMA19_NEXT_DESC_PTR,
54 (struct dma_register *) DMA20_NEXT_DESC_PTR,
55 (struct dma_register *) DMA21_NEXT_DESC_PTR,
56 (struct dma_register *) DMA22_NEXT_DESC_PTR,
57 (struct dma_register *) DMA23_NEXT_DESC_PTR,
58 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
59 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
60 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
61 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
62 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
63 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
64 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
65 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
66};
67
68int channel2irq(unsigned int channel)
69{
70 int ret_irq = -1;
71
72 switch (channel) {
73 case CH_SPORT0_RX:
74 ret_irq = IRQ_SPORT0_RX;
75 break;
76 case CH_SPORT0_TX:
77 ret_irq = IRQ_SPORT0_TX;
78 break;
79 case CH_SPORT1_RX:
80 ret_irq = IRQ_SPORT1_RX;
81 break;
82 case CH_SPORT1_TX:
83 ret_irq = IRQ_SPORT1_TX;
84 case CH_SPI0:
85 ret_irq = IRQ_SPI0;
86 break;
87 case CH_SPI1:
88 ret_irq = IRQ_SPI1;
89 break;
90 case CH_UART0_RX:
91 ret_irq = IRQ_UART_RX;
92 break;
93 case CH_UART0_TX:
94 ret_irq = IRQ_UART_TX;
95 break;
96 case CH_UART1_RX:
97 ret_irq = IRQ_UART_RX;
98 break;
99 case CH_UART1_TX:
100 ret_irq = IRQ_UART_TX;
101 break;
102 case CH_EPPI0:
103 ret_irq = IRQ_EPPI0;
104 break;
105 case CH_EPPI1:
106 ret_irq = IRQ_EPPI1;
107 break;
108 case CH_EPPI2:
109 ret_irq = IRQ_EPPI2;
110 break;
111 case CH_PIXC_IMAGE:
112 ret_irq = IRQ_PIXC_IN0;
113 break;
114 case CH_PIXC_OVERLAY:
115 ret_irq = IRQ_PIXC_IN1;
116 break;
117 case CH_PIXC_OUTPUT:
118 ret_irq = IRQ_PIXC_OUT;
119 break;
120 case CH_SPORT2_RX:
121 ret_irq = IRQ_SPORT2_RX;
122 break;
123 case CH_SPORT2_TX:
124 ret_irq = IRQ_SPORT2_TX;
125 break;
126 case CH_SPORT3_RX:
127 ret_irq = IRQ_SPORT3_RX;
128 break;
129 case CH_SPORT3_TX:
130 ret_irq = IRQ_SPORT3_TX;
131 break;
132 case CH_SDH:
133 ret_irq = IRQ_SDH;
134 break;
135 case CH_SPI2:
136 ret_irq = IRQ_SPI2;
137 break;
138 case CH_MEM_STREAM0_SRC:
139 case CH_MEM_STREAM0_DEST:
140 ret_irq = IRQ_MDMAS0;
141 break;
142 case CH_MEM_STREAM1_SRC:
143 case CH_MEM_STREAM1_DEST:
144 ret_irq = IRQ_MDMAS1;
145 break;
146 case CH_MEM_STREAM2_SRC:
147 case CH_MEM_STREAM2_DEST:
148 ret_irq = IRQ_MDMAS2;
149 break;
150 case CH_MEM_STREAM3_SRC:
151 case CH_MEM_STREAM3_DEST:
152 ret_irq = IRQ_MDMAS3;
153 break;
154 }
155 return ret_irq;
156}
diff --git a/arch/blackfin/mach-bf548/gpio.c b/arch/blackfin/mach-bf548/gpio.c
new file mode 100644
index 000000000000..854896d6ceda
--- /dev/null
+++ b/arch/blackfin/mach-bf548/gpio.c
@@ -0,0 +1,175 @@
1/*
2 * File: arch/blackfin/mach-bf548/gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
10 * Copyright 2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <linux/err.h>
32#include <asm/blackfin.h>
33#include <asm/gpio.h>
34#include <linux/irq.h>
35
36static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
37 (struct gpio_port_t *) PORTA_FER,
38 (struct gpio_port_t *) PORTB_FER,
39 (struct gpio_port_t *) PORTC_FER,
40 (struct gpio_port_t *) PORTD_FER,
41 (struct gpio_port_t *) PORTE_FER,
42 (struct gpio_port_t *) PORTF_FER,
43 (struct gpio_port_t *) PORTG_FER,
44 (struct gpio_port_t *) PORTH_FER,
45 (struct gpio_port_t *) PORTI_FER,
46 (struct gpio_port_t *) PORTJ_FER,
47};
48
49static unsigned short reserved_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
50
51inline int check_gpio(unsigned short gpio)
52{
53 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 \
54 || gpio == GPIO_PH14 || gpio == GPIO_PH15 \
55 || gpio > MAX_BLACKFIN_GPIOS)
56 return -EINVAL;
57 return 0;
58}
59
60static void port_setup(unsigned short gpio, unsigned short usage)
61{
62 if (usage == GPIO_USAGE) {
63 if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio))
64 printk(KERN_WARNING "bfin-gpio: Possible Conflict with Peripheral "
65 "usage and GPIO %d detected!\n", gpio);
66 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
67 } else
68 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
69 SSYNC();
70}
71
72static int __init bfin_gpio_init(void)
73{
74 int i;
75
76 printk(KERN_INFO "Blackfin GPIO Controller\n");
77
78 for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE)
79 reserved_map[gpio_bank(i)] = 0;
80
81 return 0;
82}
83
84arch_initcall(bfin_gpio_init);
85
86
87/***********************************************************
88*
89* FUNCTIONS: Blackfin GPIO Driver
90*
91* INPUTS/OUTPUTS:
92* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
93*
94*
95* DESCRIPTION: Blackfin GPIO Driver API
96*
97* CAUTION:
98*************************************************************
99* MODIFICATION HISTORY :
100**************************************************************/
101
102int gpio_request(unsigned short gpio, const char *label)
103{
104 unsigned long flags;
105
106 if (check_gpio(gpio) < 0)
107 return -EINVAL;
108
109 local_irq_save(flags);
110
111 if (unlikely(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
112 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio);
113 dump_stack();
114 local_irq_restore(flags);
115 return -EBUSY;
116 }
117 reserved_map[gpio_bank(gpio)] |= gpio_bit(gpio);
118
119 local_irq_restore(flags);
120
121 port_setup(gpio, GPIO_USAGE);
122
123 return 0;
124}
125EXPORT_SYMBOL(gpio_request);
126
127
128void gpio_free(unsigned short gpio)
129{
130 unsigned long flags;
131
132 if (check_gpio(gpio) < 0)
133 return;
134
135 local_irq_save(flags);
136
137 if (unlikely(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
138 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
139 dump_stack();
140 local_irq_restore(flags);
141 return;
142 }
143
144 reserved_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
145
146 local_irq_restore(flags);
147}
148EXPORT_SYMBOL(gpio_free);
149
150
151void gpio_direction_input(unsigned short gpio)
152{
153 unsigned long flags;
154
155 BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)));
156
157 local_irq_save(flags);
158 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
159 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
160 local_irq_restore(flags);
161}
162EXPORT_SYMBOL(gpio_direction_input);
163
164void gpio_direction_output(unsigned short gpio)
165{
166 unsigned long flags;
167
168 BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)));
169
170 local_irq_save(flags);
171 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
172 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
173 local_irq_restore(flags);
174}
175EXPORT_SYMBOL(gpio_direction_output);
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
new file mode 100644
index 000000000000..0e1a25447391
--- /dev/null
+++ b/arch/blackfin/mach-bf548/head.S
@@ -0,0 +1,507 @@
1/*
2 * File: arch/blackfin/mach-bf548/head.S
3 * Based on: arch/blackfin/mach-bf537/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5 *
6 * Created: 1998
7 * Description: Startup code for Blackfin BF548
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <asm/blackfin.h>
32#if CONFIG_BFIN_KERNEL_CLOCK
33#include <asm/mach/mem_init.h>
34#endif
35
36.global __rambase
37.global __ramstart
38.global __ramend
39.extern ___bss_stop
40.extern ___bss_start
41.extern _bf53x_relocate_l1_mem
42
43#define INITIAL_STACK 0xFFB01000
44
45.text
46
47ENTRY(__start)
48ENTRY(__stext)
49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0;
51 /* Set the SYSCFG register */
52 R0 = 0x36;
53 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
54 R0 = 0;
55
56 /* Clear Out All the data and pointer Registers*/
57 R1 = R0;
58 R2 = R0;
59 R3 = R0;
60 R4 = R0;
61 R5 = R0;
62 R6 = R0;
63
64 P0 = R0;
65 P1 = R0;
66 P2 = R0;
67 P3 = R0;
68 P4 = R0;
69 P5 = R0;
70
71 LC0 = r0;
72 LC1 = r0;
73 L0 = r0;
74 L1 = r0;
75 L2 = r0;
76 L3 = r0;
77
78 /* Clear Out All the DAG Registers*/
79 B0 = r0;
80 B1 = r0;
81 B2 = r0;
82 B3 = r0;
83
84 I0 = r0;
85 I1 = r0;
86 I2 = r0;
87 I3 = r0;
88
89 M0 = r0;
90 M1 = r0;
91 M2 = r0;
92 M3 = r0;
93
94 /* Turn off the icache */
95 p0.l = (IMEM_CONTROL & 0xFFFF);
96 p0.h = (IMEM_CONTROL >> 16);
97 R1 = [p0];
98 R0 = ~ENICPLB;
99 R0 = R0 & R1;
100 [p0] = R0;
101 SSYNC;
102
103 /* Turn off the dcache */
104 p0.l = (DMEM_CONTROL & 0xFFFF);
105 p0.h = (DMEM_CONTROL >> 16);
106 R1 = [p0];
107 R0 = ~ENDCPLB;
108 R0 = R0 & R1;
109 [p0] = R0;
110 SSYNC;
111
112 /* Initialize stack pointer */
113 SP.L = LO(INITIAL_STACK);
114 SP.H = HI(INITIAL_STACK);
115 FP = SP;
116 USP = SP;
117
118 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
119 call _bf53x_relocate_l1_mem;
120#if CONFIG_BFIN_KERNEL_CLOCK
121 call _start_dma_code;
122#endif
123 /* Code for initializing Async memory banks */
124
125 p2.h = hi(EBIU_AMBCTL1);
126 p2.l = lo(EBIU_AMBCTL1);
127 r0.h = hi(AMBCTL1VAL);
128 r0.l = lo(AMBCTL1VAL);
129 [p2] = r0;
130 ssync;
131
132 p2.h = hi(EBIU_AMBCTL0);
133 p2.l = lo(EBIU_AMBCTL0);
134 r0.h = hi(AMBCTL0VAL);
135 r0.l = lo(AMBCTL0VAL);
136 [p2] = r0;
137 ssync;
138
139 p2.h = hi(EBIU_AMGCTL);
140 p2.l = lo(EBIU_AMGCTL);
141 r0 = AMGCTLVAL;
142 w[p2] = r0;
143 ssync;
144
145 /* This section keeps the processor in supervisor mode
146 * during kernel boot. Switches to user mode at end of boot.
147 * See page 3-9 of Hardware Reference manual for documentation.
148 */
149
150 /* EVT15 = _real_start */
151
152 p0.l = lo(EVT15);
153 p0.h = hi(EVT15);
154 p1.l = _real_start;
155 p1.h = _real_start;
156 [p0] = p1;
157 csync;
158
159 p0.l = lo(IMASK);
160 p0.h = hi(IMASK);
161 p1.l = IMASK_IVG15;
162 p1.h = 0x0;
163 [p0] = p1;
164 csync;
165
166 raise 15;
167 p0.l = .LWAIT_HERE;
168 p0.h = .LWAIT_HERE;
169 reti = p0;
170#if defined (ANOMALY_05000281)
171 nop;
172 nop;
173 nop;
174#endif
175 rti;
176
177.LWAIT_HERE:
178 jump .LWAIT_HERE;
179
180ENTRY(_real_start)
181 [ -- sp ] = reti;
182 p0.l = lo(WDOG_CTL);
183 p0.h = hi(WDOG_CTL);
184 r0 = 0xAD6(z);
185 w[p0] = r0; /* watchdog off for now */
186 ssync;
187
188 /* Code update for BSS size == 0
189 * Zero out the bss region.
190 */
191
192 p1.l = ___bss_start;
193 p1.h = ___bss_start;
194 p2.l = ___bss_stop;
195 p2.h = ___bss_stop;
196 r0 = 0;
197 p2 -= p1;
198 lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
199.L_clear_bss:
200 B[p1++] = r0;
201
202 /* In case there is a NULL pointer reference
203 * Zero out region before stext
204 */
205
206 p1.l = 0x0;
207 p1.h = 0x0;
208 r0.l = __stext;
209 r0.h = __stext;
210 r0 = r0 >> 1;
211 p2 = r0;
212 r0 = 0;
213 lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
214.L_clear_zero:
215 W[p1++] = r0;
216
217 /* pass the uboot arguments to the global value command line */
218 R0 = R7;
219 call _cmdline_init;
220
221 p1.l = __rambase;
222 p1.h = __rambase;
223 r0.l = __sdata;
224 r0.h = __sdata;
225 [p1] = r0;
226
227 p1.l = __ramstart;
228 p1.h = __ramstart;
229 p3.l = ___bss_stop;
230 p3.h = ___bss_stop;
231
232 r1 = p3;
233 [p1] = r1;
234
235
236 /*
237 * load the current thread pointer and stack
238 */
239 r1.l = _init_thread_union;
240 r1.h = _init_thread_union;
241
242 r2.l = 0x2000;
243 r2.h = 0x0000;
244 r1 = r1 + r2;
245 sp = r1;
246 usp = sp;
247 fp = sp;
248 call _start_kernel;
249.L_exit:
250 jump.s .L_exit;
251
252.section .l1.text
253#if CONFIG_BFIN_KERNEL_CLOCK
254ENTRY(_start_dma_code)
255
256 /* Enable PHY CLK buffer output */
257 p0.h = hi(VR_CTL);
258 p0.l = lo(VR_CTL);
259 r0.l = w[p0];
260 bitset(r0, 14);
261 w[p0] = r0.l;
262 ssync;
263
264 p0.h = hi(SIC_IWR);
265 p0.l = lo(SIC_IWR);
266 r0.l = 0x1;
267 r0.h = 0x0;
268 [p0] = r0;
269 SSYNC;
270
271 /*
272 * Set PLL_CTL
273 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
274 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
275 * - [7] = output delay (add 200ps of delay to mem signals)
276 * - [6] = input delay (add 200ps of input delay to mem signals)
277 * - [5] = PDWN : 1=All Clocks off
278 * - [3] = STOPCK : 1=Core Clock off
279 * - [1] = PLL_OFF : 1=Disable Power to PLL
280 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
281 * all other bits set to zero
282 */
283
284 p0.h = hi(PLL_LOCKCNT);
285 p0.l = lo(PLL_LOCKCNT);
286 r0 = 0x300(Z);
287 w[p0] = r0.l;
288 ssync;
289
290 P2.H = hi(EBIU_SDGCTL);
291 P2.L = lo(EBIU_SDGCTL);
292 R0 = [P2];
293 BITSET (R0, 24);
294 [P2] = R0;
295 SSYNC;
296
297 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
298 r0 = r0 << 9; /* Shift it over, */
299 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
300 r0 = r1 | r0;
301 r1 = PLL_BYPASS; /* Bypass the PLL? */
302 r1 = r1 << 8; /* Shift it over */
303 r0 = r1 | r0; /* add them all together */
304
305 p0.h = hi(PLL_CTL);
306 p0.l = lo(PLL_CTL); /* Load the address */
307 cli r2; /* Disable interrupts */
308 ssync;
309 w[p0] = r0.l; /* Set the value */
310 idle; /* Wait for the PLL to stablize */
311 sti r2; /* Enable interrupts */
312
313.Lcheck_again:
314 p0.h = hi(PLL_STAT);
315 p0.l = lo(PLL_STAT);
316 R0 = W[P0](Z);
317 CC = BITTST(R0,5);
318 if ! CC jump .Lcheck_again;
319
320 /* Configure SCLK & CCLK Dividers */
321 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
322 p0.h = hi(PLL_DIV);
323 p0.l = lo(PLL_DIV);
324 w[p0] = r0.l;
325 ssync;
326
327 p0.l = lo(EBIU_SDRRC);
328 p0.h = hi(EBIU_SDRRC);
329 r0 = mem_SDRRC;
330 w[p0] = r0.l;
331 ssync;
332
333 p0.l = (EBIU_SDBCTL & 0xFFFF);
334 p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
335 r0 = mem_SDBCTL;
336 w[p0] = r0.l;
337 ssync;
338
339 P2.H = hi(EBIU_SDGCTL);
340 P2.L = lo(EBIU_SDGCTL);
341 R0 = [P2];
342 BITCLR (R0, 24);
343 p0.h = hi(EBIU_SDSTAT);
344 p0.l = lo(EBIU_SDSTAT);
345 r2.l = w[p0];
346 cc = bittst(r2,3);
347 if !cc jump .Lskip;
348 NOP;
349 BITSET (R0, 23);
350.Lskip:
351 [P2] = R0;
352 SSYNC;
353
354 R0.L = lo(mem_SDGCTL);
355 R0.H = hi(mem_SDGCTL);
356 R1 = [p2];
357 R1 = R1 | R0;
358 [P2] = R1;
359 SSYNC;
360
361 p0.h = hi(SIC_IWR);
362 p0.l = lo(SIC_IWR);
363 r0.l = lo(IWR_ENABLE_ALL);
364 r0.h = hi(IWR_ENABLE_ALL);
365 [p0] = r0;
366 SSYNC;
367
368 RTS;
369#endif /* CONFIG_BFIN_KERNEL_CLOCK */
370
371ENTRY(_bfin_reset)
372 /* No more interrupts to be handled*/
373 CLI R6;
374 SSYNC;
375
376#if defined(CONFIG_MTD_M25P80)
377/*
378 * The following code fix the SPI flash reboot issue,
379 * /CS signal of the chip which is using PF10 return to GPIO mode
380 */
381 p0.h = hi(PORTF_FER);
382 p0.l = lo(PORTF_FER);
383 r0.l = 0x0000;
384 w[p0] = r0.l;
385 SSYNC;
386
387/* /CS return to high */
388 p0.h = hi(PORTFIO);
389 p0.l = lo(PORTFIO);
390 r0.l = 0xFFFF;
391 w[p0] = r0.l;
392 SSYNC;
393
394/* Delay some time, This is necessary */
395 r1.h = 0;
396 r1.l = 0x400;
397 p1 = r1;
398 lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1;
399_delay_lab1:
400 r0.h = 0;
401 r0.l = 0x8000;
402 p0 = r0;
403 lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0;
404_delay_lab0:
405 nop;
406_delay_lab0_end:
407 nop;
408_delay_lab1_end:
409 nop;
410#endif
411
412 /* Clear the bits 13-15 in SWRST if they werent cleared */
413 p0.h = hi(SWRST);
414 p0.l = lo(SWRST);
415 csync;
416 r0.l = w[p0];
417
418 /* Clear the IMASK register */
419 p0.h = hi(IMASK);
420 p0.l = lo(IMASK);
421 r0 = 0x0;
422 [p0] = r0;
423
424 /* Clear the ILAT register */
425 p0.h = hi(ILAT);
426 p0.l = lo(ILAT);
427 r0 = [p0];
428 [p0] = r0;
429 SSYNC;
430
431 /* Disable the WDOG TIMER */
432 p0.h = hi(WDOG_CTL);
433 p0.l = lo(WDOG_CTL);
434 r0.l = 0xAD6;
435 w[p0] = r0.l;
436 SSYNC;
437
438 /* Clear the sticky bit incase it is already set */
439 p0.h = hi(WDOG_CTL);
440 p0.l = lo(WDOG_CTL);
441 r0.l = 0x8AD6;
442 w[p0] = r0.l;
443 SSYNC;
444
445 /* Program the count value */
446 R0.l = 0x100;
447 R0.h = 0x0;
448 P0.h = hi(WDOG_CNT);
449 P0.l = lo(WDOG_CNT);
450 [P0] = R0;
451 SSYNC;
452
453 /* Program WDOG_STAT if necessary */
454 P0.h = hi(WDOG_CTL);
455 P0.l = lo(WDOG_CTL);
456 R0 = W[P0](Z);
457 CC = BITTST(R0,1);
458 if !CC JUMP .LWRITESTAT;
459 CC = BITTST(R0,2);
460 if !CC JUMP .LWRITESTAT;
461 JUMP .LSKIP_WRITE;
462
463.LWRITESTAT:
464 /* When watch dog timer is enabled,
465 * a write to STAT will load the contents of CNT to STAT
466 */
467 R0 = 0x0000(z);
468 P0.h = hi(WDOG_STAT);
469 P0.l = lo(WDOG_STAT)
470 [P0] = R0;
471 SSYNC;
472
473.LSKIP_WRITE:
474 /* Enable the reset event */
475 P0.h = hi(WDOG_CTL);
476 P0.l = lo(WDOG_CTL);
477 R0 = W[P0](Z);
478 BITCLR(R0,1);
479 BITCLR(R0,2);
480 W[P0] = R0.L;
481 SSYNC;
482 NOP;
483
484 /* Enable the wdog counter */
485 R0 = W[P0](Z);
486 BITCLR(R0,4);
487 W[P0] = R0.L;
488 SSYNC;
489
490 IDLE;
491
492 RTS;
493
494.data
495
496/*
497 * Set up the usable of RAM stuff. Size of RAM is determined then
498 * an initial stack set up at the end.
499 */
500
501.align 4
502__rambase:
503.long 0
504__ramstart:
505.long 0
506__ramend:
507.long 0
diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c
new file mode 100644
index 000000000000..dde450f119e1
--- /dev/null
+++ b/arch/blackfin/mach-bf548/ints-priority.c
@@ -0,0 +1,137 @@
1/*
2 * File: arch/blackfin/mach-bf537/ints-priority.c
3 * Based on: arch/blackfin/mach-bf533/ints-priority.c
4 * Author: Michael Hennerich
5 *
6 * Created:
7 * Description: Set up the interupt priorities
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <asm/blackfin.h>
32#include <asm/irq.h>
33
34void program_IAR(void)
35{
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
38 ((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) |
39 ((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) |
40 ((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) |
41 ((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) |
42 ((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) |
43 ((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) |
44 ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
45
46 bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) |
47 ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
48 ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
49 ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
50 ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
51 ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
52 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
53 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
54
55 bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
56 ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
57 ((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) |
58 ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
59 ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
60 ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
61 ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS));
62
63 bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
64 ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
65 ((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) |
66 ((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) |
67 ((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) |
68 ((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) |
69 ((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) |
70 ((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS));
71
72 bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) |
73 ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
74 ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
75 ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
76 ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
77 ((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) |
78 ((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) |
79 ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
80
81 bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
82 ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
83 ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
84 ((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) |
85 ((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) |
86 ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
87 ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
88 ((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS));
89
90 bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) |
91 ((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) |
92 ((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) |
93 ((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) |
94 ((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) |
95 ((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) |
96 ((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) |
97 ((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS));
98
99 bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) |
100 ((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) |
101 ((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) |
102 ((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) |
103 ((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) |
104 ((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) |
105 ((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS));
106
107 bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) |
108 ((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) |
109 ((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) |
110 ((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) |
111 ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
112 ((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) |
113 ((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) |
114 ((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS));
115
116 bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) |
117 ((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) |
118 ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
119 ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
120 ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
121 ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) |
122 ((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS));
123
124 bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
125 ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS));
126
127 bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
128 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
129 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
130 ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
131 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
132 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
133 ((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) |
134 ((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS));
135
136 SSYNC();
137}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 11:51:23 -0500