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authorMike Frysinger <michael.frysinger@analog.com>2007-10-10 12:22:35 -0400
committerBryan Wu <bryan.wu@analog.com>2007-10-10 12:22:35 -0400
commit168f1212c098727f2509fe0f66bd30d7209a8159 (patch)
treee749898e8ab56131a12d8fc489081321abb3ff2f /arch/blackfin/mach-bf548
parent27d875f2c134c4b26860ccdd03b4c52cce4efc2c (diff)
Blackfin arch: rewrite our reboot code in C
rewrite our reboot code in C rather than assembly to be like other architectures and to allow board maintainers to define custom behavior Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf548')
-rw-r--r--arch/blackfin/mach-bf548/head.S125
1 files changed, 0 insertions, 125 deletions
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index 937fbef26a51..532ed0930b5e 100644
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -378,131 +378,6 @@ ENTRY(_start_dma_code)
378 RTS; 378 RTS;
379#endif /* CONFIG_BFIN_KERNEL_CLOCK */ 379#endif /* CONFIG_BFIN_KERNEL_CLOCK */
380 380
381ENTRY(_bfin_reset)
382 /* No more interrupts to be handled*/
383 CLI R6;
384 SSYNC;
385
386#if 0 /* Need to determine later if this is here necessary for BF54x */
387#if defined(CONFIG_MTD_M25P80)
388/*
389 * The following code fix the SPI flash reboot issue,
390 * /CS signal of the chip which is using PF10 return to GPIO mode
391 */
392 p0.h = hi(PORTF_FER);
393 p0.l = lo(PORTF_FER);
394 r0.l = 0x0000;
395 w[p0] = r0.l;
396 SSYNC;
397
398/* /CS return to high */
399 p0.h = hi(PORTFIO);
400 p0.l = lo(PORTFIO);
401 r0.l = 0xFFFF;
402 w[p0] = r0.l;
403 SSYNC;
404
405/* Delay some time, This is necessary */
406 r1.h = 0;
407 r1.l = 0x400;
408 p1 = r1;
409 lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1;
410_delay_lab1:
411 r0.h = 0;
412 r0.l = 0x8000;
413 p0 = r0;
414 lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0;
415_delay_lab0:
416 nop;
417_delay_lab0_end:
418 nop;
419_delay_lab1_end:
420 nop;
421#endif
422#endif
423
424 /* Clear the bits 13-15 in SWRST if they werent cleared */
425 p0.h = hi(SWRST);
426 p0.l = lo(SWRST);
427 csync;
428 r0.l = w[p0];
429
430 /* Clear the IMASK register */
431 p0.h = hi(IMASK);
432 p0.l = lo(IMASK);
433 r0 = 0x0;
434 [p0] = r0;
435
436 /* Clear the ILAT register */
437 p0.h = hi(ILAT);
438 p0.l = lo(ILAT);
439 r0 = [p0];
440 [p0] = r0;
441 SSYNC;
442
443 /* Disable the WDOG TIMER */
444 p0.h = hi(WDOG_CTL);
445 p0.l = lo(WDOG_CTL);
446 r0.l = 0xAD6;
447 w[p0] = r0.l;
448 SSYNC;
449
450 /* Clear the sticky bit incase it is already set */
451 p0.h = hi(WDOG_CTL);
452 p0.l = lo(WDOG_CTL);
453 r0.l = 0x8AD6;
454 w[p0] = r0.l;
455 SSYNC;
456
457 /* Program the count value */
458 R0.l = 0x100;
459 R0.h = 0x0;
460 P0.h = hi(WDOG_CNT);
461 P0.l = lo(WDOG_CNT);
462 [P0] = R0;
463 SSYNC;
464
465 /* Program WDOG_STAT if necessary */
466 P0.h = hi(WDOG_CTL);
467 P0.l = lo(WDOG_CTL);
468 R0 = W[P0](Z);
469 CC = BITTST(R0,1);
470 if !CC JUMP .LWRITESTAT;
471 CC = BITTST(R0,2);
472 if !CC JUMP .LWRITESTAT;
473 JUMP .LSKIP_WRITE;
474
475.LWRITESTAT:
476 /* When watch dog timer is enabled,
477 * a write to STAT will load the contents of CNT to STAT
478 */
479 R0 = 0x0000(z);
480 P0.h = hi(WDOG_STAT);
481 P0.l = lo(WDOG_STAT)
482 [P0] = R0;
483 SSYNC;
484
485.LSKIP_WRITE:
486 /* Enable the reset event */
487 P0.h = hi(WDOG_CTL);
488 P0.l = lo(WDOG_CTL);
489 R0 = W[P0](Z);
490 BITCLR(R0,1);
491 BITCLR(R0,2);
492 W[P0] = R0.L;
493 SSYNC;
494 NOP;
495
496 /* Enable the wdog counter */
497 R0 = W[P0](Z);
498 BITCLR(R0,4);
499 W[P0] = R0.L;
500 SSYNC;
501
502 IDLE;
503
504 RTS;
505
506.data 381.data
507 382
508/* 383/*