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authorSonic Zhang <sonic.zhang@analog.com>2007-12-23 10:02:13 -0500
committerBryan Wu <bryan.wu@analog.com>2007-12-23 10:02:13 -0500
commitfb5f00492a748facc9f069c95621e05c148edf53 (patch)
treecf93dbf8140279e4913eb421dd68922a76ba241f /arch/blackfin/mach-bf548
parentc50e19f49830fb651b4b702ad2c3abcdf110b576 (diff)
[Blackfin] arch: Fix bug to Enable kernel to build for bf548 with PM.
On BF548-EZKIT, build kernel faills with power management, video and audio enabled. This patch fix this. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf548')
-rw-r--r--arch/blackfin/mach-bf548/head.S8
-rw-r--r--arch/blackfin/mach-bf548/ints-priority.c2
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index 74b34c7f3629..745662e88759 100644
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -298,8 +298,8 @@ ENTRY(_start_dma_code)
298 w[p0] = r0.l; 298 w[p0] = r0.l;
299 ssync; 299 ssync;
300 300
301 p0.h = hi(SIC_IWR); 301 p0.h = hi(SIC_IWR0);
302 p0.l = lo(SIC_IWR); 302 p0.l = lo(SIC_IWR0);
303 r0.l = 0x1; 303 r0.l = 0x1;
304 r0.h = 0x0; 304 r0.h = 0x0;
305 [p0] = r0; 305 [p0] = r0;
@@ -395,8 +395,8 @@ ENTRY(_start_dma_code)
395 [P2] = R1; 395 [P2] = R1;
396 SSYNC; 396 SSYNC;
397 397
398 p0.h = hi(SIC_IWR); 398 p0.h = hi(SIC_IWR0);
399 p0.l = lo(SIC_IWR); 399 p0.l = lo(SIC_IWR0);
400 r0.l = lo(IWR_ENABLE_ALL); 400 r0.l = lo(IWR_ENABLE_ALL);
401 r0.h = hi(IWR_ENABLE_ALL); 401 r0.h = hi(IWR_ENABLE_ALL);
402 [p0] = r0; 402 [p0] = r0;
diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c
index cb0ebac53c79..05e3b3cb4c0a 100644
--- a/arch/blackfin/mach-bf548/ints-priority.c
+++ b/arch/blackfin/mach-bf548/ints-priority.c
@@ -58,7 +58,7 @@ void program_IAR(void)
58 ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) | 58 ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
59 ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) | 59 ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
60 ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) | 60 ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
61 ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS)); 61 ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCH_POS));
62 62
63 bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) | 63 bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
64 ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) | 64 ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |