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authorMichael Hennerich <michael.hennerich@analog.com>2009-01-07 10:14:39 -0500
committerBryan Wu <cooloney@kernel.org>2009-01-07 10:14:39 -0500
commit73feb5c09dcf0d64beb67aa5e1f79e11a388e0ff (patch)
tree09fa1f153a2ca810ad72978736f85359205d64a3 /arch/blackfin/mach-bf548
parentc97618d3b7b8ef86a966c4b67b54e5ca15814905 (diff)
Blackfin arch: fix bugs and unify BFIN_KERNEL_CLOCK option
- remove duplicated code and headers - add option allowing arbitrary SDRAM/DDR Timing parameters. - mark automatically calculated timings as EXPERIMENTAL - fix comment header block Related to BUGs: - kernel boot up fails with CONFIG_BFIN_KERNEL_CLOCK item on. - kernel does not boot if re-program clocks [ Mike Frysinger <vapier.adi@gmail.com> - fix comment header - mark do_sync static - document the DMA shutdown - simplify SIC_IWR handling - fix ANOMALY_05000265 handling to work as intended ] Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf548')
-rw-r--r--arch/blackfin/mach-bf548/Makefile2
-rw-r--r--arch/blackfin/mach-bf548/head.S158
-rw-r--r--arch/blackfin/mach-bf548/include/mach/mem_init.h255
3 files changed, 0 insertions, 415 deletions
diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile
index 68e5478e95a9..56994b675f9c 100644
--- a/arch/blackfin/mach-bf548/Makefile
+++ b/arch/blackfin/mach-bf548/Makefile
@@ -2,6 +2,4 @@
2# arch/blackfin/mach-bf537/Makefile 2# arch/blackfin/mach-bf537/Makefile
3# 3#
4 4
5extra-y := head.o
6
7obj-y := ints-priority.o dma.o 5obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
deleted file mode 100644
index 93b361dff27b..000000000000
--- a/arch/blackfin/mach-bf548/head.S
+++ /dev/null
@@ -1,158 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf548/head.S
3 * Based on: arch/blackfin/mach-bf537/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5 *
6 * Created: 1998
7 * Description: Startup code for Blackfin BF548
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <linux/init.h>
32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/clocks.h>
35#include <mach/mem_init.h>
36#endif
37
38.section .l1.text
39#ifdef CONFIG_BFIN_KERNEL_CLOCK
40ENTRY(_start_dma_code)
41
42 /* Enable PHY CLK buffer output */
43 p0.h = hi(VR_CTL);
44 p0.l = lo(VR_CTL);
45 r0.l = w[p0];
46 bitset(r0, 14);
47 w[p0] = r0.l;
48 ssync;
49
50 p0.h = hi(SIC_IWR0);
51 p0.l = lo(SIC_IWR0);
52 r0.l = 0x1;
53 r0.h = 0x0;
54 [p0] = r0;
55 SSYNC;
56
57 /*
58 * Set PLL_CTL
59 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
60 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
61 * - [7] = output delay (add 200ps of delay to mem signals)
62 * - [6] = input delay (add 200ps of input delay to mem signals)
63 * - [5] = PDWN : 1=All Clocks off
64 * - [3] = STOPCK : 1=Core Clock off
65 * - [1] = PLL_OFF : 1=Disable Power to PLL
66 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
67 * all other bits set to zero
68 */
69
70 p0.h = hi(PLL_LOCKCNT);
71 p0.l = lo(PLL_LOCKCNT);
72 r0 = 0x300(Z);
73 w[p0] = r0.l;
74 ssync;
75
76 /* enable self refresh via SRREQ */
77 P2.H = hi(EBIU_RSTCTL);
78 P2.L = lo(EBIU_RSTCTL);
79 R0 = [P2];
80 BITSET (R0, 3);
81 [P2] = R0;
82 SSYNC;
83
84 /* wait for SRACK bit to be set */
85.LSRR_MODE:
86 R0 = [P2];
87 CC = BITTST(R0, 4);
88 if !CC JUMP .LSRR_MODE;
89
90 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
91 r0 = r0 << 9; /* Shift it over, */
92 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
93 r0 = r1 | r0;
94 r1 = PLL_BYPASS; /* Bypass the PLL? */
95 r1 = r1 << 8; /* Shift it over */
96 r0 = r1 | r0; /* add them all together */
97#ifdef ANOMALY_05000265
98 BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
99#endif
100
101 p0.h = hi(PLL_CTL);
102 p0.l = lo(PLL_CTL); /* Load the address */
103 cli r2; /* Disable interrupts */
104 ssync;
105 w[p0] = r0.l; /* Set the value */
106 idle; /* Wait for the PLL to stablize */
107 sti r2; /* Enable interrupts */
108
109.Lcheck_again:
110 p0.h = hi(PLL_STAT);
111 p0.l = lo(PLL_STAT);
112 R0 = W[P0](Z);
113 CC = BITTST(R0,5);
114 if ! CC jump .Lcheck_again;
115
116 /* Configure SCLK & CCLK Dividers */
117 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
118 p0.h = hi(PLL_DIV);
119 p0.l = lo(PLL_DIV);
120 w[p0] = r0.l;
121 ssync;
122
123 /* disable self refresh by clearing SRREQ */
124 P2.H = hi(EBIU_RSTCTL);
125 P2.L = lo(EBIU_RSTCTL);
126 R0 = [P2];
127 CC = BITTST(R0, 0);
128 if CC jump .Lskipddrrst;
129 BITSET (R0, 0);
130.Lskipddrrst:
131 BITCLR (R0, 3);
132 [P2] = R0;
133 SSYNC;
134
135 p0.l = lo(EBIU_DDRCTL0);
136 p0.h = hi(EBIU_DDRCTL0);
137 r0.l = lo(mem_DDRCTL0);
138 r0.h = hi(mem_DDRCTL0);
139 [p0] = r0;
140 ssync;
141
142 p0.l = lo(EBIU_DDRCTL1);
143 p0.h = hi(EBIU_DDRCTL1);
144 r0.l = lo(mem_DDRCTL1);
145 r0.h = hi(mem_DDRCTL1);
146 [p0] = r0;
147 ssync;
148
149 p0.l = lo(EBIU_DDRCTL2);
150 p0.h = hi(EBIU_DDRCTL2);
151 r0.l = lo(mem_DDRCTL2);
152 r0.h = hi(mem_DDRCTL2);
153 [p0] = r0;
154 ssync;
155
156 RTS;
157ENDPROC(_start_dma_code)
158#endif /* CONFIG_BFIN_KERNEL_CLOCK */
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_init.h b/arch/blackfin/mach-bf548/include/mach/mem_init.h
deleted file mode 100644
index ab0b863eee66..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/mem_init.h
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
32#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
33#define DDR_CLK_HZ(x) (1000*1000*1000/x)
34
35#if (CONFIG_MEM_MT46V32M16_6T)
36#define DDR_SIZE DEVSZ_512
37#define DDR_WIDTH DEVWD_16
38#define DDR_MAX_tCK 13
39
40#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
41#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
42#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
43#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
44#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
45
46#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
47#define DDR_tWTR DDR_TWTR(1)
48#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
49#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
50#endif
51
52#if (CONFIG_MEM_MT46V32M16_5B)
53#define DDR_SIZE DEVSZ_512
54#define DDR_WIDTH DEVWD_16
55#define DDR_MAX_tCK 13
56
57#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
58#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
59#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
60#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
61#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
62
63#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
64#define DDR_tWTR DDR_TWTR(2)
65#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
66#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
67#endif
68
69#if (CONFIG_MEM_GENERIC_BOARD)
70#define DDR_SIZE DEVSZ_512
71#define DDR_WIDTH DEVWD_16
72#define DDR_MAX_tCK 13
73
74#define DDR_tRCD DDR_TRCD(3)
75#define DDR_tWTR DDR_TWTR(2)
76#define DDR_tWR DDR_TWR(2)
77#define DDR_tMRD DDR_TMRD(2)
78#define DDR_tRP DDR_TRP(3)
79#define DDR_tRAS DDR_TRAS(7)
80#define DDR_tRC DDR_TRC(10)
81#define DDR_tRFC DDR_TRFC(12)
82#define DDR_tREFI DDR_TREFI(1288)
83#endif
84
85#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
86# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
87#elif(CONFIG_SCLK_HZ <= 133333333)
88# define DDR_CL CL_2
89#else
90# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
91#endif
92
93
94#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
95#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
96 | DDR_tMRD | DDR_tWR | DDR_tRCD)
97#define mem_DDRCTL2 DDR_CL
98
99
100#if defined CONFIG_CLKIN_HALF
101#define CLKIN_HALF 1
102#else
103#define CLKIN_HALF 0
104#endif
105
106#if defined CONFIG_PLL_BYPASS
107#define PLL_BYPASS 1
108#else
109#define PLL_BYPASS 0
110#endif
111
112/***************************************Currently Not Being Used *********************************/
113#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
114#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
115#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
116#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
117#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
118
119#if (flash_EBIU_AMBCTL_TT > 3)
120#define flash_EBIU_AMBCTL0_TT B0TT_4
121#endif
122#if (flash_EBIU_AMBCTL_TT == 3)
123#define flash_EBIU_AMBCTL0_TT B0TT_3
124#endif
125#if (flash_EBIU_AMBCTL_TT == 2)
126#define flash_EBIU_AMBCTL0_TT B0TT_2
127#endif
128#if (flash_EBIU_AMBCTL_TT < 2)
129#define flash_EBIU_AMBCTL0_TT B0TT_1
130#endif
131
132#if (flash_EBIU_AMBCTL_ST > 3)
133#define flash_EBIU_AMBCTL0_ST B0ST_4
134#endif
135#if (flash_EBIU_AMBCTL_ST == 3)
136#define flash_EBIU_AMBCTL0_ST B0ST_3
137#endif
138#if (flash_EBIU_AMBCTL_ST == 2)
139#define flash_EBIU_AMBCTL0_ST B0ST_2
140#endif
141#if (flash_EBIU_AMBCTL_ST < 2)
142#define flash_EBIU_AMBCTL0_ST B0ST_1
143#endif
144
145#if (flash_EBIU_AMBCTL_HT > 2)
146#define flash_EBIU_AMBCTL0_HT B0HT_3
147#endif
148#if (flash_EBIU_AMBCTL_HT == 2)
149#define flash_EBIU_AMBCTL0_HT B0HT_2
150#endif
151#if (flash_EBIU_AMBCTL_HT == 1)
152#define flash_EBIU_AMBCTL0_HT B0HT_1
153#endif
154#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
155#define flash_EBIU_AMBCTL0_HT B0HT_0
156#endif
157#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
158#define flash_EBIU_AMBCTL0_HT B0HT_1
159#endif
160
161#if (flash_EBIU_AMBCTL_WAT > 14)
162#define flash_EBIU_AMBCTL0_WAT B0WAT_15
163#endif
164#if (flash_EBIU_AMBCTL_WAT == 14)
165#define flash_EBIU_AMBCTL0_WAT B0WAT_14
166#endif
167#if (flash_EBIU_AMBCTL_WAT == 13)
168#define flash_EBIU_AMBCTL0_WAT B0WAT_13
169#endif
170#if (flash_EBIU_AMBCTL_WAT == 12)
171#define flash_EBIU_AMBCTL0_WAT B0WAT_12
172#endif
173#if (flash_EBIU_AMBCTL_WAT == 11)
174#define flash_EBIU_AMBCTL0_WAT B0WAT_11
175#endif
176#if (flash_EBIU_AMBCTL_WAT == 10)
177#define flash_EBIU_AMBCTL0_WAT B0WAT_10
178#endif
179#if (flash_EBIU_AMBCTL_WAT == 9)
180#define flash_EBIU_AMBCTL0_WAT B0WAT_9
181#endif
182#if (flash_EBIU_AMBCTL_WAT == 8)
183#define flash_EBIU_AMBCTL0_WAT B0WAT_8
184#endif
185#if (flash_EBIU_AMBCTL_WAT == 7)
186#define flash_EBIU_AMBCTL0_WAT B0WAT_7
187#endif
188#if (flash_EBIU_AMBCTL_WAT == 6)
189#define flash_EBIU_AMBCTL0_WAT B0WAT_6
190#endif
191#if (flash_EBIU_AMBCTL_WAT == 5)
192#define flash_EBIU_AMBCTL0_WAT B0WAT_5
193#endif
194#if (flash_EBIU_AMBCTL_WAT == 4)
195#define flash_EBIU_AMBCTL0_WAT B0WAT_4
196#endif
197#if (flash_EBIU_AMBCTL_WAT == 3)
198#define flash_EBIU_AMBCTL0_WAT B0WAT_3
199#endif
200#if (flash_EBIU_AMBCTL_WAT == 2)
201#define flash_EBIU_AMBCTL0_WAT B0WAT_2
202#endif
203#if (flash_EBIU_AMBCTL_WAT == 1)
204#define flash_EBIU_AMBCTL0_WAT B0WAT_1
205#endif
206
207#if (flash_EBIU_AMBCTL_RAT > 14)
208#define flash_EBIU_AMBCTL0_RAT B0RAT_15
209#endif
210#if (flash_EBIU_AMBCTL_RAT == 14)
211#define flash_EBIU_AMBCTL0_RAT B0RAT_14
212#endif
213#if (flash_EBIU_AMBCTL_RAT == 13)
214#define flash_EBIU_AMBCTL0_RAT B0RAT_13
215#endif
216#if (flash_EBIU_AMBCTL_RAT == 12)
217#define flash_EBIU_AMBCTL0_RAT B0RAT_12
218#endif
219#if (flash_EBIU_AMBCTL_RAT == 11)
220#define flash_EBIU_AMBCTL0_RAT B0RAT_11
221#endif
222#if (flash_EBIU_AMBCTL_RAT == 10)
223#define flash_EBIU_AMBCTL0_RAT B0RAT_10
224#endif
225#if (flash_EBIU_AMBCTL_RAT == 9)
226#define flash_EBIU_AMBCTL0_RAT B0RAT_9
227#endif
228#if (flash_EBIU_AMBCTL_RAT == 8)
229#define flash_EBIU_AMBCTL0_RAT B0RAT_8
230#endif
231#if (flash_EBIU_AMBCTL_RAT == 7)
232#define flash_EBIU_AMBCTL0_RAT B0RAT_7
233#endif
234#if (flash_EBIU_AMBCTL_RAT == 6)
235#define flash_EBIU_AMBCTL0_RAT B0RAT_6
236#endif
237#if (flash_EBIU_AMBCTL_RAT == 5)
238#define flash_EBIU_AMBCTL0_RAT B0RAT_5
239#endif
240#if (flash_EBIU_AMBCTL_RAT == 4)
241#define flash_EBIU_AMBCTL0_RAT B0RAT_4
242#endif
243#if (flash_EBIU_AMBCTL_RAT == 3)
244#define flash_EBIU_AMBCTL0_RAT B0RAT_3
245#endif
246#if (flash_EBIU_AMBCTL_RAT == 2)
247#define flash_EBIU_AMBCTL0_RAT B0RAT_2
248#endif
249#if (flash_EBIU_AMBCTL_RAT == 1)
250#define flash_EBIU_AMBCTL0_RAT B0RAT_1
251#endif
252
253#define flash_EBIU_AMBCTL0 \
254 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
255 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 07:08:19 -0500