diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2009-10-14 23:51:30 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-12-15 00:14:43 -0500 |
| commit | e153a97c2103706e3d2308e70c78b95b4f040321 (patch) | |
| tree | 80c5dae0e44fdf357699d2917bc294f9e85c159f /arch/blackfin/mach-bf548 | |
| parent | cd32cc73625641c068393978e7bb337d29c0cd29 (diff) | |
Blackfin: punt unused MXVR masks
There are no MXVR device drivers, and if someday there is, we can put
these in a dedicated header rather than polluting the global namespace.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF549.h | 944 |
1 files changed, 0 insertions, 944 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h index d84dbe9a8f27..5a04e6d4017e 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF549.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h | |||
| @@ -188,948 +188,4 @@ | |||
| 188 | #define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */ | 188 | #define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */ |
| 189 | #define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */ | 189 | #define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */ |
| 190 | 190 | ||
| 191 | /* Bit masks for MXVR_CONFIG */ | ||
| 192 | |||
| 193 | #define MXVREN 0x1 /* MXVR Enable */ | ||
| 194 | #define MMSM 0x2 /* MXVR Master/Slave Mode Select */ | ||
| 195 | #define ACTIVE 0x4 /* Active Mode */ | ||
| 196 | #define SDELAY 0x8 /* Synchronous Data Delay */ | ||
| 197 | #define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ | ||
| 198 | #define RWRRXEN 0x20 /* Remote Write Receive Enable */ | ||
| 199 | #define MTXEN 0x40 /* MXVR Transmit Data Enable */ | ||
| 200 | #define MTXONB 0x80 /* MXVR Phy Transmitter On */ | ||
| 201 | #define EPARITY 0x100 /* Even Parity Select */ | ||
| 202 | #define MSB 0x1e00 /* Master Synchronous Boundary */ | ||
| 203 | #define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ | ||
| 204 | #define WAKEUP 0x4000 /* Wake-Up */ | ||
| 205 | #define LMECH 0x8000 /* Lock Mechanism Select */ | ||
| 206 | |||
| 207 | /* Bit masks for MXVR_STATE_0 */ | ||
| 208 | |||
| 209 | #define NACT 0x1 /* Network Activity */ | ||
| 210 | #define SBLOCK 0x2 /* Super Block Lock */ | ||
| 211 | #define FMPLLST 0xc /* Frequency Multiply PLL SM State */ | ||
| 212 | #define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ | ||
| 213 | #define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ | ||
| 214 | #define APARB 0x200 /* Asynchronous Packet Arbitrating */ | ||
| 215 | #define APTX 0x400 /* Asynchronous Packet Transmitting */ | ||
| 216 | #define APRX 0x800 /* Receiving Asynchronous Packet */ | ||
| 217 | #define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ | ||
| 218 | #define CMARB 0x2000 /* Control Message Arbitrating */ | ||
| 219 | #define CMTX 0x4000 /* Control Message Transmitting */ | ||
| 220 | #define CMRX 0x8000 /* Receiving Control Message */ | ||
| 221 | #define MRXONB 0x10000 /* MRXONB Pin State */ | ||
| 222 | #define RGSIP 0x20000 /* Remote Get Source In Progress */ | ||
| 223 | #define DALIP 0x40000 /* Resource Deallocate In Progress */ | ||
| 224 | #define ALIP 0x80000 /* Resource Allocate In Progress */ | ||
| 225 | #define RRDIP 0x100000 /* Remote Read In Progress */ | ||
| 226 | #define RWRIP 0x200000 /* Remote Write In Progress */ | ||
| 227 | #define FLOCK 0x400000 /* Frame Lock */ | ||
| 228 | #define BLOCK 0x800000 /* Block Lock */ | ||
| 229 | #define RSB 0xf000000 /* Received Synchronous Boundary */ | ||
| 230 | #define DERRNUM 0xf0000000 /* DMA Error Channel Number */ | ||
| 231 | |||
| 232 | /* Bit masks for MXVR_STATE_1 */ | ||
| 233 | |||
| 234 | #define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ | ||
| 235 | #define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ | ||
| 236 | #define APCONT 0x100 /* Asynchronous Packet Continuation */ | ||
| 237 | #define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ | ||
| 238 | #define DMAACTIVE0 0x10000 /* DMA0 Active */ | ||
| 239 | #define DMAACTIVE1 0x20000 /* DMA1 Active */ | ||
| 240 | #define DMAACTIVE2 0x40000 /* DMA2 Active */ | ||
| 241 | #define DMAACTIVE3 0x80000 /* DMA3 Active */ | ||
| 242 | #define DMAACTIVE4 0x100000 /* DMA4 Active */ | ||
| 243 | #define DMAACTIVE5 0x200000 /* DMA5 Active */ | ||
| 244 | #define DMAACTIVE6 0x400000 /* DMA6 Active */ | ||
| 245 | #define DMAACTIVE7 0x800000 /* DMA7 Active */ | ||
| 246 | #define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ | ||
| 247 | #define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ | ||
| 248 | #define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ | ||
| 249 | #define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ | ||
| 250 | #define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ | ||
| 251 | #define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ | ||
| 252 | #define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ | ||
| 253 | #define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ | ||
| 254 | |||
| 255 | /* Bit masks for MXVR_INT_STAT_0 */ | ||
| 256 | |||
| 257 | #define NI2A 0x1 /* Network Inactive to Active */ | ||
| 258 | #define NA2I 0x2 /* Network Active to Inactive */ | ||
| 259 | #define SBU2L 0x4 /* Super Block Unlock to Lock */ | ||
| 260 | #define SBL2U 0x8 /* Super Block Lock to Unlock */ | ||
| 261 | #define PRU 0x10 /* Position Register Updated */ | ||
| 262 | #define MPRU 0x20 /* Maximum Position Register Updated */ | ||
| 263 | #define DRU 0x40 /* Delay Register Updated */ | ||
| 264 | #define MDRU 0x80 /* Maximum Delay Register Updated */ | ||
| 265 | #define SBU 0x100 /* Synchronous Boundary Updated */ | ||
| 266 | #define ATU 0x200 /* Allocation Table Updated */ | ||
| 267 | #define FCZ0 0x400 /* Frame Counter 0 Zero */ | ||
| 268 | #define FCZ1 0x800 /* Frame Counter 1 Zero */ | ||
| 269 | #define PERR 0x1000 /* Parity Error */ | ||
| 270 | #define MH2L 0x2000 /* MRXONB High to Low */ | ||
| 271 | #define ML2H 0x4000 /* MRXONB Low to High */ | ||
| 272 | #define WUP 0x8000 /* Wake-Up Preamble Received */ | ||
| 273 | #define FU2L 0x10000 /* Frame Unlock to Lock */ | ||
| 274 | #define FL2U 0x20000 /* Frame Lock to Unlock */ | ||
| 275 | #define BU2L 0x40000 /* Block Unlock to Lock */ | ||
| 276 | #define BL2U 0x80000 /* Block Lock to Unlock */ | ||
| 277 | #define OBERR 0x100000 /* DMA Out of Bounds Error */ | ||
| 278 | #define PFL 0x200000 /* PLL Frequency Locked */ | ||
| 279 | #define SCZ 0x400000 /* System Clock Counter Zero */ | ||
| 280 | #define FERR 0x800000 /* FIFO Error */ | ||
| 281 | #define CMR 0x1000000 /* Control Message Received */ | ||
| 282 | #define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ | ||
| 283 | #define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ | ||
| 284 | #define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ | ||
| 285 | #define RWRC 0x10000000 /* Remote Write Control Message Completed */ | ||
| 286 | #define BCZ 0x20000000 /* Block Counter Zero */ | ||
| 287 | #define BMERR 0x40000000 /* Biphase Mark Coding Error */ | ||
| 288 | #define DERR 0x80000000 /* DMA Error */ | ||
| 289 | |||
| 290 | /* Bit masks for MXVR_INT_STAT_1 */ | ||
| 291 | |||
| 292 | #define HDONE0 0x1 /* DMA0 Half Done */ | ||
| 293 | #define DONE0 0x2 /* DMA0 Done */ | ||
| 294 | #define APR 0x4 /* Asynchronous Packet Received */ | ||
| 295 | #define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ | ||
| 296 | #define HDONE1 0x10 /* DMA1 Half Done */ | ||
| 297 | #define DONE1 0x20 /* DMA1 Done */ | ||
| 298 | #define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ | ||
| 299 | #define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ | ||
| 300 | #define HDONE2 0x100 /* DMA2 Half Done */ | ||
| 301 | #define DONE2 0x200 /* DMA2 Done */ | ||
| 302 | #define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ | ||
| 303 | #define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ | ||
| 304 | #define HDONE3 0x1000 /* DMA3 Half Done */ | ||
| 305 | #define DONE3 0x2000 /* DMA3 Done */ | ||
| 306 | #define HDONE4 0x10000 /* DMA4 Half Done */ | ||
| 307 | #define DONE4 0x20000 /* DMA4 Done */ | ||
| 308 | #define HDONE5 0x100000 /* DMA5 Half Done */ | ||
| 309 | #define DONE5 0x200000 /* DMA5 Done */ | ||
| 310 | #define HDONE6 0x1000000 /* DMA6 Half Done */ | ||
| 311 | #define DONE6 0x2000000 /* DMA6 Done */ | ||
| 312 | #define HDONE7 0x10000000 /* DMA7 Half Done */ | ||
| 313 | #define DONE7 0x20000000 /* DMA7 Done */ | ||
| 314 | |||
| 315 | /* Bit masks for MXVR_INT_EN_0 */ | ||
| 316 | |||
| 317 | #define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ | ||
| 318 | #define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ | ||
| 319 | #define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ | ||
| 320 | #define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ | ||
| 321 | #define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ | ||
| 322 | #define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ | ||
| 323 | #define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ | ||
| 324 | #define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ | ||
| 325 | #define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ | ||
| 326 | #define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ | ||
| 327 | #define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ | ||
| 328 | #define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ | ||
| 329 | #define PERREN 0x1000 /* Parity Error Interrupt Enable */ | ||
| 330 | #define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ | ||
| 331 | #define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ | ||
| 332 | #define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ | ||
| 333 | #define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ | ||
| 334 | #define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ | ||
| 335 | #define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ | ||
| 336 | #define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ | ||
| 337 | #define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ | ||
| 338 | #define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ | ||
| 339 | #define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ | ||
| 340 | #define FERREN 0x800000 /* FIFO Error Interrupt Enable */ | ||
| 341 | #define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ | ||
| 342 | #define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ | ||
| 343 | #define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ | ||
| 344 | #define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ | ||
| 345 | #define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ | ||
| 346 | #define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ | ||
| 347 | #define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ | ||
| 348 | #define DERREN 0x80000000 /* DMA Error Interrupt Enable */ | ||
| 349 | |||
| 350 | /* Bit masks for MXVR_INT_EN_1 */ | ||
| 351 | |||
| 352 | #define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ | ||
| 353 | #define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ | ||
| 354 | #define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ | ||
| 355 | #define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ | ||
| 356 | #define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ | ||
| 357 | #define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ | ||
| 358 | #define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ | ||
| 359 | #define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ | ||
| 360 | #define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ | ||
| 361 | #define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ | ||
| 362 | #define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ | ||
| 363 | #define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ | ||
| 364 | #define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ | ||
| 365 | #define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ | ||
| 366 | #define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ | ||
| 367 | #define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ | ||
| 368 | #define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ | ||
| 369 | #define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ | ||
| 370 | #define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ | ||
| 371 | #define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ | ||
| 372 | #define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ | ||
| 373 | #define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ | ||
| 374 | |||
| 375 | /* Bit masks for MXVR_POSITION */ | ||
| 376 | |||
| 377 | #define POSITION 0x3f /* Node Position */ | ||
| 378 | #define PVALID 0x8000 /* Node Position Valid */ | ||
| 379 | |||
| 380 | /* Bit masks for MXVR_MAX_POSITION */ | ||
| 381 | |||
| 382 | #define MPOSITION 0x3f /* Maximum Node Position */ | ||
| 383 | #define MPVALID 0x8000 /* Maximum Node Position Valid */ | ||
| 384 | |||
| 385 | /* Bit masks for MXVR_DELAY */ | ||
| 386 | |||
| 387 | #define DELAY 0x3f /* Node Frame Delay */ | ||
| 388 | #define DVALID 0x8000 /* Node Frame Delay Valid */ | ||
| 389 | |||
| 390 | /* Bit masks for MXVR_MAX_DELAY */ | ||
| 391 | |||
| 392 | #define MDELAY 0x3f /* Maximum Node Frame Delay */ | ||
| 393 | #define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ | ||
| 394 | |||
| 395 | /* Bit masks for MXVR_LADDR */ | ||
| 396 | |||
| 397 | #define LADDR 0xffff /* Logical Address */ | ||
| 398 | #define LVALID 0x80000000 /* Logical Address Valid */ | ||
| 399 | |||
| 400 | /* Bit masks for MXVR_GADDR */ | ||
| 401 | |||
| 402 | #define GADDRL 0xff /* Group Address Lower Byte */ | ||
| 403 | #define GVALID 0x8000 /* Group Address Valid */ | ||
| 404 | |||
| 405 | /* Bit masks for MXVR_AADDR */ | ||
| 406 | |||
| 407 | #define AADDR 0xffff /* Alternate Address */ | ||
| 408 | #define AVALID 0x80000000 /* Alternate Address Valid */ | ||
| 409 | |||
| 410 | /* Bit masks for MXVR_ALLOC_0 */ | ||
| 411 | |||
| 412 | #define CL0 0x7f /* Channel 0 Connection Label */ | ||
| 413 | #define CIU0 0x80 /* Channel 0 In Use */ | ||
| 414 | #define CL1 0x7f00 /* Channel 0 Connection Label */ | ||
| 415 | #define CIU1 0x8000 /* Channel 0 In Use */ | ||
| 416 | #define CL2 0x7f0000 /* Channel 0 Connection Label */ | ||
| 417 | #define CIU2 0x800000 /* Channel 0 In Use */ | ||
| 418 | #define CL3 0x7f000000 /* Channel 0 Connection Label */ | ||
| 419 | #define CIU3 0x80000000 /* Channel 0 In Use */ | ||
| 420 | |||
| 421 | /* Bit masks for MXVR_ALLOC_1 */ | ||
| 422 | |||
| 423 | #define CL4 0x7f /* Channel 4 Connection Label */ | ||
| 424 | #define CIU4 0x80 /* Channel 4 In Use */ | ||
| 425 | #define CL5 0x7f00 /* Channel 5 Connection Label */ | ||
| 426 | #define CIU5 0x8000 /* Channel 5 In Use */ | ||
| 427 | #define CL6 0x7f0000 /* Channel 6 Connection Label */ | ||
| 428 | #define CIU6 0x800000 /* Channel 6 In Use */ | ||
| 429 | #define CL7 0x7f000000 /* Channel 7 Connection Label */ | ||
| 430 | #define CIU7 0x80000000 /* Channel 7 In Use */ | ||
| 431 | |||
| 432 | /* Bit masks for MXVR_ALLOC_2 */ | ||
| 433 | |||
| 434 | #define CL8 0x7f /* Channel 8 Connection Label */ | ||
| 435 | #define CIU8 0x80 /* Channel 8 In Use */ | ||
| 436 | #define CL9 0x7f00 /* Channel 9 Connection Label */ | ||
| 437 | #define CIU9 0x8000 /* Channel 9 In Use */ | ||
| 438 | #define CL10 0x7f0000 /* Channel 10 Connection Label */ | ||
| 439 | #define CIU10 0x800000 /* Channel 10 In Use */ | ||
| 440 | #define CL11 0x7f000000 /* Channel 11 Connection Label */ | ||
| 441 | #define CIU11 0x80000000 /* Channel 11 In Use */ | ||
| 442 | |||
| 443 | /* Bit masks for MXVR_ALLOC_3 */ | ||
| 444 | |||
| 445 | #define CL12 0x7f /* Channel 12 Connection Label */ | ||
| 446 | #define CIU12 0x80 /* Channel 12 In Use */ | ||
| 447 | #define CL13 0x7f00 /* Channel 13 Connection Label */ | ||
| 448 | #define CIU13 0x8000 /* Channel 13 In Use */ | ||
| 449 | #define CL14 0x7f0000 /* Channel 14 Connection Label */ | ||
| 450 | #define CIU14 0x800000 /* Channel 14 In Use */ | ||
| 451 | #define CL15 0x7f000000 /* Channel 15 Connection Label */ | ||
| 452 | #define CIU15 0x80000000 /* Channel 15 In Use */ | ||
| 453 | |||
| 454 | /* Bit masks for MXVR_ALLOC_4 */ | ||
| 455 | |||
| 456 | #define CL16 0x7f /* Channel 16 Connection Label */ | ||
| 457 | #define CIU16 0x80 /* Channel 16 In Use */ | ||
| 458 | #define CL17 0x7f00 /* Channel 17 Connection Label */ | ||
| 459 | #define CIU17 0x8000 /* Channel 17 In Use */ | ||
| 460 | #define CL18 0x7f0000 /* Channel 18 Connection Label */ | ||
| 461 | #define CIU18 0x800000 /* Channel 18 In Use */ | ||
| 462 | #define CL19 0x7f000000 /* Channel 19 Connection Label */ | ||
| 463 | #define CIU19 0x80000000 /* Channel 19 In Use */ | ||
| 464 | |||
| 465 | /* Bit masks for MXVR_ALLOC_5 */ | ||
| 466 | |||
| 467 | #define CL20 0x7f /* Channel 20 Connection Label */ | ||
| 468 | #define CIU20 0x80 /* Channel 20 In Use */ | ||
| 469 | #define CL21 0x7f00 /* Channel 21 Connection Label */ | ||
| 470 | #define CIU21 0x8000 /* Channel 21 In Use */ | ||
| 471 | #define CL22 0x7f0000 /* Channel 22 Connection Label */ | ||
| 472 | #define CIU22 0x800000 /* Channel 22 In Use */ | ||
| 473 | #define CL23 0x7f000000 /* Channel 23 Connection Label */ | ||
| 474 | #define CIU23 0x80000000 /* Channel 23 In Use */ | ||
| 475 | |||
| 476 | /* Bit masks for MXVR_ALLOC_6 */ | ||
| 477 | |||
| 478 | #define CL24 0x7f /* Channel 24 Connection Label */ | ||
| 479 | #define CIU24 0x80 /* Channel 24 In Use */ | ||
| 480 | #define CL25 0x7f00 /* Channel 25 Connection Label */ | ||
| 481 | #define CIU25 0x8000 /* Channel 25 In Use */ | ||
| 482 | #define CL26 0x7f0000 /* Channel 26 Connection Label */ | ||
| 483 | #define CIU26 0x800000 /* Channel 26 In Use */ | ||
| 484 | #define CL27 0x7f000000 /* Channel 27 Connection Label */ | ||
| 485 | #define CIU27 0x80000000 /* Channel 27 In Use */ | ||
| 486 | |||
| 487 | /* Bit masks for MXVR_ALLOC_7 */ | ||
| 488 | |||
| 489 | #define CL28 0x7f /* Channel 28 Connection Label */ | ||
| 490 | #define CIU28 0x80 /* Channel 28 In Use */ | ||
| 491 | #define CL29 0x7f00 /* Channel 29 Connection Label */ | ||
| 492 | #define CIU29 0x8000 /* Channel 29 In Use */ | ||
| 493 | #define CL30 0x7f0000 /* Channel 30 Connection Label */ | ||
| 494 | #define CIU30 0x800000 /* Channel 30 In Use */ | ||
| 495 | #define CL31 0x7f000000 /* Channel 31 Connection Label */ | ||
| 496 | #define CIU31 0x80000000 /* Channel 31 In Use */ | ||
| 497 | |||
| 498 | /* Bit masks for MXVR_ALLOC_8 */ | ||
| 499 | |||
| 500 | #define CL32 0x7f /* Channel 32 Connection Label */ | ||
| 501 | #define CIU32 0x80 /* Channel 32 In Use */ | ||
| 502 | #define CL33 0x7f00 /* Channel 33 Connection Label */ | ||
| 503 | #define CIU33 0x8000 /* Channel 33 In Use */ | ||
| 504 | #define CL34 0x7f0000 /* Channel 34 Connection Label */ | ||
| 505 | #define CIU34 0x800000 /* Channel 34 In Use */ | ||
| 506 | #define CL35 0x7f000000 /* Channel 35 Connection Label */ | ||
| 507 | #define CIU35 0x80000000 /* Channel 35 In Use */ | ||
| 508 | |||
| 509 | /* Bit masks for MXVR_ALLOC_9 */ | ||
| 510 | |||
| 511 | #define CL36 0x7f /* Channel 36 Connection Label */ | ||
| 512 | #define CIU36 0x80 /* Channel 36 In Use */ | ||
| 513 | #define CL37 0x7f00 /* Channel 37 Connection Label */ | ||
| 514 | #define CIU37 0x8000 /* Channel 37 In Use */ | ||
| 515 | #define CL38 0x7f0000 /* Channel 38 Connection Label */ | ||
| 516 | #define CIU38 0x800000 /* Channel 38 In Use */ | ||
| 517 | #define CL39 0x7f000000 /* Channel 39 Connection Label */ | ||
| 518 | #define CIU39 0x80000000 /* Channel 39 In Use */ | ||
| 519 | |||
| 520 | /* Bit masks for MXVR_ALLOC_10 */ | ||
| 521 | |||
| 522 | #define CL40 0x7f /* Channel 40 Connection Label */ | ||
| 523 | #define CIU40 0x80 /* Channel 40 In Use */ | ||
| 524 | #define CL41 0x7f00 /* Channel 41 Connection Label */ | ||
| 525 | #define CIU41 0x8000 /* Channel 41 In Use */ | ||
| 526 | #define CL42 0x7f0000 /* Channel 42 Connection Label */ | ||
| 527 | #define CIU42 0x800000 /* Channel 42 In Use */ | ||
| 528 | #define CL43 0x7f000000 /* Channel 43 Connection Label */ | ||
| 529 | #define CIU43 0x80000000 /* Channel 43 In Use */ | ||
| 530 | |||
| 531 | /* Bit masks for MXVR_ALLOC_11 */ | ||
| 532 | |||
| 533 | #define CL44 0x7f /* Channel 44 Connection Label */ | ||
| 534 | #define CIU44 0x80 /* Channel 44 In Use */ | ||
| 535 | #define CL45 0x7f00 /* Channel 45 Connection Label */ | ||
| 536 | #define CIU45 0x8000 /* Channel 45 In Use */ | ||
| 537 | #define CL46 0x7f0000 /* Channel 46 Connection Label */ | ||
| 538 | #define CIU46 0x800000 /* Channel 46 In Use */ | ||
| 539 | #define CL47 0x7f000000 /* Channel 47 Connection Label */ | ||
| 540 | #define CIU47 0x80000000 /* Channel 47 In Use */ | ||
| 541 | |||
| 542 | /* Bit masks for MXVR_ALLOC_12 */ | ||
| 543 | |||
| 544 | #define CL48 0x7f /* Channel 48 Connection Label */ | ||
| 545 | #define CIU48 0x80 /* Channel 48 In Use */ | ||
| 546 | #define CL49 0x7f00 /* Channel 49 Connection Label */ | ||
| 547 | #define CIU49 0x8000 /* Channel 49 In Use */ | ||
| 548 | #define CL50 0x7f0000 /* Channel 50 Connection Label */ | ||
| 549 | #define CIU50 0x800000 /* Channel 50 In Use */ | ||
| 550 | #define CL51 0x7f000000 /* Channel 51 Connection Label */ | ||
| 551 | #define CIU51 0x80000000 /* Channel 51 In Use */ | ||
| 552 | |||
| 553 | /* Bit masks for MXVR_ALLOC_13 */ | ||
| 554 | |||
| 555 | #define CL52 0x7f /* Channel 52 Connection Label */ | ||
| 556 | #define CIU52 0x80 /* Channel 52 In Use */ | ||
| 557 | #define CL53 0x7f00 /* Channel 53 Connection Label */ | ||
| 558 | #define CIU53 0x8000 /* Channel 53 In Use */ | ||
| 559 | #define CL54 0x7f0000 /* Channel 54 Connection Label */ | ||
| 560 | #define CIU54 0x800000 /* Channel 54 In Use */ | ||
| 561 | #define CL55 0x7f000000 /* Channel 55 Connection Label */ | ||
| 562 | #define CIU55 0x80000000 /* Channel 55 In Use */ | ||
| 563 | |||
| 564 | /* Bit masks for MXVR_ALLOC_14 */ | ||
| 565 | |||
| 566 | #define CL56 0x7f /* Channel 56 Connection Label */ | ||
| 567 | #define CIU56 0x80 /* Channel 56 In Use */ | ||
| 568 | #define CL57 0x7f00 /* Channel 57 Connection Label */ | ||
| 569 | #define CIU57 0x8000 /* Channel 57 In Use */ | ||
| 570 | #define CL58 0x7f0000 /* Channel 58 Connection Label */ | ||
| 571 | #define CIU58 0x800000 /* Channel 58 In Use */ | ||
| 572 | #define CL59 0x7f000000 /* Channel 59 Connection Label */ | ||
| 573 | #define CIU59 0x80000000 /* Channel 59 In Use */ | ||
| 574 | |||
| 575 | /* MXVR_SYNC_LCHAN_0 Masks */ | ||
| 576 | |||
| 577 | #define LCHANPC0 0x0000000Flu | ||
| 578 | #define LCHANPC1 0x000000F0lu | ||
| 579 | #define LCHANPC2 0x00000F00lu | ||
| 580 | #define LCHANPC3 0x0000F000lu | ||
| 581 | #define LCHANPC4 0x000F0000lu | ||
| 582 | #define LCHANPC5 0x00F00000lu | ||
| 583 | #define LCHANPC6 0x0F000000lu | ||
| 584 | #define LCHANPC7 0xF0000000lu | ||
| 585 | |||
| 586 | |||
| 587 | /* MXVR_SYNC_LCHAN_1 Masks */ | ||
| 588 | |||
| 589 | #define LCHANPC8 0x0000000Flu | ||
| 590 | #define LCHANPC9 0x000000F0lu | ||
| 591 | #define LCHANPC10 0x00000F00lu | ||
| 592 | #define LCHANPC11 0x0000F000lu | ||
| 593 | #define LCHANPC12 0x000F0000lu | ||
| 594 | #define LCHANPC13 0x00F00000lu | ||
| 595 | #define LCHANPC14 0x0F000000lu | ||
| 596 | #define LCHANPC15 0xF0000000lu | ||
| 597 | |||
| 598 | |||
| 599 | /* MXVR_SYNC_LCHAN_2 Masks */ | ||
| 600 | |||
| 601 | #define LCHANPC16 0x0000000Flu | ||
| 602 | #define LCHANPC17 0x000000F0lu | ||
| 603 | #define LCHANPC18 0x00000F00lu | ||
| 604 | #define LCHANPC19 0x0000F000lu | ||
| 605 | #define LCHANPC20 0x000F0000lu | ||
| 606 | #define LCHANPC21 0x00F00000lu | ||
| 607 | #define LCHANPC22 0x0F000000lu | ||
| 608 | #define LCHANPC23 0xF0000000lu | ||
| 609 | |||
| 610 | |||
| 611 | /* MXVR_SYNC_LCHAN_3 Masks */ | ||
| 612 | |||
| 613 | #define LCHANPC24 0x0000000Flu | ||
| 614 | #define LCHANPC25 0x000000F0lu | ||
| 615 | #define LCHANPC26 0x00000F00lu | ||
| 616 | #define LCHANPC27 0x0000F000lu | ||
| 617 | #define LCHANPC28 0x000F0000lu | ||
| 618 | #define LCHANPC29 0x00F00000lu | ||
| 619 | #define LCHANPC30 0x0F000000lu | ||
| 620 | #define LCHANPC31 0xF0000000lu | ||
| 621 | |||
| 622 | |||
| 623 | /* MXVR_SYNC_LCHAN_4 Masks */ | ||
| 624 | |||
| 625 | #define LCHANPC32 0x0000000Flu | ||
| 626 | #define LCHANPC33 0x000000F0lu | ||
| 627 | #define LCHANPC34 0x00000F00lu | ||
| 628 | #define LCHANPC35 0x0000F000lu | ||
| 629 | #define LCHANPC36 0x000F0000lu | ||
| 630 | #define LCHANPC37 0x00F00000lu | ||
| 631 | #define LCHANPC38 0x0F000000lu | ||
| 632 | #define LCHANPC39 0xF0000000lu | ||
| 633 | |||
| 634 | |||
| 635 | /* MXVR_SYNC_LCHAN_5 Masks */ | ||
| 636 | |||
| 637 | #define LCHANPC40 0x0000000Flu | ||
| 638 | #define LCHANPC41 0x000000F0lu | ||
| 639 | #define LCHANPC42 0x00000F00lu | ||
| 640 | #define LCHANPC43 0x0000F000lu | ||
| 641 | #define LCHANPC44 0x000F0000lu | ||
| 642 | #define LCHANPC45 0x00F00000lu | ||
| 643 | #define LCHANPC46 0x0F000000lu | ||
| 644 | #define LCHANPC47 0xF0000000lu | ||
| 645 | |||
| 646 | |||
| 647 | /* MXVR_SYNC_LCHAN_6 Masks */ | ||
| 648 | |||
| 649 | #define LCHANPC48 0x0000000Flu | ||
| 650 | #define LCHANPC49 0x000000F0lu | ||
| 651 | #define LCHANPC50 0x00000F00lu | ||
| 652 | #define LCHANPC51 0x0000F000lu | ||
| 653 | #define LCHANPC52 0x000F0000lu | ||
| 654 | #define LCHANPC53 0x00F00000lu | ||
| 655 | #define LCHANPC54 0x0F000000lu | ||
| 656 | #define LCHANPC55 0xF0000000lu | ||
| 657 | |||
| 658 | |||
| 659 | /* MXVR_SYNC_LCHAN_7 Masks */ | ||
| 660 | |||
| 661 | #define LCHANPC56 0x0000000Flu | ||
| 662 | #define LCHANPC57 0x000000F0lu | ||
| 663 | #define LCHANPC58 0x00000F00lu | ||
| 664 | #define LCHANPC59 0x0000F000lu | ||
| 665 | |||
| 666 | /* Bit masks for MXVR_DMAx_CONFIG */ | ||
| 667 | |||
| 668 | #define MDMAEN 0x1 /* DMA Channel Enable */ | ||
| 669 | #define DMADD 0x2 /* DMA Channel Direction */ | ||
| 670 | #define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ | ||
| 671 | #define LCHAN 0x3c0 /* DMA Channel Logical Channel */ | ||
| 672 | #define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ | ||
| 673 | #define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ | ||
| 674 | #define MFLOW 0x7000 /* DMA Channel Operation Flow */ | ||
| 675 | #define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ | ||
| 676 | #define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ | ||
| 677 | #define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ | ||
| 678 | #define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ | ||
| 679 | |||
| 680 | /* Bit masks for MXVR_AP_CTL */ | ||
| 681 | |||
| 682 | #define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ | ||
| 683 | #define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ | ||
| 684 | #define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ | ||
| 685 | #define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ | ||
| 686 | #define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ | ||
| 687 | |||
| 688 | /* Bit masks for MXVR_APRB_START_ADDR */ | ||
| 689 | |||
| 690 | #define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ | ||
| 691 | |||
| 692 | /* Bit masks for MXVR_APRB_CURR_ADDR */ | ||
| 693 | |||
| 694 | #define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ | ||
| 695 | |||
| 696 | /* Bit masks for MXVR_APTB_START_ADDR */ | ||
| 697 | |||
| 698 | #define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ | ||
| 699 | |||
| 700 | /* Bit masks for MXVR_APTB_CURR_ADDR */ | ||
| 701 | |||
| 702 | #define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ | ||
| 703 | |||
| 704 | /* Bit masks for MXVR_CM_CTL */ | ||
| 705 | |||
| 706 | #define STARTCM 0x1 /* Start Control Message Transmission */ | ||
| 707 | #define CANCELCM 0x2 /* Cancel Control Message Transmission */ | ||
| 708 | #define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */ | ||
| 709 | #define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */ | ||
| 710 | #define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */ | ||
| 711 | #define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */ | ||
| 712 | #define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */ | ||
| 713 | #define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */ | ||
| 714 | #define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */ | ||
| 715 | #define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */ | ||
| 716 | #define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */ | ||
| 717 | #define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */ | ||
| 718 | #define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */ | ||
| 719 | #define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */ | ||
| 720 | #define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */ | ||
| 721 | #define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */ | ||
| 722 | #define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */ | ||
| 723 | #define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */ | ||
| 724 | |||
| 725 | /* Bit masks for MXVR_CMRB_START_ADDR */ | ||
| 726 | |||
| 727 | #define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */ | ||
| 728 | |||
| 729 | /* Bit masks for MXVR_CMRB_CURR_ADDR */ | ||
| 730 | |||
| 731 | #define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */ | ||
| 732 | |||
| 733 | /* Bit masks for MXVR_CMTB_START_ADDR */ | ||
| 734 | |||
| 735 | #define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */ | ||
| 736 | |||
| 737 | /* Bit masks for MXVR_CMTB_CURR_ADDR */ | ||
| 738 | |||
| 739 | #define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */ | ||
| 740 | |||
| 741 | /* Bit masks for MXVR_RRDB_START_ADDR */ | ||
| 742 | |||
| 743 | #define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */ | ||
| 744 | |||
| 745 | /* Bit masks for MXVR_RRDB_CURR_ADDR */ | ||
| 746 | |||
| 747 | #define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */ | ||
| 748 | |||
| 749 | /* Bit masks for MXVR_PAT_DATAx */ | ||
| 750 | |||
| 751 | #define MATCH_DATA_0 0xff /* Pattern Match Data Byte 0 */ | ||
| 752 | #define MATCH_DATA_1 0xff00 /* Pattern Match Data Byte 1 */ | ||
| 753 | #define MATCH_DATA_2 0xff0000 /* Pattern Match Data Byte 2 */ | ||
| 754 | #define MATCH_DATA_3 0xff000000 /* Pattern Match Data Byte 3 */ | ||
| 755 | |||
| 756 | /* Bit masks for MXVR_PAT_EN_0 */ | ||
| 757 | |||
| 758 | #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ | ||
| 759 | #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ | ||
| 760 | #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ | ||
| 761 | #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ | ||
| 762 | #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ | ||
| 763 | #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ | ||
| 764 | #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ | ||
| 765 | #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ | ||
| 766 | #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ | ||
| 767 | #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ | ||
| 768 | #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ | ||
| 769 | #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ | ||
| 770 | #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ | ||
| 771 | #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ | ||
| 772 | #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ | ||
| 773 | #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ | ||
| 774 | #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ | ||
| 775 | #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ | ||
| 776 | #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ | ||
| 777 | #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ | ||
| 778 | #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ | ||
| 779 | #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ | ||
| 780 | #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ | ||
| 781 | #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ | ||
| 782 | #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ | ||
| 783 | #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ | ||
| 784 | #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ | ||
| 785 | #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ | ||
| 786 | #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ | ||
| 787 | #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ | ||
| 788 | #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ | ||
| 789 | #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ | ||
| 790 | |||
| 791 | /* Bit masks for MXVR_PAT_EN_1 */ | ||
| 792 | |||
| 793 | #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ | ||
| 794 | #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ | ||
| 795 | #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ | ||
| 796 | #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ | ||
| 797 | #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ | ||
| 798 | #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ | ||
| 799 | #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ | ||
| 800 | #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ | ||
| 801 | #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ | ||
| 802 | #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ | ||
| 803 | #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ | ||
| 804 | #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ | ||
| 805 | #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ | ||
| 806 | #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ | ||
| 807 | #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ | ||
| 808 | #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ | ||
| 809 | #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ | ||
| 810 | #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ | ||
| 811 | #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ | ||
| 812 | #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ | ||
| 813 | #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ | ||
| 814 | #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ | ||
| 815 | #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ | ||
| 816 | #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ | ||
| 817 | #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ | ||
| 818 | #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ | ||
| 819 | #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ | ||
| 820 | #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ | ||
| 821 | #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ | ||
| 822 | #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ | ||
| 823 | #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ | ||
| 824 | #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ | ||
| 825 | |||
| 826 | /* Bit masks for MXVR_FRAME_CNT_0 */ | ||
| 827 | |||
| 828 | #define FCNT 0xffff /* Frame Count */ | ||
| 829 | |||
| 830 | /* Bit masks for MXVR_FRAME_CNT_1 */ | ||
| 831 | |||
| 832 | #define FCNT 0xffff /* Frame Count */ | ||
| 833 | |||
| 834 | /* Bit masks for MXVR_ROUTING_0 */ | ||
| 835 | |||
| 836 | #define TX_CH0 0x3f /* Transmit Channel 0 */ | ||
| 837 | #define MUTE_CH0 0x80 /* Mute Channel 0 */ | ||
| 838 | #define TX_CH1 0x3f00 /* Transmit Channel 0 */ | ||
| 839 | #define MUTE_CH1 0x8000 /* Mute Channel 0 */ | ||
| 840 | #define TX_CH2 0x3f0000 /* Transmit Channel 0 */ | ||
| 841 | #define MUTE_CH2 0x800000 /* Mute Channel 0 */ | ||
| 842 | #define TX_CH3 0x3f000000 /* Transmit Channel 0 */ | ||
| 843 | #define MUTE_CH3 0x80000000 /* Mute Channel 0 */ | ||
| 844 | |||
| 845 | /* Bit masks for MXVR_ROUTING_1 */ | ||
| 846 | |||
| 847 | #define TX_CH4 0x3f /* Transmit Channel 4 */ | ||
| 848 | #define MUTE_CH4 0x80 /* Mute Channel 4 */ | ||
| 849 | #define TX_CH5 0x3f00 /* Transmit Channel 5 */ | ||
| 850 | #define MUTE_CH5 0x8000 /* Mute Channel 5 */ | ||
| 851 | #define TX_CH6 0x3f0000 /* Transmit Channel 6 */ | ||
| 852 | #define MUTE_CH6 0x800000 /* Mute Channel 6 */ | ||
| 853 | #define TX_CH7 0x3f000000 /* Transmit Channel 7 */ | ||
| 854 | #define MUTE_CH7 0x80000000 /* Mute Channel 7 */ | ||
| 855 | |||
| 856 | /* Bit masks for MXVR_ROUTING_2 */ | ||
| 857 | |||
| 858 | #define TX_CH8 0x3f /* Transmit Channel 8 */ | ||
| 859 | #define MUTE_CH8 0x80 /* Mute Channel 8 */ | ||
| 860 | #define TX_CH9 0x3f00 /* Transmit Channel 9 */ | ||
| 861 | #define MUTE_CH9 0x8000 /* Mute Channel 9 */ | ||
| 862 | #define TX_CH10 0x3f0000 /* Transmit Channel 10 */ | ||
| 863 | #define MUTE_CH10 0x800000 /* Mute Channel 10 */ | ||
| 864 | #define TX_CH11 0x3f000000 /* Transmit Channel 11 */ | ||
| 865 | #define MUTE_CH11 0x80000000 /* Mute Channel 11 */ | ||
| 866 | |||
| 867 | /* Bit masks for MXVR_ROUTING_3 */ | ||
| 868 | |||
| 869 | #define TX_CH12 0x3f /* Transmit Channel 12 */ | ||
| 870 | #define MUTE_CH12 0x80 /* Mute Channel 12 */ | ||
| 871 | #define TX_CH13 0x3f00 /* Transmit Channel 13 */ | ||
| 872 | #define MUTE_CH13 0x8000 /* Mute Channel 13 */ | ||
| 873 | #define TX_CH14 0x3f0000 /* Transmit Channel 14 */ | ||
| 874 | #define MUTE_CH14 0x800000 /* Mute Channel 14 */ | ||
| 875 | #define TX_CH15 0x3f000000 /* Transmit Channel 15 */ | ||
| 876 | #define MUTE_CH15 0x80000000 /* Mute Channel 15 */ | ||
| 877 | |||
| 878 | /* Bit masks for MXVR_ROUTING_4 */ | ||
| 879 | |||
| 880 | #define TX_CH16 0x3f /* Transmit Channel 16 */ | ||
| 881 | #define MUTE_CH16 0x80 /* Mute Channel 16 */ | ||
| 882 | #define TX_CH17 0x3f00 /* Transmit Channel 17 */ | ||
| 883 | #define MUTE_CH17 0x8000 /* Mute Channel 17 */ | ||
| 884 | #define TX_CH18 0x3f0000 /* Transmit Channel 18 */ | ||
| 885 | #define MUTE_CH18 0x800000 /* Mute Channel 18 */ | ||
| 886 | #define TX_CH19 0x3f000000 /* Transmit Channel 19 */ | ||
| 887 | #define MUTE_CH19 0x80000000 /* Mute Channel 19 */ | ||
| 888 | |||
| 889 | /* Bit masks for MXVR_ROUTING_5 */ | ||
| 890 | |||
| 891 | #define TX_CH20 0x3f /* Transmit Channel 20 */ | ||
| 892 | #define MUTE_CH20 0x80 /* Mute Channel 20 */ | ||
| 893 | #define TX_CH21 0x3f00 /* Transmit Channel 21 */ | ||
| 894 | #define MUTE_CH21 0x8000 /* Mute Channel 21 */ | ||
| 895 | #define TX_CH22 0x3f0000 /* Transmit Channel 22 */ | ||
| 896 | #define MUTE_CH22 0x800000 /* Mute Channel 22 */ | ||
| 897 | #define TX_CH23 0x3f000000 /* Transmit Channel 23 */ | ||
| 898 | #define MUTE_CH23 0x80000000 /* Mute Channel 23 */ | ||
| 899 | |||
| 900 | /* Bit masks for MXVR_ROUTING_6 */ | ||
| 901 | |||
| 902 | #define TX_CH24 0x3f /* Transmit Channel 24 */ | ||
| 903 | #define MUTE_CH24 0x80 /* Mute Channel 24 */ | ||
| 904 | #define TX_CH25 0x3f00 /* Transmit Channel 25 */ | ||
| 905 | #define MUTE_CH25 0x8000 /* Mute Channel 25 */ | ||
| 906 | #define TX_CH26 0x3f0000 /* Transmit Channel 26 */ | ||
| 907 | #define MUTE_CH26 0x800000 /* Mute Channel 26 */ | ||
| 908 | #define TX_CH27 0x3f000000 /* Transmit Channel 27 */ | ||
| 909 | #define MUTE_CH27 0x80000000 /* Mute Channel 27 */ | ||
| 910 | |||
| 911 | /* Bit masks for MXVR_ROUTING_7 */ | ||
| 912 | |||
| 913 | #define TX_CH28 0x3f /* Transmit Channel 28 */ | ||
| 914 | #define MUTE_CH28 0x80 /* Mute Channel 28 */ | ||
| 915 | #define TX_CH29 0x3f00 /* Transmit Channel 29 */ | ||
| 916 | #define MUTE_CH29 0x8000 /* Mute Channel 29 */ | ||
| 917 | #define TX_CH30 0x3f0000 /* Transmit Channel 30 */ | ||
| 918 | #define MUTE_CH30 0x800000 /* Mute Channel 30 */ | ||
| 919 | #define TX_CH31 0x3f000000 /* Transmit Channel 31 */ | ||
| 920 | #define MUTE_CH31 0x80000000 /* Mute Channel 31 */ | ||
| 921 | |||
| 922 | /* Bit masks for MXVR_ROUTING_8 */ | ||
| 923 | |||
| 924 | #define TX_CH32 0x3f /* Transmit Channel 32 */ | ||
| 925 | #define MUTE_CH32 0x80 /* Mute Channel 32 */ | ||
| 926 | #define TX_CH33 0x3f00 /* Transmit Channel 33 */ | ||
| 927 | #define MUTE_CH33 0x8000 /* Mute Channel 33 */ | ||
| 928 | #define TX_CH34 0x3f0000 /* Transmit Channel 34 */ | ||
| 929 | #define MUTE_CH34 0x800000 /* Mute Channel 34 */ | ||
| 930 | #define TX_CH35 0x3f000000 /* Transmit Channel 35 */ | ||
| 931 | #define MUTE_CH35 0x80000000 /* Mute Channel 35 */ | ||
| 932 | |||
| 933 | /* Bit masks for MXVR_ROUTING_9 */ | ||
| 934 | |||
| 935 | #define TX_CH36 0x3f /* Transmit Channel 36 */ | ||
| 936 | #define MUTE_CH36 0x80 /* Mute Channel 36 */ | ||
| 937 | #define TX_CH37 0x3f00 /* Transmit Channel 37 */ | ||
| 938 | #define MUTE_CH37 0x8000 /* Mute Channel 37 */ | ||
| 939 | #define TX_CH38 0x3f0000 /* Transmit Channel 38 */ | ||
| 940 | #define MUTE_CH38 0x800000 /* Mute Channel 38 */ | ||
| 941 | #define TX_CH39 0x3f000000 /* Transmit Channel 39 */ | ||
| 942 | #define MUTE_CH39 0x80000000 /* Mute Channel 39 */ | ||
| 943 | |||
| 944 | /* Bit masks for MXVR_ROUTING_10 */ | ||
| 945 | |||
| 946 | #define TX_CH40 0x3f /* Transmit Channel 40 */ | ||
| 947 | #define MUTE_CH40 0x80 /* Mute Channel 40 */ | ||
| 948 | #define TX_CH41 0x3f00 /* Transmit Channel 41 */ | ||
| 949 | #define MUTE_CH41 0x8000 /* Mute Channel 41 */ | ||
| 950 | #define TX_CH42 0x3f0000 /* Transmit Channel 42 */ | ||
| 951 | #define MUTE_CH42 0x800000 /* Mute Channel 42 */ | ||
| 952 | #define TX_CH43 0x3f000000 /* Transmit Channel 43 */ | ||
| 953 | #define MUTE_CH43 0x80000000 /* Mute Channel 43 */ | ||
| 954 | |||
| 955 | /* Bit masks for MXVR_ROUTING_11 */ | ||
| 956 | |||
| 957 | #define TX_CH44 0x3f /* Transmit Channel 44 */ | ||
| 958 | #define MUTE_CH44 0x80 /* Mute Channel 44 */ | ||
| 959 | #define TX_CH45 0x3f00 /* Transmit Channel 45 */ | ||
| 960 | #define MUTE_CH45 0x8000 /* Mute Channel 45 */ | ||
| 961 | #define TX_CH46 0x3f0000 /* Transmit Channel 46 */ | ||
| 962 | #define MUTE_CH46 0x800000 /* Mute Channel 46 */ | ||
| 963 | #define TX_CH47 0x3f000000 /* Transmit Channel 47 */ | ||
| 964 | #define MUTE_CH47 0x80000000 /* Mute Channel 47 */ | ||
| 965 | |||
| 966 | /* Bit masks for MXVR_ROUTING_12 */ | ||
| 967 | |||
| 968 | #define TX_CH48 0x3f /* Transmit Channel 48 */ | ||
| 969 | #define MUTE_CH48 0x80 /* Mute Channel 48 */ | ||
| 970 | #define TX_CH49 0x3f00 /* Transmit Channel 49 */ | ||
| 971 | #define MUTE_CH49 0x8000 /* Mute Channel 49 */ | ||
| 972 | #define TX_CH50 0x3f0000 /* Transmit Channel 50 */ | ||
| 973 | #define MUTE_CH50 0x800000 /* Mute Channel 50 */ | ||
| 974 | #define TX_CH51 0x3f000000 /* Transmit Channel 51 */ | ||
| 975 | #define MUTE_CH51 0x80000000 /* Mute Channel 51 */ | ||
| 976 | |||
| 977 | /* Bit masks for MXVR_ROUTING_13 */ | ||
| 978 | |||
| 979 | #define TX_CH52 0x3f /* Transmit Channel 52 */ | ||
| 980 | #define MUTE_CH52 0x80 /* Mute Channel 52 */ | ||
| 981 | #define TX_CH53 0x3f00 /* Transmit Channel 53 */ | ||
| 982 | #define MUTE_CH53 0x8000 /* Mute Channel 53 */ | ||
| 983 | #define TX_CH54 0x3f0000 /* Transmit Channel 54 */ | ||
| 984 | #define MUTE_CH54 0x800000 /* Mute Channel 54 */ | ||
| 985 | #define TX_CH55 0x3f000000 /* Transmit Channel 55 */ | ||
| 986 | #define MUTE_CH55 0x80000000 /* Mute Channel 55 */ | ||
| 987 | |||
| 988 | /* Bit masks for MXVR_ROUTING_14 */ | ||
| 989 | |||
| 990 | #define TX_CH56 0x3f /* Transmit Channel 56 */ | ||
| 991 | #define MUTE_CH56 0x80 /* Mute Channel 56 */ | ||
| 992 | #define TX_CH57 0x3f00 /* Transmit Channel 57 */ | ||
| 993 | #define MUTE_CH57 0x8000 /* Mute Channel 57 */ | ||
| 994 | #define TX_CH58 0x3f0000 /* Transmit Channel 58 */ | ||
| 995 | #define MUTE_CH58 0x800000 /* Mute Channel 58 */ | ||
| 996 | #define TX_CH59 0x3f000000 /* Transmit Channel 59 */ | ||
| 997 | #define MUTE_CH59 0x80000000 /* Mute Channel 59 */ | ||
| 998 | |||
| 999 | /* Bit masks for MXVR_BLOCK_CNT */ | ||
| 1000 | |||
| 1001 | #define BCNT 0xffff /* Block Count */ | ||
| 1002 | |||
| 1003 | /* Bit masks for MXVR_CLK_CTL */ | ||
| 1004 | |||
| 1005 | #define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */ | ||
| 1006 | #define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */ | ||
| 1007 | #define MXTALMUL 0x30 /* MXVR Crystal Multiplier */ | ||
| 1008 | #define CLKX3SEL 0x80 /* Clock Generation Source Select */ | ||
| 1009 | #define MMCLKEN 0x100 /* Master Clock Enable */ | ||
| 1010 | #define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */ | ||
| 1011 | #define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */ | ||
| 1012 | #define MBCLKEN 0x10000 /* Bit Clock Enable */ | ||
| 1013 | #define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */ | ||
| 1014 | #define INVRX 0x800000 /* Invert Receive Data */ | ||
| 1015 | #define MFSEN 0x1000000 /* Frame Sync Enable */ | ||
| 1016 | #define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */ | ||
| 1017 | #define MFSSEL 0x60000000 /* Frame Sync Select */ | ||
| 1018 | #define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */ | ||
| 1019 | |||
| 1020 | /* Bit masks for MXVR_CDRPLL_CTL */ | ||
| 1021 | |||
| 1022 | #define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */ | ||
| 1023 | #define CDRRSTB 0x2 /* MXVR CDRPLL Reset */ | ||
| 1024 | #define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */ | ||
| 1025 | #define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */ | ||
| 1026 | #define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */ | ||
| 1027 | #define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */ | ||
| 1028 | #define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */ | ||
| 1029 | #define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */ | ||
| 1030 | #define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */ | ||
| 1031 | |||
| 1032 | /* Bit masks for MXVR_FMPLL_CTL */ | ||
| 1033 | |||
| 1034 | #define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */ | ||
| 1035 | #define FMRSTB 0x2 /* MXVR FMPLL Reset */ | ||
| 1036 | #define FMSVCO 0x4 /* MXVR FMPLL Start VCO */ | ||
| 1037 | #define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */ | ||
| 1038 | #define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */ | ||
| 1039 | #define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */ | ||
| 1040 | |||
| 1041 | /* Bit masks for MXVR_PIN_CTL */ | ||
| 1042 | |||
| 1043 | #define MTXONBOD 0x1 /* MTXONB Open Drain Select */ | ||
| 1044 | #define MTXONBG 0x2 /* MTXONB Gates MTX Select */ | ||
| 1045 | #define MFSOE 0x10 /* MFS Output Enable */ | ||
| 1046 | #define MFSGPSEL 0x20 /* MFS General Purpose Output Select */ | ||
| 1047 | #define MFSGPDAT 0x40 /* MFS General Purpose Output Data */ | ||
| 1048 | |||
| 1049 | /* Bit masks for MXVR_SCLK_CNT */ | ||
| 1050 | |||
| 1051 | #define SCNT 0xffff /* System Clock Count */ | ||
| 1052 | |||
| 1053 | /* ******************************************* */ | ||
| 1054 | /* MULTI BIT MACRO ENUMERATIONS */ | ||
| 1055 | /* ******************************************* */ | ||
| 1056 | |||
| 1057 | /* ************************ */ | ||
| 1058 | /* MXVR Address Offsets */ | ||
| 1059 | /* ************************ */ | ||
| 1060 | |||
| 1061 | /* Control Message Receive Buffer (CMRB) Address Offsets */ | ||
| 1062 | |||
| 1063 | #define CMRB_STRIDE 0x00000016lu | ||
| 1064 | |||
| 1065 | #define CMRB_DST_OFFSET 0x00000000lu | ||
| 1066 | #define CMRB_SRC_OFFSET 0x00000002lu | ||
| 1067 | #define CMRB_DATA_OFFSET 0x00000005lu | ||
| 1068 | |||
| 1069 | /* Control Message Transmit Buffer (CMTB) Address Offsets */ | ||
| 1070 | |||
| 1071 | #define CMTB_PRIO_OFFSET 0x00000000lu | ||
| 1072 | #define CMTB_DST_OFFSET 0x00000002lu | ||
| 1073 | #define CMTB_SRC_OFFSET 0x00000004lu | ||
| 1074 | #define CMTB_TYPE_OFFSET 0x00000006lu | ||
| 1075 | #define CMTB_DATA_OFFSET 0x00000007lu | ||
| 1076 | |||
| 1077 | #define CMTB_ANSWER_OFFSET 0x0000000Alu | ||
| 1078 | |||
| 1079 | #define CMTB_STAT_N_OFFSET 0x00000018lu | ||
| 1080 | #define CMTB_STAT_A_OFFSET 0x00000016lu | ||
| 1081 | #define CMTB_STAT_D_OFFSET 0x0000000Elu | ||
| 1082 | #define CMTB_STAT_R_OFFSET 0x00000014lu | ||
| 1083 | #define CMTB_STAT_W_OFFSET 0x00000014lu | ||
| 1084 | #define CMTB_STAT_G_OFFSET 0x00000014lu | ||
| 1085 | |||
| 1086 | /* Asynchronous Packet Receive Buffer (APRB) Address Offsets */ | ||
| 1087 | |||
| 1088 | #define APRB_STRIDE 0x00000400lu | ||
| 1089 | |||
| 1090 | #define APRB_DST_OFFSET 0x00000000lu | ||
| 1091 | #define APRB_LEN_OFFSET 0x00000002lu | ||
| 1092 | #define APRB_SRC_OFFSET 0x00000004lu | ||
| 1093 | #define APRB_DATA_OFFSET 0x00000006lu | ||
| 1094 | |||
| 1095 | /* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */ | ||
| 1096 | |||
| 1097 | #define APTB_PRIO_OFFSET 0x00000000lu | ||
| 1098 | #define APTB_DST_OFFSET 0x00000002lu | ||
| 1099 | #define APTB_LEN_OFFSET 0x00000004lu | ||
| 1100 | #define APTB_SRC_OFFSET 0x00000006lu | ||
| 1101 | #define APTB_DATA_OFFSET 0x00000008lu | ||
| 1102 | |||
| 1103 | /* Remote Read Buffer (RRDB) Address Offsets */ | ||
| 1104 | |||
| 1105 | #define RRDB_WADDR_OFFSET 0x00000100lu | ||
| 1106 | #define RRDB_WLEN_OFFSET 0x00000101lu | ||
| 1107 | |||
| 1108 | /* **************** */ | ||
| 1109 | /* MXVR Macros */ | ||
| 1110 | /* **************** */ | ||
| 1111 | |||
| 1112 | /* MXVR_CONFIG Macros */ | ||
| 1113 | |||
| 1114 | #define SET_MSB(x) ( ( (x) & 0xF ) << 9) | ||
| 1115 | |||
| 1116 | /* MXVR_INT_STAT_1 Macros */ | ||
| 1117 | |||
| 1118 | #define DONEX(x) (0x00000002 << (4 * (x))) | ||
| 1119 | #define HDONEX(x) (0x00000001 << (4 * (x))) | ||
| 1120 | |||
| 1121 | /* MXVR_INT_EN_1 Macros */ | ||
| 1122 | |||
| 1123 | #define DONEENX(x) (0x00000002 << (4 * (x))) | ||
| 1124 | #define HDONEENX(x) (0x00000001 << (4 * (x))) | ||
| 1125 | |||
| 1126 | /* MXVR_CDRPLL_CTL Macros */ | ||
| 1127 | |||
| 1128 | #define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16) | ||
| 1129 | |||
| 1130 | /* MXVR_FMPLL_CTL Macros */ | ||
| 1131 | |||
| 1132 | #define SET_CDRCPSEL(x) ( ( (x) & 0xFF ) << 24) | ||
| 1133 | #define SET_FMCPSEL(x) ( ( (x) & 0xFF ) << 24) | ||
| 1134 | |||
| 1135 | #endif /* _DEF_BF549_H */ | 191 | #endif /* _DEF_BF549_H */ |