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authorRoy Huang <roy.huang@analog.com>2007-07-12 10:41:45 -0400
committerBryan Wu <bryan.wu@analog.com>2007-07-12 10:41:45 -0400
commit24a07a124198153540f8f43d9e91d16227aba66e (patch)
tree917b2011e67e224515830833b1151e276b6c6137 /arch/blackfin/mach-bf548/ints-priority.c
parent088eec1192a0ae60fc218796027e622008af36c0 (diff)
Blackfin arch: initial supporting for BF548-EZKIT
The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia applications where system performance and cost are essential ingredients. The integration of multimedia, human interface, and connectivity peripherals combined with increased system bandwidth and on-chip memory provides customers a platform to design the most demanding applications. Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will be submitted later. Please enjoy the show. Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf548/ints-priority.c')
-rw-r--r--arch/blackfin/mach-bf548/ints-priority.c137
1 files changed, 137 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c
new file mode 100644
index 000000000000..dde450f119e1
--- /dev/null
+++ b/arch/blackfin/mach-bf548/ints-priority.c
@@ -0,0 +1,137 @@
1/*
2 * File: arch/blackfin/mach-bf537/ints-priority.c
3 * Based on: arch/blackfin/mach-bf533/ints-priority.c
4 * Author: Michael Hennerich
5 *
6 * Created:
7 * Description: Set up the interupt priorities
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <asm/blackfin.h>
32#include <asm/irq.h>
33
34void program_IAR(void)
35{
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
38 ((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) |
39 ((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) |
40 ((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) |
41 ((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) |
42 ((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) |
43 ((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) |
44 ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
45
46 bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) |
47 ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
48 ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
49 ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
50 ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
51 ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
52 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
53 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
54
55 bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
56 ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
57 ((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) |
58 ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
59 ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
60 ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
61 ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS));
62
63 bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
64 ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
65 ((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) |
66 ((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) |
67 ((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) |
68 ((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) |
69 ((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) |
70 ((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS));
71
72 bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) |
73 ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
74 ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
75 ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
76 ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
77 ((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) |
78 ((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) |
79 ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
80
81 bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
82 ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
83 ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
84 ((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) |
85 ((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) |
86 ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
87 ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
88 ((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS));
89
90 bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) |
91 ((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) |
92 ((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) |
93 ((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) |
94 ((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) |
95 ((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) |
96 ((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) |
97 ((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS));
98
99 bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) |
100 ((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) |
101 ((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) |
102 ((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) |
103 ((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) |
104 ((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) |
105 ((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS));
106
107 bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) |
108 ((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) |
109 ((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) |
110 ((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) |
111 ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
112 ((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) |
113 ((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) |
114 ((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS));
115
116 bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) |
117 ((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) |
118 ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
119 ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
120 ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
121 ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) |
122 ((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS));
123
124 bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
125 ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS));
126
127 bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
128 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
129 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
130 ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
131 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
132 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
133 ((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) |
134 ((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS));
135
136 SSYNC();
137}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 17:11:43 -0500