diff options
author | Yi Li <yi.li@analog.com> | 2009-01-07 10:14:39 -0500 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2009-01-07 10:14:39 -0500 |
commit | 6a01f230339321292cf065551f8cf55361052461 (patch) | |
tree | 7ac2ac8fc9f05a7315ef6a7f6f0a387433c62c14 /arch/blackfin/mach-bf548/include | |
parent | 5105432a3201e3f0e6c219cd0a74feee1e5e262b (diff) |
Blackfin arch: merge adeos blackfin part to arch/blackfin/
[Mike Frysinger <vapier.adi@gmail.com>:
- handle bf531/bf532/bf534/bf536 variants in ipipe.h
- cleanup IPIPE logic for bfin_set_irq_handler()
- cleanup ipipe asm code a bit and add missing ENDPROC()
- simplify IPIPE code in trap_c
- unify some of the IPIPE code and fix style
- simplify DO_IRQ_L1 handling with ipipe code
- revert IRQ_SW_INT# addition from ipipe merge
- remove duplicate get_{c,s}clk() prototypes
]
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf548/include')
-rw-r--r-- | arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h | 8 | ||||
-rw-r--r-- | arch/blackfin/mach-bf548/include/mach/irq.h | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h index 0a3b210daadf..6e636c418cb0 100644 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h | |||
@@ -2702,7 +2702,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val) | |||
2702 | if (val == bfin_read_PLL_CTL()) | 2702 | if (val == bfin_read_PLL_CTL()) |
2703 | return; | 2703 | return; |
2704 | 2704 | ||
2705 | local_irq_save(flags); | 2705 | local_irq_save_hw(flags); |
2706 | /* Enable the PLL Wakeup bit in SIC IWR */ | 2706 | /* Enable the PLL Wakeup bit in SIC IWR */ |
2707 | iwr0 = bfin_read32(SIC_IWR0); | 2707 | iwr0 = bfin_read32(SIC_IWR0); |
2708 | iwr1 = bfin_read32(SIC_IWR1); | 2708 | iwr1 = bfin_read32(SIC_IWR1); |
@@ -2719,7 +2719,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val) | |||
2719 | bfin_write32(SIC_IWR0, iwr0); | 2719 | bfin_write32(SIC_IWR0, iwr0); |
2720 | bfin_write32(SIC_IWR1, iwr1); | 2720 | bfin_write32(SIC_IWR1, iwr1); |
2721 | bfin_write32(SIC_IWR2, iwr2); | 2721 | bfin_write32(SIC_IWR2, iwr2); |
2722 | local_irq_restore(flags); | 2722 | local_irq_restore_hw(flags); |
2723 | } | 2723 | } |
2724 | 2724 | ||
2725 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | 2725 | /* Writing to VR_CTL initiates a PLL relock sequence. */ |
@@ -2730,7 +2730,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
2730 | if (val == bfin_read_VR_CTL()) | 2730 | if (val == bfin_read_VR_CTL()) |
2731 | return; | 2731 | return; |
2732 | 2732 | ||
2733 | local_irq_save(flags); | 2733 | local_irq_save_hw(flags); |
2734 | /* Enable the PLL Wakeup bit in SIC IWR */ | 2734 | /* Enable the PLL Wakeup bit in SIC IWR */ |
2735 | iwr0 = bfin_read32(SIC_IWR0); | 2735 | iwr0 = bfin_read32(SIC_IWR0); |
2736 | iwr1 = bfin_read32(SIC_IWR1); | 2736 | iwr1 = bfin_read32(SIC_IWR1); |
@@ -2747,7 +2747,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
2747 | bfin_write32(SIC_IWR0, iwr0); | 2747 | bfin_write32(SIC_IWR0, iwr0); |
2748 | bfin_write32(SIC_IWR1, iwr1); | 2748 | bfin_write32(SIC_IWR1, iwr1); |
2749 | bfin_write32(SIC_IWR2, iwr2); | 2749 | bfin_write32(SIC_IWR2, iwr2); |
2750 | local_irq_restore(flags); | 2750 | local_irq_restore_hw(flags); |
2751 | } | 2751 | } |
2752 | 2752 | ||
2753 | #endif /* _CDEF_BF54X_H */ | 2753 | #endif /* _CDEF_BF54X_H */ |
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h index ad380d1f5872..60299a71e090 100644 --- a/arch/blackfin/mach-bf548/include/mach/irq.h +++ b/arch/blackfin/mach-bf548/include/mach/irq.h | |||
@@ -158,7 +158,7 @@ Events (highest priority) EMU 0 | |||
158 | #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ | 158 | #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ |
159 | #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ | 159 | #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ |
160 | 160 | ||
161 | #define SYS_IRQS IRQ_PINT3 | 161 | #define SYS_IRQS IRQ_PINT3 |
162 | 162 | ||
163 | #define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) | 163 | #define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) |
164 | #define IRQ_PA0 BFIN_PA_IRQ(0) | 164 | #define IRQ_PA0 BFIN_PA_IRQ(0) |