diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2009-10-20 13:20:21 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-12-15 00:14:59 -0500 |
| commit | 00d2460454676344a55a03f03fa284ad69325592 (patch) | |
| tree | 7885d8dcdeb1ffc026bc4888e1074ce7b8133c7a /arch/blackfin/mach-bf548/include | |
| parent | c6feb7682885f732a264ef589ee44edb1a3d45f2 (diff) | |
Blackfin: unify DMA masks
Every Blackfin variant has the same DMA bit masks, so avoid duplicating
them over and over in each mach header.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548/include')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF54x_base.h | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index 6d97b4e892b4..ab04d137fd8b 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h | |||
| @@ -1609,44 +1609,6 @@ | |||
| 1609 | #define PINT2 0x40000000 /* Pin Interrupt 2 */ | 1609 | #define PINT2 0x40000000 /* Pin Interrupt 2 */ |
| 1610 | #define PINT3 0x80000000 /* Pin Interrupt 3 */ | 1610 | #define PINT3 0x80000000 /* Pin Interrupt 3 */ |
| 1611 | 1611 | ||
| 1612 | /* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ | ||
| 1613 | |||
| 1614 | #define DMAEN 0x1 /* DMA Channel Enable */ | ||
| 1615 | #define WNR 0x2 /* DMA Direction */ | ||
| 1616 | #define WDSIZE_8 0x0 /* Transfer Word Size = 8 */ | ||
| 1617 | #define WDSIZE_16 0x4 /* Transfer Word Size = 16 */ | ||
| 1618 | #define WDSIZE_32 0x8 /* Transfer Word Size = 32 */ | ||
| 1619 | #define DMA2D 0x10 /* DMA Mode */ | ||
| 1620 | #define RESTART 0x20 /* Work Unit Transitions */ | ||
| 1621 | #define DI_SEL 0x40 /* Data Interrupt Timing Select */ | ||
| 1622 | #define DI_EN 0x80 /* Data Interrupt Enable */ | ||
| 1623 | |||
| 1624 | #define NDSIZE 0xf00 /* Flex Descriptor Size */ | ||
| 1625 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ | ||
| 1626 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ | ||
| 1627 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ | ||
| 1628 | #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ | ||
| 1629 | #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ | ||
| 1630 | #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ | ||
| 1631 | #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ | ||
| 1632 | #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ | ||
| 1633 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ | ||
| 1634 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ | ||
| 1635 | |||
| 1636 | #define DMAFLOW 0xf000 /* Next Operation */ | ||
| 1637 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ | ||
| 1638 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ | ||
| 1639 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ | ||
| 1640 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ | ||
| 1641 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ | ||
| 1642 | |||
| 1643 | /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ | ||
| 1644 | |||
| 1645 | #define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ | ||
| 1646 | #define DMA_ERR 0x2 /* DMA Error Interrupt Status */ | ||
| 1647 | #define DFETCH 0x4 /* DMA Descriptor Fetch */ | ||
| 1648 | #define DMA_RUN 0x8 /* DMA Channel Running */ | ||
| 1649 | |||
| 1650 | /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ | 1612 | /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ |
| 1651 | 1613 | ||
| 1652 | #define CTYPE 0x40 /* DMA Channel Type */ | 1614 | #define CTYPE 0x40 /* DMA Channel Type */ |