diff options
| author | Michael Hennerich <michael.hennerich@analog.com> | 2009-03-02 05:06:13 -0500 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2009-03-02 05:06:13 -0500 |
| commit | 0f29456a21ae55c43b4e2a64611f778b1fbe4bdf (patch) | |
| tree | dc25ccaea0836ca2e261f9439d4ca8e94067bea4 /arch/blackfin/mach-bf548/include | |
| parent | 28e4cf22a3707d05eb697b9b8ae6a4ed39c99b45 (diff) | |
Blackfin arch: Make IRQ_EPPIx_ERROR naming consistent
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf548/include')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/irq.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h index 60299a71e090..f194625f6821 100644 --- a/arch/blackfin/mach-bf548/include/mach/irq.h +++ b/arch/blackfin/mach-bf548/include/mach/irq.h | |||
| @@ -123,8 +123,8 @@ Events (highest priority) EMU 0 | |||
| 123 | #define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ | 123 | #define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ |
| 124 | #define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ | 124 | #define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ |
| 125 | #define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ | 125 | #define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ |
| 126 | #define IRQ_EPP1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ | 126 | #define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ |
| 127 | #define IRQ_EPP2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ | 127 | #define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ |
| 128 | #define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ | 128 | #define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ |
| 129 | #define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ | 129 | #define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ |
| 130 | #define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ | 130 | #define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ |
| @@ -361,8 +361,8 @@ Events (highest priority) EMU 0 | |||
| 361 | #define IRQ_UART2_ERR IRQ_UART2_ERROR | 361 | #define IRQ_UART2_ERR IRQ_UART2_ERROR |
| 362 | #define IRQ_CAN0_ERR IRQ_CAN0_ERROR | 362 | #define IRQ_CAN0_ERR IRQ_CAN0_ERROR |
| 363 | #define IRQ_MXVR_ERR IRQ_MXVR_ERROR | 363 | #define IRQ_MXVR_ERR IRQ_MXVR_ERROR |
| 364 | #define IRQ_EPP1_ERR IRQ_EPP1_ERROR | 364 | #define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR |
| 365 | #define IRQ_EPP2_ERR IRQ_EPP2_ERROR | 365 | #define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR |
| 366 | #define IRQ_UART3_ERR IRQ_UART3_ERROR | 366 | #define IRQ_UART3_ERR IRQ_UART3_ERROR |
| 367 | #define IRQ_HOST_ERR IRQ_HOST_ERROR | 367 | #define IRQ_HOST_ERR IRQ_HOST_ERROR |
| 368 | #define IRQ_PIXC_ERR IRQ_PIXC_ERROR | 368 | #define IRQ_PIXC_ERR IRQ_PIXC_ERROR |