diff options
| author | steven miao <realmz6@gmail.com> | 2010-10-22 04:48:41 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-03-18 03:49:23 -0400 |
| commit | 55835175a03392d2e4d9bff9d482312d118f304e (patch) | |
| tree | 51157bc604b5c5baa917bd22f420fa6291d5da76 /arch/blackfin/mach-bf548/include/mach/irq.h | |
| parent | 6ce0466d631d40662e2ab9ec5a05019482bd1074 (diff) | |
Blackfin: bf54x: add kconfig for UART2/3 DMA channel assignments
The BF54x lacks dedicated DMA channels for the UART peripherals and need
to be muxed between others. So add a kconfig option so people can select
which channels the UARTs will use so they can pick between SPORTs and the
less commonly used EPPI/PIXC peripherals.
Signed-off-by: steven miao <realmz6@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach/irq.h')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/irq.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h index 99fd1b2c53d8..7f87787e7738 100644 --- a/arch/blackfin/mach-bf548/include/mach/irq.h +++ b/arch/blackfin/mach-bf548/include/mach/irq.h | |||
| @@ -74,13 +74,9 @@ Events (highest priority) EMU 0 | |||
| 74 | #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ | 74 | #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ |
| 75 | #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ | 75 | #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ |
| 76 | #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ | 76 | #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ |
| 77 | #define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */ | ||
| 78 | #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ | 77 | #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ |
| 79 | #define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */ | ||
| 80 | #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ | 78 | #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ |
| 81 | #define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */ | ||
| 82 | #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ | 79 | #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ |
| 83 | #define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */ | ||
| 84 | #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ | 80 | #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ |
| 85 | #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ | 81 | #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ |
| 86 | #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ | 82 | #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ |