diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2010-07-29 01:28:32 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-08-06 12:55:56 -0400 |
| commit | c385acceb4db55a492cb16b24b6102af90348440 (patch) | |
| tree | 9046eedaa8a44954d1b76764a906f2eb5ccc9dab /arch/blackfin/mach-bf548/include/mach/defBF542.h | |
| parent | 2b73a19f2d3391b070d9d9270a9c9d502fe357ce (diff) | |
Blackfin: unify SDH/RSI bitmasks
Avoid duplication and ugly global namespace pollution.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach/defBF542.h')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF542.h | 130 |
1 files changed, 0 insertions, 130 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h index d3bc6d1df547..abf5f750dd8b 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF542.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h | |||
| @@ -366,136 +366,6 @@ | |||
| 366 | 366 | ||
| 367 | #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ | 367 | #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ |
| 368 | 368 | ||
| 369 | /* Bit masks for SDH_COMMAND */ | ||
| 370 | |||
| 371 | #define CMD_IDX 0x3f /* Command Index */ | ||
| 372 | #define CMD_RSP 0x40 /* Response */ | ||
| 373 | #define CMD_L_RSP 0x80 /* Long Response */ | ||
| 374 | #define CMD_INT_E 0x100 /* Command Interrupt */ | ||
| 375 | #define CMD_PEND_E 0x200 /* Command Pending */ | ||
| 376 | #define CMD_E 0x400 /* Command Enable */ | ||
| 377 | |||
| 378 | /* Bit masks for SDH_PWR_CTL */ | ||
| 379 | |||
| 380 | #define PWR_ON 0x3 /* Power On */ | ||
| 381 | #if 0 | ||
| 382 | #define TBD 0x3c /* TBD */ | ||
| 383 | #endif | ||
| 384 | #define SD_CMD_OD 0x40 /* Open Drain Output */ | ||
| 385 | #define ROD_CTL 0x80 /* Rod Control */ | ||
| 386 | |||
| 387 | /* Bit masks for SDH_CLK_CTL */ | ||
| 388 | |||
| 389 | #define CLKDIV 0xff /* MC_CLK Divisor */ | ||
| 390 | #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ | ||
| 391 | #define PWR_SV_E 0x200 /* Power Save Enable */ | ||
| 392 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ | ||
| 393 | #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ | ||
| 394 | |||
| 395 | /* Bit masks for SDH_RESP_CMD */ | ||
| 396 | |||
| 397 | #define RESP_CMD 0x3f /* Response Command */ | ||
| 398 | |||
| 399 | /* Bit masks for SDH_DATA_CTL */ | ||
| 400 | |||
| 401 | #define DTX_E 0x1 /* Data Transfer Enable */ | ||
| 402 | #define DTX_DIR 0x2 /* Data Transfer Direction */ | ||
| 403 | #define DTX_MODE 0x4 /* Data Transfer Mode */ | ||
| 404 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ | ||
| 405 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ | ||
| 406 | |||
| 407 | /* Bit masks for SDH_STATUS */ | ||
| 408 | |||
| 409 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ | ||
| 410 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ | ||
| 411 | #define CMD_TIME_OUT 0x4 /* CMD Time Out */ | ||
| 412 | #define DAT_TIME_OUT 0x8 /* Data Time Out */ | ||
| 413 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ | ||
| 414 | #define RX_OVERRUN 0x20 /* Receive Overrun */ | ||
| 415 | #define CMD_RESP_END 0x40 /* CMD Response End */ | ||
| 416 | #define CMD_SENT 0x80 /* CMD Sent */ | ||
| 417 | #define DAT_END 0x100 /* Data End */ | ||
| 418 | #define START_BIT_ERR 0x200 /* Start Bit Error */ | ||
| 419 | #define DAT_BLK_END 0x400 /* Data Block End */ | ||
| 420 | #define CMD_ACT 0x800 /* CMD Active */ | ||
| 421 | #define TX_ACT 0x1000 /* Transmit Active */ | ||
| 422 | #define RX_ACT 0x2000 /* Receive Active */ | ||
| 423 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ | ||
| 424 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ | ||
| 425 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ | ||
| 426 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ | ||
| 427 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ | ||
| 428 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ | ||
| 429 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ | ||
| 430 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ | ||
| 431 | |||
| 432 | /* Bit masks for SDH_STATUS_CLR */ | ||
| 433 | |||
| 434 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ | ||
| 435 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ | ||
| 436 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ | ||
| 437 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ | ||
| 438 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ | ||
| 439 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ | ||
| 440 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ | ||
| 441 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ | ||
| 442 | #define DAT_END_STAT 0x100 /* Data End Status */ | ||
| 443 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ | ||
| 444 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ | ||
| 445 | |||
| 446 | /* Bit masks for SDH_MASK0 */ | ||
| 447 | |||
| 448 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ | ||
| 449 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ | ||
| 450 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ | ||
| 451 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ | ||
| 452 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ | ||
| 453 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ | ||
| 454 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ | ||
| 455 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ | ||
| 456 | #define DAT_END_MASK 0x100 /* Data End Mask */ | ||
| 457 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ | ||
| 458 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ | ||
| 459 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ | ||
| 460 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ | ||
| 461 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ | ||
| 462 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ | ||
| 463 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ | ||
| 464 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ | ||
| 465 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ | ||
| 466 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ | ||
| 467 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ | ||
| 468 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ | ||
| 469 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ | ||
| 470 | |||
| 471 | /* Bit masks for SDH_FIFO_CNT */ | ||
| 472 | |||
| 473 | #define FIFO_COUNT 0x7fff /* FIFO Count */ | ||
| 474 | |||
| 475 | /* Bit masks for SDH_E_STATUS */ | ||
| 476 | |||
| 477 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ | ||
| 478 | #define SD_CARD_DET 0x10 /* SD Card Detect */ | ||
| 479 | |||
| 480 | /* Bit masks for SDH_E_MASK */ | ||
| 481 | |||
| 482 | #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ | ||
| 483 | #define SCD_MSK 0x40 /* Mask Card Detect */ | ||
| 484 | |||
| 485 | /* Bit masks for SDH_CFG */ | ||
| 486 | |||
| 487 | #define CLKS_EN 0x1 /* Clocks Enable */ | ||
| 488 | #define SD4E 0x4 /* SDIO 4-Bit Enable */ | ||
| 489 | #define MWE 0x8 /* Moving Window Enable */ | ||
| 490 | #define SD_RST 0x10 /* SDMMC Reset */ | ||
| 491 | #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ | ||
| 492 | #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ | ||
| 493 | #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ | ||
| 494 | |||
| 495 | /* Bit masks for SDH_RD_WAIT_EN */ | ||
| 496 | |||
| 497 | #define RWR 0x1 /* Read Wait Request */ | ||
| 498 | |||
| 499 | /* Bit masks for ATAPI_CONTROL */ | 369 | /* Bit masks for ATAPI_CONTROL */ |
| 500 | 370 | ||
| 501 | #define PIO_START 0x1 /* Start PIO/Reg Op */ | 371 | #define PIO_START 0x1 /* Start PIO/Reg Op */ |