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authorRoy Huang <roy.huang@analog.com>2007-07-12 10:41:45 -0400
committerBryan Wu <bryan.wu@analog.com>2007-07-12 10:41:45 -0400
commit24a07a124198153540f8f43d9e91d16227aba66e (patch)
tree917b2011e67e224515830833b1151e276b6c6137 /arch/blackfin/mach-bf548/dma.c
parent088eec1192a0ae60fc218796027e622008af36c0 (diff)
Blackfin arch: initial supporting for BF548-EZKIT
The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia applications where system performance and cost are essential ingredients. The integration of multimedia, human interface, and connectivity peripherals combined with increased system bandwidth and on-chip memory provides customers a platform to design the most demanding applications. Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will be submitted later. Please enjoy the show. Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf548/dma.c')
-rw-r--r--arch/blackfin/mach-bf548/dma.c156
1 files changed, 156 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
new file mode 100644
index 000000000000..a8184113be48
--- /dev/null
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -0,0 +1,156 @@
1/*
2 * File: arch/blackfin/mach-bf561/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <asm/blackfin.h>
31#include <asm/dma.h>
32
33 struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
34 (struct dma_register *) DMA0_NEXT_DESC_PTR,
35 (struct dma_register *) DMA1_NEXT_DESC_PTR,
36 (struct dma_register *) DMA2_NEXT_DESC_PTR,
37 (struct dma_register *) DMA3_NEXT_DESC_PTR,
38 (struct dma_register *) DMA4_NEXT_DESC_PTR,
39 (struct dma_register *) DMA5_NEXT_DESC_PTR,
40 (struct dma_register *) DMA6_NEXT_DESC_PTR,
41 (struct dma_register *) DMA7_NEXT_DESC_PTR,
42 (struct dma_register *) DMA8_NEXT_DESC_PTR,
43 (struct dma_register *) DMA9_NEXT_DESC_PTR,
44 (struct dma_register *) DMA10_NEXT_DESC_PTR,
45 (struct dma_register *) DMA11_NEXT_DESC_PTR,
46 (struct dma_register *) DMA12_NEXT_DESC_PTR,
47 (struct dma_register *) DMA13_NEXT_DESC_PTR,
48 (struct dma_register *) DMA14_NEXT_DESC_PTR,
49 (struct dma_register *) DMA15_NEXT_DESC_PTR,
50 (struct dma_register *) DMA16_NEXT_DESC_PTR,
51 (struct dma_register *) DMA17_NEXT_DESC_PTR,
52 (struct dma_register *) DMA18_NEXT_DESC_PTR,
53 (struct dma_register *) DMA19_NEXT_DESC_PTR,
54 (struct dma_register *) DMA20_NEXT_DESC_PTR,
55 (struct dma_register *) DMA21_NEXT_DESC_PTR,
56 (struct dma_register *) DMA22_NEXT_DESC_PTR,
57 (struct dma_register *) DMA23_NEXT_DESC_PTR,
58 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
59 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
60 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
61 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
62 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
63 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
64 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
65 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
66};
67
68int channel2irq(unsigned int channel)
69{
70 int ret_irq = -1;
71
72 switch (channel) {
73 case CH_SPORT0_RX:
74 ret_irq = IRQ_SPORT0_RX;
75 break;
76 case CH_SPORT0_TX:
77 ret_irq = IRQ_SPORT0_TX;
78 break;
79 case CH_SPORT1_RX:
80 ret_irq = IRQ_SPORT1_RX;
81 break;
82 case CH_SPORT1_TX:
83 ret_irq = IRQ_SPORT1_TX;
84 case CH_SPI0:
85 ret_irq = IRQ_SPI0;
86 break;
87 case CH_SPI1:
88 ret_irq = IRQ_SPI1;
89 break;
90 case CH_UART0_RX:
91 ret_irq = IRQ_UART_RX;
92 break;
93 case CH_UART0_TX:
94 ret_irq = IRQ_UART_TX;
95 break;
96 case CH_UART1_RX:
97 ret_irq = IRQ_UART_RX;
98 break;
99 case CH_UART1_TX:
100 ret_irq = IRQ_UART_TX;
101 break;
102 case CH_EPPI0:
103 ret_irq = IRQ_EPPI0;
104 break;
105 case CH_EPPI1:
106 ret_irq = IRQ_EPPI1;
107 break;
108 case CH_EPPI2:
109 ret_irq = IRQ_EPPI2;
110 break;
111 case CH_PIXC_IMAGE:
112 ret_irq = IRQ_PIXC_IN0;
113 break;
114 case CH_PIXC_OVERLAY:
115 ret_irq = IRQ_PIXC_IN1;
116 break;
117 case CH_PIXC_OUTPUT:
118 ret_irq = IRQ_PIXC_OUT;
119 break;
120 case CH_SPORT2_RX:
121 ret_irq = IRQ_SPORT2_RX;
122 break;
123 case CH_SPORT2_TX:
124 ret_irq = IRQ_SPORT2_TX;
125 break;
126 case CH_SPORT3_RX:
127 ret_irq = IRQ_SPORT3_RX;
128 break;
129 case CH_SPORT3_TX:
130 ret_irq = IRQ_SPORT3_TX;
131 break;
132 case CH_SDH:
133 ret_irq = IRQ_SDH;
134 break;
135 case CH_SPI2:
136 ret_irq = IRQ_SPI2;
137 break;
138 case CH_MEM_STREAM0_SRC:
139 case CH_MEM_STREAM0_DEST:
140 ret_irq = IRQ_MDMAS0;
141 break;
142 case CH_MEM_STREAM1_SRC:
143 case CH_MEM_STREAM1_DEST:
144 ret_irq = IRQ_MDMAS1;
145 break;
146 case CH_MEM_STREAM2_SRC:
147 case CH_MEM_STREAM2_DEST:
148 ret_irq = IRQ_MDMAS2;
149 break;
150 case CH_MEM_STREAM3_SRC:
151 case CH_MEM_STREAM3_DEST:
152 ret_irq = IRQ_MDMAS3;
153 break;
154 }
155 return ret_irq;
156}
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