diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2010-07-28 15:59:03 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-08-06 12:55:55 -0400 |
| commit | ba3f5973ce3eb7ef4894ccd3df78c5cb410b17cc (patch) | |
| tree | 45880a04101440fe731ab15bca490886aaf50754 /arch/blackfin/mach-bf538 | |
| parent | ada091729e8737edc3d455681fda9f745cfd2b63 (diff) | |
Blackfin: TWI: clean up the MMR names
The standard short name for control is CTL and not CTRL. Use TWI0_xxx
even on parts that only have one TWI bus to keep things simple. Drop
all the cdef helpers since the bus driver takes care of everything.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf538')
| -rw-r--r-- | arch/blackfin/mach-bf538/include/mach/cdefBF538.h | 64 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf538/include/mach/defBF539.h | 14 |
2 files changed, 7 insertions, 71 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h index 401ebd79d0aa..66aa722cf6c8 100644 --- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h +++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h | |||
| @@ -1293,70 +1293,6 @@ | |||
| 1293 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) | 1293 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) |
| 1294 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) | 1294 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) |
| 1295 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) | 1295 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) |
| 1296 | #define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) | ||
| 1297 | #define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) | ||
| 1298 | #define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) | ||
| 1299 | #define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) | ||
| 1300 | #define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) | ||
| 1301 | #define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) | ||
| 1302 | #define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) | ||
| 1303 | #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) | ||
| 1304 | #define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) | ||
| 1305 | #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) | ||
| 1306 | #define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) | ||
| 1307 | #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) | ||
| 1308 | #define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) | ||
| 1309 | #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) | ||
| 1310 | #define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) | ||
| 1311 | #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) | ||
| 1312 | #define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) | ||
| 1313 | #define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) | ||
| 1314 | #define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) | ||
| 1315 | #define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) | ||
| 1316 | #define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) | ||
| 1317 | #define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) | ||
| 1318 | #define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) | ||
| 1319 | #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) | ||
| 1320 | #define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) | ||
| 1321 | #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) | ||
| 1322 | #define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) | ||
| 1323 | #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) | ||
| 1324 | #define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) | ||
| 1325 | #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) | ||
| 1326 | #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) | ||
| 1327 | #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) | ||
| 1328 | #define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) | ||
| 1329 | #define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) | ||
| 1330 | #define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) | ||
| 1331 | #define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) | ||
| 1332 | #define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) | ||
| 1333 | #define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) | ||
| 1334 | #define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) | ||
| 1335 | #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) | ||
| 1336 | #define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) | ||
| 1337 | #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) | ||
| 1338 | #define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) | ||
| 1339 | #define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) | ||
| 1340 | #define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) | ||
| 1341 | #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) | ||
| 1342 | #define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) | ||
| 1343 | #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) | ||
| 1344 | #define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) | ||
| 1345 | #define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) | ||
| 1346 | #define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) | ||
| 1347 | #define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) | ||
| 1348 | #define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) | ||
| 1349 | #define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) | ||
| 1350 | #define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) | ||
| 1351 | #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) | ||
| 1352 | #define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) | ||
| 1353 | #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) | ||
| 1354 | #define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) | ||
| 1355 | #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) | ||
| 1356 | #define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) | ||
| 1357 | #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) | ||
| 1358 | #define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) | ||
| 1359 | #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) | ||
| 1360 | #define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) | 1296 | #define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) |
| 1361 | #define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) | 1297 | #define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) |
| 1362 | #define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) | 1298 | #define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) |
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h index d7061d9f2a83..b674a1c4aef1 100644 --- a/arch/blackfin/mach-bf538/include/mach/defBF539.h +++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h | |||
| @@ -442,15 +442,15 @@ | |||
| 442 | /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ | 442 | /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ |
| 443 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ | 443 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
| 444 | #define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ | 444 | #define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ |
| 445 | #define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */ | 445 | #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ |
| 446 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | 446 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
| 447 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | 447 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
| 448 | #define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */ | 448 | #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
| 449 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | 449 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
| 450 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | 450 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
| 451 | #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ | 451 | #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ |
| 452 | #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ | 452 | #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ |
| 453 | #define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */ | 453 | #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
| 454 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | 454 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
| 455 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | 455 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
| 456 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | 456 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
| @@ -761,15 +761,15 @@ | |||
| 761 | /* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ | 761 | /* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ |
| 762 | #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ | 762 | #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ |
| 763 | #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ | 763 | #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ |
| 764 | #define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */ | 764 | #define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */ |
| 765 | #define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ | 765 | #define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ |
| 766 | #define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ | 766 | #define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ |
| 767 | #define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */ | 767 | #define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */ |
| 768 | #define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ | 768 | #define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ |
| 769 | #define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ | 769 | #define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ |
| 770 | #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ | 770 | #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ |
| 771 | #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ | 771 | #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ |
| 772 | #define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */ | 772 | #define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */ |
| 773 | #define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ | 773 | #define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ |
| 774 | #define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ | 774 | #define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ |
| 775 | #define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ | 775 | #define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ |
| @@ -2401,7 +2401,7 @@ | |||
| 2401 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ | 2401 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ |
| 2402 | #define RCVSERV 0x0080 /* Receive FIFO Service */ | 2402 | #define RCVSERV 0x0080 /* Receive FIFO Service */ |
| 2403 | 2403 | ||
| 2404 | /* TWIx_FIFO_CTRL Masks */ | 2404 | /* TWIx_FIFO_CTL Masks */ |
| 2405 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ | 2405 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ |
| 2406 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ | 2406 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ |
| 2407 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ | 2407 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ |