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authorMike Frysinger <vapier@gentoo.org>2010-10-25 21:11:10 -0400
committerMike Frysinger <vapier@gentoo.org>2011-01-10 07:18:06 -0500
commit4de2bf8786ec8ec9a45b556e1ddf5c80c807a361 (patch)
tree7ac3dbd87b81d207c8417b5e581122ff5dba0fa4 /arch/blackfin/mach-bf538
parent9887f41533c860777b2fcf2eccf04f95980ab52a (diff)
Blackfin: push gpio (port) defines into common headers
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf538')
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h129
-rw-r--r--arch/blackfin/mach-bf538/include/mach/gpio.h5
2 files changed, 5 insertions, 129 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 1dcf16f25b1f..e0aad63b55ca 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1627,135 +1627,6 @@
1627#define ERR_TYP_P0 0x0E 1627#define ERR_TYP_P0 0x0E
1628#define ERR_TYP_P1 0x0F 1628#define ERR_TYP_P1 0x0F
1629 1629
1630
1631/*/ ****************** GENERAL-PURPOSE I/O ********************* */
1632/* Flag I/O (FIO_) Masks */
1633#define PF0 0x0001
1634#define PF1 0x0002
1635#define PF2 0x0004
1636#define PF3 0x0008
1637#define PF4 0x0010
1638#define PF5 0x0020
1639#define PF6 0x0040
1640#define PF7 0x0080
1641#define PF8 0x0100
1642#define PF9 0x0200
1643#define PF10 0x0400
1644#define PF11 0x0800
1645#define PF12 0x1000
1646#define PF13 0x2000
1647#define PF14 0x4000
1648#define PF15 0x8000
1649
1650/* PORT F BIT POSITIONS */
1651#define PF0_P 0x0
1652#define PF1_P 0x1
1653#define PF2_P 0x2
1654#define PF3_P 0x3
1655#define PF4_P 0x4
1656#define PF5_P 0x5
1657#define PF6_P 0x6
1658#define PF7_P 0x7
1659#define PF8_P 0x8
1660#define PF9_P 0x9
1661#define PF10_P 0xA
1662#define PF11_P 0xB
1663#define PF12_P 0xC
1664#define PF13_P 0xD
1665#define PF14_P 0xE
1666#define PF15_P 0xF
1667
1668
1669/******************* GPIO MASKS *********************/
1670/* Port C Masks */
1671#define PC0 0x0001
1672#define PC1 0x0002
1673#define PC4 0x0010
1674#define PC5 0x0020
1675#define PC6 0x0040
1676#define PC7 0x0080
1677#define PC8 0x0100
1678#define PC9 0x0200
1679/* Port C Bit Positions */
1680#define PC0_P 0x0
1681#define PC1_P 0x1
1682#define PC4_P 0x4
1683#define PC5_P 0x5
1684#define PC6_P 0x6
1685#define PC7_P 0x7
1686#define PC8_P 0x8
1687#define PC9_P 0x9
1688
1689/* Port D */
1690#define PD0 0x0001
1691#define PD1 0x0002
1692#define PD2 0x0004
1693#define PD3 0x0008
1694#define PD4 0x0010
1695#define PD5 0x0020
1696#define PD6 0x0040
1697#define PD7 0x0080
1698#define PD8 0x0100
1699#define PD9 0x0200
1700#define PD10 0x0400
1701#define PD11 0x0800
1702#define PD12 0x1000
1703#define PD13 0x2000
1704#define PD14 0x4000
1705#define PD15 0x8000
1706/* Port D Bit Positions */
1707#define PD0_P 0x0
1708#define PD1_P 0x1
1709#define PD2_P 0x2
1710#define PD3_P 0x3
1711#define PD4_P 0x4
1712#define PD5_P 0x5
1713#define PD6_P 0x6
1714#define PD7_P 0x7
1715#define PD8_P 0x8
1716#define PD9_P 0x9
1717#define PD10_P 0xA
1718#define PD11_P 0xB
1719#define PD12_P 0xC
1720#define PD13_P 0xD
1721#define PD14_P 0xE
1722#define PD15_P 0xF
1723
1724/* Port E */
1725#define PE0 0x0001
1726#define PE1 0x0002
1727#define PE2 0x0004
1728#define PE3 0x0008
1729#define PE4 0x0010
1730#define PE5 0x0020
1731#define PE6 0x0040
1732#define PE7 0x0080
1733#define PE8 0x0100
1734#define PE9 0x0200
1735#define PE10 0x0400
1736#define PE11 0x0800
1737#define PE12 0x1000
1738#define PE13 0x2000
1739#define PE14 0x4000
1740#define PE15 0x8000
1741/* Port E Bit Positions */
1742#define PE0_P 0x0
1743#define PE1_P 0x1
1744#define PE2_P 0x2
1745#define PE3_P 0x3
1746#define PE4_P 0x4
1747#define PE5_P 0x5
1748#define PE6_P 0x6
1749#define PE7_P 0x7
1750#define PE8_P 0x8
1751#define PE9_P 0x9
1752#define PE10_P 0xA
1753#define PE11_P 0xB
1754#define PE12_P 0xC
1755#define PE13_P 0xD
1756#define PE14_P 0xE
1757#define PE15_P 0xF
1758
1759/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 1630/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
1760/* EBIU_AMGCTL Masks */ 1631/* EBIU_AMGCTL Masks */
1761#define AMCKEN 0x0001 /* Enable CLKOUT */ 1632#define AMCKEN 0x0001 /* Enable CLKOUT */
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
index bd9adb7183da..8a5beeece996 100644
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -70,4 +70,9 @@
70#define PORT_D GPIO_PD0 70#define PORT_D GPIO_PD0
71#define PORT_E GPIO_PE0 71#define PORT_E GPIO_PE0
72 72
73#include <mach-common/ports-c.h>
74#include <mach-common/ports-d.h>
75#include <mach-common/ports-e.h>
76#include <mach-common/ports-f.h>
77
73#endif /* _MACH_GPIO_H_ */ 78#endif /* _MACH_GPIO_H_ */