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authorYi Li <yi.li@analog.com>2009-01-07 10:14:39 -0500
committerBryan Wu <cooloney@kernel.org>2009-01-07 10:14:39 -0500
commit6a01f230339321292cf065551f8cf55361052461 (patch)
tree7ac2ac8fc9f05a7315ef6a7f6f0a387433c62c14 /arch/blackfin/mach-bf538/include
parent5105432a3201e3f0e6c219cd0a74feee1e5e262b (diff)
Blackfin arch: merge adeos blackfin part to arch/blackfin/
[Mike Frysinger <vapier.adi@gmail.com>: - handle bf531/bf532/bf534/bf536 variants in ipipe.h - cleanup IPIPE logic for bfin_set_irq_handler() - cleanup ipipe asm code a bit and add missing ENDPROC() - simplify IPIPE code in trap_c - unify some of the IPIPE code and fix style - simplify DO_IRQ_L1 handling with ipipe code - revert IRQ_SW_INT# addition from ipipe merge - remove duplicate get_{c,s}clk() prototypes ] Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf538/include')
-rw-r--r--arch/blackfin/mach-bf538/include/mach/cdefBF538.h8
-rw-r--r--arch/blackfin/mach-bf538/include/mach/irq.h12
2 files changed, 10 insertions, 10 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
index 7e469b8d939c..241725bc6988 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -2063,7 +2063,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2063 if (val == bfin_read_PLL_CTL()) 2063 if (val == bfin_read_PLL_CTL())
2064 return; 2064 return;
2065 2065
2066 local_irq_save(flags); 2066 local_irq_save_hw(flags);
2067 /* Enable the PLL Wakeup bit in SIC IWR */ 2067 /* Enable the PLL Wakeup bit in SIC IWR */
2068 iwr0 = bfin_read32(SIC_IWR0); 2068 iwr0 = bfin_read32(SIC_IWR0);
2069 iwr1 = bfin_read32(SIC_IWR1); 2069 iwr1 = bfin_read32(SIC_IWR1);
@@ -2077,7 +2077,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2077 2077
2078 bfin_write32(SIC_IWR0, iwr0); 2078 bfin_write32(SIC_IWR0, iwr0);
2079 bfin_write32(SIC_IWR1, iwr1); 2079 bfin_write32(SIC_IWR1, iwr1);
2080 local_irq_restore(flags); 2080 local_irq_restore_hw(flags);
2081} 2081}
2082 2082
2083/* Writing to VR_CTL initiates a PLL relock sequence. */ 2083/* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -2088,7 +2088,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
2088 if (val == bfin_read_VR_CTL()) 2088 if (val == bfin_read_VR_CTL())
2089 return; 2089 return;
2090 2090
2091 local_irq_save(flags); 2091 local_irq_save_hw(flags);
2092 /* Enable the PLL Wakeup bit in SIC IWR */ 2092 /* Enable the PLL Wakeup bit in SIC IWR */
2093 iwr0 = bfin_read32(SIC_IWR0); 2093 iwr0 = bfin_read32(SIC_IWR0);
2094 iwr1 = bfin_read32(SIC_IWR1); 2094 iwr1 = bfin_read32(SIC_IWR1);
@@ -2102,7 +2102,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
2102 2102
2103 bfin_write32(SIC_IWR0, iwr0); 2103 bfin_write32(SIC_IWR0, iwr0);
2104 bfin_write32(SIC_IWR1, iwr1); 2104 bfin_write32(SIC_IWR1, iwr1);
2105 local_irq_restore(flags); 2105 local_irq_restore_hw(flags);
2106} 2106}
2107 2107
2108#endif 2108#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
index 60bdac4cb6a4..fdc87fe2c174 100644
--- a/arch/blackfin/mach-bf538/include/mach/irq.h
+++ b/arch/blackfin/mach-bf538/include/mach/irq.h
@@ -81,9 +81,9 @@
81#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */ 81#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */
82#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */ 82#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */
83#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */ 83#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */
84#define IRQ_TMR0 BFIN_IRQ(16) /* Timer 0 */ 84#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
85#define IRQ_TMR1 BFIN_IRQ(17) /* Timer 1 */ 85#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
86#define IRQ_TMR2 BFIN_IRQ(18) /* Timer 2 */ 86#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
87#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */ 87#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */
88#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */ 88#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */
89#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */ 89#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */
@@ -168,9 +168,9 @@
168#define IRQ_UART0_TX_POS 28 168#define IRQ_UART0_TX_POS 28
169 169
170/* IAR2 BIT FIELDS */ 170/* IAR2 BIT FIELDS */
171#define IRQ_TMR0_POS 0 171#define IRQ_TIMER0_POS 0
172#define IRQ_TMR1_POS 4 172#define IRQ_TIMER1_POS 4
173#define IRQ_TMR2_POS 8 173#define IRQ_TIMER2_POS 8
174#define IRQ_PORTF_INTA_POS 12 174#define IRQ_PORTF_INTA_POS 12
175#define IRQ_PORTF_INTB_POS 16 175#define IRQ_PORTF_INTB_POS 16
176#define IRQ_MEM0_DMA0_POS 20 176#define IRQ_MEM0_DMA0_POS 20