Blackfin arch: merge adeos blackfin part to arch/blackfin/

[Mike Frysinger <vapier.adi@gmail.com>:
 - handle bf531/bf532/bf534/bf536 variants in ipipe.h
 - cleanup IPIPE logic for bfin_set_irq_handler()
 - cleanup ipipe asm code a bit and add missing ENDPROC()
 - simplify IPIPE code in trap_c
 - unify some of the IPIPE code and fix style
 - simplify DO_IRQ_L1 handling with ipipe code
 - revert IRQ_SW_INT# addition from ipipe merge
 - remove duplicate get_{c,s}clk() prototypes
]

Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

2 files changed, 10 insertions, 10 deletions

diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
index 7e469b8d939c..241725bc6988 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -2063,7 +2063,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
         if (val == bfin_read_PLL_CTL())
                 return;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         /* Enable the PLL Wakeup bit in SIC IWR */
         iwr0 = bfin_read32(SIC_IWR0);
         iwr1 = bfin_read32(SIC_IWR1);
@@ -2077,7 +2077,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
 
         bfin_write32(SIC_IWR0, iwr0);
         bfin_write32(SIC_IWR1, iwr1);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
 /* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -2088,7 +2088,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
         if (val == bfin_read_VR_CTL())
                 return;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         /* Enable the PLL Wakeup bit in SIC IWR */
         iwr0 = bfin_read32(SIC_IWR0);
         iwr1 = bfin_read32(SIC_IWR1);
@@ -2102,7 +2102,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 
         bfin_write32(SIC_IWR0, iwr0);
         bfin_write32(SIC_IWR1, iwr1);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
 #endif
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
index 60bdac4cb6a4..fdc87fe2c174 100644
--- a/arch/blackfin/mach-bf538/include/mach/irq.h
+++ b/arch/blackfin/mach-bf538/include/mach/irq.h
@@ -81,9 +81,9 @@
 #define IRQ_SPI0                BFIN_IRQ(13)    /* DMA 5 Channel (SPI0) */
 #define IRQ_UART0_RX            BFIN_IRQ(14)    /* DMA 6 Channel (UART0 RX) */
 #define IRQ_UART0_TX            BFIN_IRQ(15)    /* DMA 7 Channel (UART0 TX) */
-#define IRQ_TMR0                BFIN_IRQ(16)    /* Timer 0 */
-#define IRQ_TMR1                BFIN_IRQ(17)    /* Timer 1 */
-#define IRQ_TMR2                BFIN_IRQ(18)    /* Timer 2 */
+#define IRQ_TIMER0              BFIN_IRQ(16)    /* Timer 0 */
+#define IRQ_TIMER1              BFIN_IRQ(17)    /* Timer 1 */
+#define IRQ_TIMER2              BFIN_IRQ(18)    /* Timer 2 */
 #define IRQ_PORTF_INTA          BFIN_IRQ(19)    /* Port F Interrupt A */
 #define IRQ_PORTF_INTB          BFIN_IRQ(20)    /* Port F Interrupt B */
 #define IRQ_MEM0_DMA0           BFIN_IRQ(21)    /* MDMA0 Stream 0 */
@@ -168,9 +168,9 @@
 #define IRQ_UART0_TX_POS        28
 
 /* IAR2 BIT FIELDS */
-#define IRQ_TMR0_POS            0
-#define IRQ_TMR1_POS            4
-#define IRQ_TMR2_POS            8
+#define IRQ_TIMER0_POS          0
+#define IRQ_TIMER1_POS          4
+#define IRQ_TIMER2_POS          8
 #define IRQ_PORTF_INTA_POS      12
 #define IRQ_PORTF_INTB_POS      16
 #define IRQ_MEM0_DMA0_POS       20