diff options
author | Mike Frysinger <vapier.adi@gmail.com> | 2008-11-18 04:48:22 -0500 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-11-18 04:48:22 -0500 |
commit | 53442e1cbdc1559cd39e0076adae6df64af36a3e (patch) | |
tree | 6513ffea1fcfdf488d5ec5e96f78fb2c2bc4b9f2 /arch/blackfin/mach-bf538/include | |
parent | b94919e2da2f7acde842972a57fcd6dcc4a528db (diff) |
Blackfin arch: delay PLL_CTL/VR_CTL wrappers
Delay PLL_CTL/VR_CTL wrappers as much as possible to avoid
the inter-dependency problems with cdef and common headers
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf538/include')
-rw-r--r-- | arch/blackfin/mach-bf538/include/mach/cdefBF538.h | 103 |
1 files changed, 53 insertions, 50 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h index f92e7c3932f3..1d768a65d139 100644 --- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h +++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h | |||
@@ -39,62 +39,12 @@ | |||
39 | /*include core specific register pointer definitions*/ | 39 | /*include core specific register pointer definitions*/ |
40 | #include <asm/cdef_LPBlackfin.h> | 40 | #include <asm/cdef_LPBlackfin.h> |
41 | 41 | ||
42 | #include <asm/system.h> | ||
43 | |||
44 | #define bfin_writePTR(addr, val) bfin_write32(addr, val) | 42 | #define bfin_writePTR(addr, val) bfin_write32(addr, val) |
45 | 43 | ||
46 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | 44 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
47 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
48 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
49 | { | ||
50 | unsigned long flags, iwr0, iwr1; | ||
51 | |||
52 | if (val == bfin_read_PLL_CTL()) | ||
53 | return; | ||
54 | |||
55 | local_irq_save(flags); | ||
56 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
57 | iwr0 = bfin_read32(SIC_IWR0); | ||
58 | iwr1 = bfin_read32(SIC_IWR1); | ||
59 | /* Only allow PPL Wakeup) */ | ||
60 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
61 | bfin_write32(SIC_IWR1, 0); | ||
62 | |||
63 | bfin_write16(PLL_CTL, val); | ||
64 | SSYNC(); | ||
65 | asm("IDLE;"); | ||
66 | |||
67 | bfin_write32(SIC_IWR0, iwr0); | ||
68 | bfin_write32(SIC_IWR1, iwr1); | ||
69 | local_irq_restore(flags); | ||
70 | } | ||
71 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | 45 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
72 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) | 46 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) |
73 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | 47 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) |
74 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
75 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
76 | { | ||
77 | unsigned long flags, iwr0, iwr1; | ||
78 | |||
79 | if (val == bfin_read_VR_CTL()) | ||
80 | return; | ||
81 | |||
82 | local_irq_save(flags); | ||
83 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
84 | iwr0 = bfin_read32(SIC_IWR0); | ||
85 | iwr1 = bfin_read32(SIC_IWR1); | ||
86 | /* Only allow PPL Wakeup) */ | ||
87 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
88 | bfin_write32(SIC_IWR1, 0); | ||
89 | |||
90 | bfin_write16(VR_CTL, val); | ||
91 | SSYNC(); | ||
92 | asm("IDLE;"); | ||
93 | |||
94 | bfin_write32(SIC_IWR0, iwr0); | ||
95 | bfin_write32(SIC_IWR1, iwr1); | ||
96 | local_irq_restore(flags); | ||
97 | } | ||
98 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | 48 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
99 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) | 49 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) |
100 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | 50 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) |
@@ -2102,4 +2052,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
2102 | #define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) | 2052 | #define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) |
2103 | #define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) | 2053 | #define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) |
2104 | 2054 | ||
2055 | /* These need to be last due to the cdef/linux inter-dependencies */ | ||
2056 | #include <asm/system.h> | ||
2057 | |||
2058 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
2059 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
2060 | { | ||
2061 | unsigned long flags, iwr0, iwr1; | ||
2062 | |||
2063 | if (val == bfin_read_PLL_CTL()) | ||
2064 | return; | ||
2065 | |||
2066 | local_irq_save(flags); | ||
2067 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
2068 | iwr0 = bfin_read32(SIC_IWR0); | ||
2069 | iwr1 = bfin_read32(SIC_IWR1); | ||
2070 | /* Only allow PPL Wakeup) */ | ||
2071 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
2072 | bfin_write32(SIC_IWR1, 0); | ||
2073 | |||
2074 | bfin_write16(PLL_CTL, val); | ||
2075 | SSYNC(); | ||
2076 | asm("IDLE;"); | ||
2077 | |||
2078 | bfin_write32(SIC_IWR0, iwr0); | ||
2079 | bfin_write32(SIC_IWR1, iwr1); | ||
2080 | local_irq_restore(flags); | ||
2081 | } | ||
2082 | |||
2083 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
2084 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
2085 | { | ||
2086 | unsigned long flags, iwr0, iwr1; | ||
2087 | |||
2088 | if (val == bfin_read_VR_CTL()) | ||
2089 | return; | ||
2090 | |||
2091 | local_irq_save(flags); | ||
2092 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
2093 | iwr0 = bfin_read32(SIC_IWR0); | ||
2094 | iwr1 = bfin_read32(SIC_IWR1); | ||
2095 | /* Only allow PPL Wakeup) */ | ||
2096 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
2097 | bfin_write32(SIC_IWR1, 0); | ||
2098 | |||
2099 | bfin_write16(VR_CTL, val); | ||
2100 | SSYNC(); | ||
2101 | asm("IDLE;"); | ||
2102 | |||
2103 | bfin_write32(SIC_IWR0, iwr0); | ||
2104 | bfin_write32(SIC_IWR1, iwr1); | ||
2105 | local_irq_restore(flags); | ||
2106 | } | ||
2107 | |||
2105 | #endif | 2108 | #endif |