diff options
| author | Sonic Zhang <sonic.zhang@analog.com> | 2011-11-24 04:40:07 -0500 |
|---|---|---|
| committer | Bob Liu <lliubbo@gmail.com> | 2012-05-21 02:54:21 -0400 |
| commit | c55c89e939f2a0a83d5c61462be554d5d2408178 (patch) | |
| tree | f3fe0781b6bf66acb3fb1a321ff446c240afeb73 /arch/blackfin/mach-bf537 | |
| parent | 2879bb30d788bb3841e2f1675ea7af5204eb171c (diff) | |
blackfin: twi: move twi bit mask macro to twi head file
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat (limited to 'arch/blackfin/mach-bf537')
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/defBF534.h | 69 |
1 files changed, 0 insertions, 69 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index 4a031dde173f..d0deb66e6e80 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h | |||
| @@ -1403,75 +1403,6 @@ | |||
| 1403 | #define ERR_DET 0x4000 /* Error Detected Indicator */ | 1403 | #define ERR_DET 0x4000 /* Error Detected Indicator */ |
| 1404 | #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ | 1404 | #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ |
| 1405 | 1405 | ||
| 1406 | /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ | ||
| 1407 | /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ | ||
| 1408 | #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ | ||
| 1409 | #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ | ||
| 1410 | |||
| 1411 | /* TWI_PRESCALE Masks */ | ||
| 1412 | #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ | ||
| 1413 | #define TWI_ENA 0x0080 /* TWI Enable */ | ||
| 1414 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ | ||
| 1415 | |||
| 1416 | /* TWI_SLAVE_CTL Masks */ | ||
| 1417 | #define SEN 0x0001 /* Slave Enable */ | ||
| 1418 | #define SADD_LEN 0x0002 /* Slave Address Length */ | ||
| 1419 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ | ||
| 1420 | #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ | ||
| 1421 | #define GEN 0x0010 /* General Call Address Matching Enabled */ | ||
| 1422 | |||
| 1423 | /* TWI_SLAVE_STAT Masks */ | ||
| 1424 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ | ||
| 1425 | #define GCALL 0x0002 /* General Call Indicator */ | ||
| 1426 | |||
| 1427 | /* TWI_MASTER_CTL Masks */ | ||
| 1428 | #define MEN 0x0001 /* Master Mode Enable */ | ||
| 1429 | #define MADD_LEN 0x0002 /* Master Address Length */ | ||
| 1430 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ | ||
| 1431 | #define FAST 0x0008 /* Use Fast Mode Timing Specs */ | ||
| 1432 | #define STOP 0x0010 /* Issue Stop Condition */ | ||
| 1433 | #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ | ||
| 1434 | #define DCNT 0x3FC0 /* Data Bytes To Transfer */ | ||
| 1435 | #define SDAOVR 0x4000 /* Serial Data Override */ | ||
| 1436 | #define SCLOVR 0x8000 /* Serial Clock Override */ | ||
| 1437 | |||
| 1438 | /* TWI_MASTER_STAT Masks */ | ||
| 1439 | #define MPROG 0x0001 /* Master Transfer In Progress */ | ||
| 1440 | #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ | ||
| 1441 | #define ANAK 0x0004 /* Address Not Acknowledged */ | ||
| 1442 | #define DNAK 0x0008 /* Data Not Acknowledged */ | ||
| 1443 | #define BUFRDERR 0x0010 /* Buffer Read Error */ | ||
| 1444 | #define BUFWRERR 0x0020 /* Buffer Write Error */ | ||
| 1445 | #define SDASEN 0x0040 /* Serial Data Sense */ | ||
| 1446 | #define SCLSEN 0x0080 /* Serial Clock Sense */ | ||
| 1447 | #define BUSBUSY 0x0100 /* Bus Busy Indicator */ | ||
| 1448 | |||
| 1449 | /* TWI_INT_SRC and TWI_INT_ENABLE Masks */ | ||
| 1450 | #define SINIT 0x0001 /* Slave Transfer Initiated */ | ||
| 1451 | #define SCOMP 0x0002 /* Slave Transfer Complete */ | ||
| 1452 | #define SERR 0x0004 /* Slave Transfer Error */ | ||
| 1453 | #define SOVF 0x0008 /* Slave Overflow */ | ||
| 1454 | #define MCOMP 0x0010 /* Master Transfer Complete */ | ||
| 1455 | #define MERR 0x0020 /* Master Transfer Error */ | ||
| 1456 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ | ||
| 1457 | #define RCVSERV 0x0080 /* Receive FIFO Service */ | ||
| 1458 | |||
| 1459 | /* TWI_FIFO_CTRL Masks */ | ||
| 1460 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ | ||
| 1461 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ | ||
| 1462 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ | ||
| 1463 | #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ | ||
| 1464 | |||
| 1465 | /* TWI_FIFO_STAT Masks */ | ||
| 1466 | #define XMTSTAT 0x0003 /* Transmit FIFO Status */ | ||
| 1467 | #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ | ||
| 1468 | #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ | ||
| 1469 | #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ | ||
| 1470 | |||
| 1471 | #define RCVSTAT 0x000C /* Receive FIFO Status */ | ||
| 1472 | #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ | ||
| 1473 | #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ | ||
| 1474 | #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ | ||
| 1475 | 1406 | ||
| 1476 | /* ******************* PIN CONTROL REGISTER MASKS ************************/ | 1407 | /* ******************* PIN CONTROL REGISTER MASKS ************************/ |
| 1477 | /* PORT_MUX Masks */ | 1408 | /* PORT_MUX Masks */ |