diff options
author | Mike Frysinger <vapier.adi@gmail.com> | 2008-08-06 05:23:50 -0400 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-08-06 05:23:50 -0400 |
commit | 17e89bcfa12f71b840361da07fe6c2f9c48d0605 (patch) | |
tree | c5ab94b397bcdfc5ffe0363f24ff83e012e8801a /arch/blackfin/mach-bf537 | |
parent | 67618fd8748a5d83f6bdcd578c8e748c3f47c4d4 (diff) |
Blackfin arch: unify the duplicated portions of __start and split mach-specific pieces into _mach_early_start where they will be easier to trim over time
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf537')
-rw-r--r-- | arch/blackfin/mach-bf537/head.S | 132 |
1 files changed, 3 insertions, 129 deletions
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index c062acb04836..6a02e472587a 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S | |||
@@ -30,93 +30,16 @@ | |||
30 | #include <linux/linkage.h> | 30 | #include <linux/linkage.h> |
31 | #include <linux/init.h> | 31 | #include <linux/init.h> |
32 | #include <asm/blackfin.h> | 32 | #include <asm/blackfin.h> |
33 | #include <asm/trace.h> | ||
34 | |||
35 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | 33 | #ifdef CONFIG_BFIN_KERNEL_CLOCK |
36 | #include <asm/mach-common/clocks.h> | 34 | #include <asm/mach-common/clocks.h> |
37 | #include <asm/mach/mem_init.h> | 35 | #include <asm/mach/mem_init.h> |
38 | #endif | 36 | #endif |
39 | 37 | ||
40 | .extern ___bss_stop | ||
41 | .extern ___bss_start | ||
42 | .extern _bf53x_relocate_l1_mem | 38 | .extern _bf53x_relocate_l1_mem |
43 | 39 | ||
44 | #define INITIAL_STACK 0xFFB01000 | ||
45 | |||
46 | __INIT | 40 | __INIT |
47 | 41 | ||
48 | ENTRY(__start) | 42 | ENTRY(_mach_early_start) |
49 | /* R0: argument of command line string, passed from uboot, save it */ | ||
50 | R7 = R0; | ||
51 | /* Enable Cycle Counter and Nesting Of Interrupts */ | ||
52 | #ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES | ||
53 | R0 = SYSCFG_SNEN; | ||
54 | #else | ||
55 | R0 = SYSCFG_SNEN | SYSCFG_CCEN; | ||
56 | #endif | ||
57 | SYSCFG = R0; | ||
58 | R0 = 0; | ||
59 | |||
60 | /* Clear Out All the data and pointer Registers */ | ||
61 | R1 = R0; | ||
62 | R2 = R0; | ||
63 | R3 = R0; | ||
64 | R4 = R0; | ||
65 | R5 = R0; | ||
66 | R6 = R0; | ||
67 | |||
68 | P0 = R0; | ||
69 | P1 = R0; | ||
70 | P2 = R0; | ||
71 | P3 = R0; | ||
72 | P4 = R0; | ||
73 | P5 = R0; | ||
74 | |||
75 | LC0 = r0; | ||
76 | LC1 = r0; | ||
77 | L0 = r0; | ||
78 | L1 = r0; | ||
79 | L2 = r0; | ||
80 | L3 = r0; | ||
81 | |||
82 | /* Clear Out All the DAG Registers */ | ||
83 | B0 = r0; | ||
84 | B1 = r0; | ||
85 | B2 = r0; | ||
86 | B3 = r0; | ||
87 | |||
88 | I0 = r0; | ||
89 | I1 = r0; | ||
90 | I2 = r0; | ||
91 | I3 = r0; | ||
92 | |||
93 | M0 = r0; | ||
94 | M1 = r0; | ||
95 | M2 = r0; | ||
96 | M3 = r0; | ||
97 | |||
98 | trace_buffer_init(p0,r0); | ||
99 | P0 = R1; | ||
100 | R0 = R1; | ||
101 | |||
102 | /* Turn off the icache */ | ||
103 | p0.l = LO(IMEM_CONTROL); | ||
104 | p0.h = HI(IMEM_CONTROL); | ||
105 | R1 = [p0]; | ||
106 | R0 = ~ENICPLB; | ||
107 | R0 = R0 & R1; | ||
108 | [p0] = R0; | ||
109 | SSYNC; | ||
110 | |||
111 | /* Turn off the dcache */ | ||
112 | p0.l = LO(DMEM_CONTROL); | ||
113 | p0.h = HI(DMEM_CONTROL); | ||
114 | R1 = [p0]; | ||
115 | R0 = ~ENDCPLB; | ||
116 | R0 = R0 & R1; | ||
117 | [p0] = R0; | ||
118 | SSYNC; | ||
119 | |||
120 | /* Initialise General-Purpose I/O Modules on BF537 */ | 43 | /* Initialise General-Purpose I/O Modules on BF537 */ |
121 | p0.h = hi(BFIN_PORT_MUX); | 44 | p0.h = hi(BFIN_PORT_MUX); |
122 | p0.l = lo(BFIN_PORT_MUX); | 45 | p0.l = lo(BFIN_PORT_MUX); |
@@ -166,57 +89,8 @@ ENTRY(__start) | |||
166 | w[p0] = r0.L; /* To enable UART clock */ | 89 | w[p0] = r0.L; /* To enable UART clock */ |
167 | ssync; | 90 | ssync; |
168 | 91 | ||
169 | /* Initialize stack pointer */ | 92 | rts; |
170 | sp.l = lo(INITIAL_STACK); | 93 | ENDPROC(_mach_early_start) |
171 | sp.h = hi(INITIAL_STACK); | ||
172 | fp = sp; | ||
173 | usp = sp; | ||
174 | |||
175 | #ifdef CONFIG_EARLY_PRINTK | ||
176 | SP += -12; | ||
177 | call _init_early_exception_vectors; | ||
178 | SP += 12; | ||
179 | #endif | ||
180 | |||
181 | /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ | ||
182 | call _bf53x_relocate_l1_mem; | ||
183 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
184 | call _start_dma_code; | ||
185 | #endif | ||
186 | |||
187 | /* This section keeps the processor in supervisor mode | ||
188 | * during kernel boot. Switches to user mode at end of boot. | ||
189 | * See page 3-9 of Hardware Reference manual for documentation. | ||
190 | */ | ||
191 | |||
192 | /* EVT15 = _real_start */ | ||
193 | |||
194 | p0.l = lo(EVT15); | ||
195 | p0.h = hi(EVT15); | ||
196 | p1.l = _real_start; | ||
197 | p1.h = _real_start; | ||
198 | [p0] = p1; | ||
199 | csync; | ||
200 | |||
201 | p0.l = lo(IMASK); | ||
202 | p0.h = hi(IMASK); | ||
203 | p1.l = IMASK_IVG15; | ||
204 | p1.h = 0x0; | ||
205 | [p0] = p1; | ||
206 | csync; | ||
207 | |||
208 | raise 15; | ||
209 | p0.l = .LWAIT_HERE; | ||
210 | p0.h = .LWAIT_HERE; | ||
211 | reti = p0; | ||
212 | #if ANOMALY_05000281 | ||
213 | nop; nop; nop; | ||
214 | #endif | ||
215 | rti; | ||
216 | |||
217 | .LWAIT_HERE: | ||
218 | jump .LWAIT_HERE; | ||
219 | ENDPROC(__start) | ||
220 | 94 | ||
221 | __FINIT | 95 | __FINIT |
222 | 96 | ||