diff options
author | Mike Frysinger <vapier.adi@gmail.com> | 2008-08-14 03:15:43 -0400 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-08-14 03:15:43 -0400 |
commit | 7e1e7aed0ca082b4e76567ee7ea13993b476e66a (patch) | |
tree | 8d294d0b5f838e52f708b6bba622acdf2231c755 /arch/blackfin/mach-bf537 | |
parent | 95a86b5e51139a199d081b6b108e761966d914ef (diff) |
Blackfin arch: do not muck with the UART during boot -- let the serial driver worry about it
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf537')
-rw-r--r-- | arch/blackfin/mach-bf537/head.S | 50 |
1 files changed, 0 insertions, 50 deletions
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index ba81b779511d..64e0287ab266 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S | |||
@@ -35,56 +35,6 @@ | |||
35 | #include <asm/mach/mem_init.h> | 35 | #include <asm/mach/mem_init.h> |
36 | #endif | 36 | #endif |
37 | 37 | ||
38 | .extern _bf53x_relocate_l1_mem | ||
39 | |||
40 | __INIT | ||
41 | |||
42 | ENTRY(_mach_early_start) | ||
43 | /* Initialise General-Purpose I/O Modules on BF537 */ | ||
44 | p0.h = hi(BFIN_PORT_MUX); | ||
45 | p0.l = lo(BFIN_PORT_MUX); | ||
46 | R0 = (PGDE_UART | PFTE_UART)(Z); | ||
47 | W[P0] = R0.L; /* Enable both UARTS */ | ||
48 | SSYNC; | ||
49 | |||
50 | /* Enable peripheral function of PORTF for UART0 and UART1 */ | ||
51 | p0.h = hi(PORTF_FER); | ||
52 | p0.l = lo(PORTF_FER); | ||
53 | R0 = 0x000F(Z); | ||
54 | W[P0] = R0.L; | ||
55 | SSYNC; | ||
56 | |||
57 | /* Initialise UART - when booting from u-boot, the UART is not disabled | ||
58 | * so if we dont initalize here, our serial console gets hosed */ | ||
59 | p0.h = hi(BFIN_UART_LCR); | ||
60 | p0.l = lo(BFIN_UART_LCR); | ||
61 | r0 = 0x0(Z); | ||
62 | w[p0] = r0.L; /* To enable DLL writes */ | ||
63 | ssync; | ||
64 | |||
65 | p0.h = hi(BFIN_UART_DLL); | ||
66 | p0.l = lo(BFIN_UART_DLL); | ||
67 | r0 = 0x0(Z); | ||
68 | w[p0] = r0.L; | ||
69 | ssync; | ||
70 | |||
71 | p0.h = hi(BFIN_UART_DLH); | ||
72 | p0.l = lo(BFIN_UART_DLH); | ||
73 | r0 = 0x00(Z); | ||
74 | w[p0] = r0.L; | ||
75 | ssync; | ||
76 | |||
77 | p0.h = hi(BFIN_UART_GCTL); | ||
78 | p0.l = lo(BFIN_UART_GCTL); | ||
79 | r0 = 0x0(Z); | ||
80 | w[p0] = r0.L; /* To enable UART clock */ | ||
81 | ssync; | ||
82 | |||
83 | rts; | ||
84 | ENDPROC(_mach_early_start) | ||
85 | |||
86 | __FINIT | ||
87 | |||
88 | .section .l1.text | 38 | .section .l1.text |
89 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | 39 | #ifdef CONFIG_BFIN_KERNEL_CLOCK |
90 | ENTRY(_start_dma_code) | 40 | ENTRY(_start_dma_code) |