diff options
author | Mike Frysinger <vapier@gentoo.org> | 2009-10-15 02:47:28 -0400 |
---|---|---|
committer | Mike Frysinger <vapier@gentoo.org> | 2009-12-15 00:14:53 -0500 |
commit | a8e8e491686bb34eb5aea37f58c9020f48629237 (patch) | |
tree | 2d079d743fba65f89f44181670ada148955ec867 /arch/blackfin/mach-bf537 | |
parent | 761ec44add46d4dfdcb3a0607bfecb4cfc0dc0f0 (diff) |
Blackfin: unify duplicated power masks
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf537')
-rw-r--r-- | arch/blackfin/mach-bf537/include/mach/blackfin.h | 6 | ||||
-rw-r--r-- | arch/blackfin/mach-bf537/include/mach/defBF534.h | 61 |
2 files changed, 0 insertions, 67 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h index eab006d260c5..a12d4b6a221d 100644 --- a/arch/blackfin/mach-bf537/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h | |||
@@ -40,10 +40,4 @@ | |||
40 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | 40 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ |
41 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | 41 | #define OFFSET_GCTL 0x24 /* Global Control Register */ |
42 | 42 | ||
43 | /* PLL_DIV Masks */ | ||
44 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | ||
45 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | ||
46 | #define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ | ||
47 | #define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ | ||
48 | |||
49 | #endif | 43 | #endif |
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index a6d20ca57683..868e1a139944 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h | |||
@@ -958,67 +958,6 @@ | |||
958 | ** modifier UNLESS the lower order bits are saved and ORed back in when | 958 | ** modifier UNLESS the lower order bits are saved and ORed back in when |
959 | ** the macro is used. | 959 | ** the macro is used. |
960 | *************************************************************************************/ | 960 | *************************************************************************************/ |
961 | /* | ||
962 | ** ********************* PLL AND RESET MASKS ****************************************/ | ||
963 | /* PLL_CTL Masks */ | ||
964 | #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ | ||
965 | #define PLL_OFF 0x0002 /* PLL Not Powered */ | ||
966 | #define STOPCK 0x0008 /* Core Clock Off */ | ||
967 | #define PDWN 0x0020 /* Enter Deep Sleep Mode */ | ||
968 | #define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ | ||
969 | #define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ | ||
970 | #define BYPASS 0x0100 /* Bypass the PLL */ | ||
971 | #define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ | ||
972 | /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ | ||
973 | #define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ | ||
974 | |||
975 | /* PLL_DIV Masks */ | ||
976 | #define SSEL 0x000F /* System Select */ | ||
977 | #define CSEL 0x0030 /* Core Select */ | ||
978 | #define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ | ||
979 | #define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ | ||
980 | #define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ | ||
981 | #define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ | ||
982 | /* PLL_DIV Macros */ | ||
983 | #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ | ||
984 | |||
985 | /* VR_CTL Masks */ | ||
986 | #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ | ||
987 | #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ | ||
988 | #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ | ||
989 | #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ | ||
990 | #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ | ||
991 | |||
992 | #define GAIN 0x000C /* Voltage Level Gain */ | ||
993 | #define GAIN_5 0x0000 /* GAIN = 5 */ | ||
994 | #define GAIN_10 0x0004 /* GAIN = 10 */ | ||
995 | #define GAIN_20 0x0008 /* GAIN = 20 */ | ||
996 | #define GAIN_50 0x000C /* GAIN = 50 */ | ||
997 | |||
998 | #define VLEV 0x00F0 /* Internal Voltage Level */ | ||
999 | #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ | ||
1000 | #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ | ||
1001 | #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ | ||
1002 | #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ | ||
1003 | #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ | ||
1004 | #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ | ||
1005 | #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ | ||
1006 | #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ | ||
1007 | #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ | ||
1008 | #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ | ||
1009 | |||
1010 | #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ | ||
1011 | #define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ | ||
1012 | #define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ | ||
1013 | #define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ | ||
1014 | #define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ | ||
1015 | #define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */ | ||
1016 | |||
1017 | /* PLL_STAT Masks */ | ||
1018 | #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ | ||
1019 | #define FULL_ON 0x0002 /* Processor In Full On Mode */ | ||
1020 | #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ | ||
1021 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ | ||
1022 | 961 | ||
1023 | /* CHIPID Masks */ | 962 | /* CHIPID Masks */ |
1024 | #define CHIPID_VERSION 0xF0000000 | 963 | #define CHIPID_VERSION 0xF0000000 |