diff options
author | Mike Frysinger <michael.frysinger@analog.com> | 2007-07-24 22:11:42 -0400 |
---|---|---|
committer | Bryan Wu <bryan.wu@analog.com> | 2007-07-24 22:11:42 -0400 |
commit | e208f83a7aa4ebf6c0a68e814903e8aa33f9439a (patch) | |
tree | a45d34fa199c8e5d75878d8a2f15e944eadce852 /arch/blackfin/mach-bf537 | |
parent | 36a1548f99e54520f049a703e1b91bae95e72481 (diff) |
Blackfin arch: use HI/LO macros rather than masking the bit ranges ourselves
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf537')
-rw-r--r-- | arch/blackfin/mach-bf537/head.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index d9b411adf6a7..b1d4b91b7aed 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S | |||
@@ -100,8 +100,8 @@ ENTRY(__start) | |||
100 | R0 = R1; | 100 | R0 = R1; |
101 | 101 | ||
102 | /* Turn off the icache */ | 102 | /* Turn off the icache */ |
103 | p0.l = (IMEM_CONTROL & 0xFFFF); | 103 | p0.l = LO(IMEM_CONTROL); |
104 | p0.h = (IMEM_CONTROL >> 16); | 104 | p0.h = HI(IMEM_CONTROL); |
105 | R1 = [p0]; | 105 | R1 = [p0]; |
106 | R0 = ~ENICPLB; | 106 | R0 = ~ENICPLB; |
107 | R0 = R0 & R1; | 107 | R0 = R0 & R1; |
@@ -118,8 +118,8 @@ ENTRY(__start) | |||
118 | #endif | 118 | #endif |
119 | 119 | ||
120 | /* Turn off the dcache */ | 120 | /* Turn off the dcache */ |
121 | p0.l = (DMEM_CONTROL & 0xFFFF); | 121 | p0.l = LO(DMEM_CONTROL); |
122 | p0.h = (DMEM_CONTROL >> 16); | 122 | p0.h = HI(DMEM_CONTROL); |
123 | R1 = [p0]; | 123 | R1 = [p0]; |
124 | R0 = ~ENDCPLB; | 124 | R0 = ~ENDCPLB; |
125 | R0 = R0 & R1; | 125 | R0 = R0 & R1; |
@@ -436,8 +436,8 @@ ENTRY(_start_dma_code) | |||
436 | w[p0] = r0.l; | 436 | w[p0] = r0.l; |
437 | ssync; | 437 | ssync; |
438 | 438 | ||
439 | p0.l = (EBIU_SDBCTL & 0xFFFF); | 439 | p0.l = LO(EBIU_SDBCTL); |
440 | p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */ | 440 | p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */ |
441 | r0 = mem_SDBCTL; | 441 | r0 = mem_SDBCTL; |
442 | w[p0] = r0.l; | 442 | w[p0] = r0.l; |
443 | ssync; | 443 | ssync; |