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authorMike Frysinger <michael.frysinger@analog.com>2007-07-24 23:19:14 -0400
committerBryan Wu <bryan.wu@analog.com>2007-07-24 23:19:14 -0400
commit1aafd9091226a02b481298315f959f777294684e (patch)
treeb09e0aaabb6aacd882499a69b28638cbd669dbba /arch/blackfin/mach-bf537
parent287050fe13bf34824f03b4351002b0e2db4ee5cb (diff)
Blackfin arch: revise anomaly handling by basing things on the compiler not the kconfig defines
revise anomaly handling by basing things on the compiler not the kconfig defines, so the header is stable and usable outside of the kernel. This also allows us to move some code from preprocessing to compiling (gcc culls dead code) which should help with code quality (readability, catch minor bugs, etc...). Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf537')
-rw-r--r--arch/blackfin/mach-bf537/head.S18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 429c8a1019da..d9b411adf6a7 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -107,13 +107,13 @@ ENTRY(__start)
107 R0 = R0 & R1; 107 R0 = R0 & R1;
108 108
109 /* Anomaly 05000125 */ 109 /* Anomaly 05000125 */
110#ifdef ANOMALY_05000125 110#if ANOMALY_05000125
111 CLI R2; 111 CLI R2;
112 SSYNC; 112 SSYNC;
113#endif 113#endif
114 [p0] = R0; 114 [p0] = R0;
115 SSYNC; 115 SSYNC;
116#ifdef ANOMALY_05000125 116#if ANOMALY_05000125
117 STI R2; 117 STI R2;
118#endif 118#endif
119 119
@@ -125,13 +125,13 @@ ENTRY(__start)
125 R0 = R0 & R1; 125 R0 = R0 & R1;
126 126
127 /* Anomaly 05000125 */ 127 /* Anomaly 05000125 */
128#ifdef ANOMALY_05000125 128#if ANOMALY_05000125
129 CLI R2; 129 CLI R2;
130 SSYNC; 130 SSYNC;
131#endif 131#endif
132 [p0] = R0; 132 [p0] = R0;
133 SSYNC; 133 SSYNC;
134#ifdef ANOMALY_05000125 134#if ANOMALY_05000125
135 STI R2; 135 STI R2;
136#endif 136#endif
137 137
@@ -141,12 +141,12 @@ ENTRY(__start)
141 */ 141 */
142 p0.h = hi(BFIN_PORT_MUX); 142 p0.h = hi(BFIN_PORT_MUX);
143 p0.l = lo(BFIN_PORT_MUX); 143 p0.l = lo(BFIN_PORT_MUX);
144#ifdef ANOMALY_05000212 144#if ANOMALY_05000212
145 R0.L = W[P0]; /* Read */ 145 R0.L = W[P0]; /* Read */
146 SSYNC; 146 SSYNC;
147#endif 147#endif
148 R0 = (PGDE_UART | PFTE_UART)(Z); 148 R0 = (PGDE_UART | PFTE_UART)(Z);
149#ifdef ANOMALY_05000212 149#if ANOMALY_05000212
150 W[P0] = R0.L; /* Write */ 150 W[P0] = R0.L; /* Write */
151 SSYNC; 151 SSYNC;
152#endif 152#endif
@@ -155,12 +155,12 @@ ENTRY(__start)
155 155
156 p0.h = hi(PORTF_FER); 156 p0.h = hi(PORTF_FER);
157 p0.l = lo(PORTF_FER); 157 p0.l = lo(PORTF_FER);
158#ifdef ANOMALY_05000212 158#if ANOMALY_05000212
159 R0.L = W[P0]; /* Read */ 159 R0.L = W[P0]; /* Read */
160 SSYNC; 160 SSYNC;
161#endif 161#endif
162 R0 = 0x000F(Z); 162 R0 = 0x000F(Z);
163#ifdef ANOMALY_05000212 163#if ANOMALY_05000212
164 W[P0] = R0.L; /* Write */ 164 W[P0] = R0.L; /* Write */
165 SSYNC; 165 SSYNC;
166#endif 166#endif
@@ -274,7 +274,7 @@ ENTRY(__start)
274 p0.l = .LWAIT_HERE; 274 p0.l = .LWAIT_HERE;
275 p0.h = .LWAIT_HERE; 275 p0.h = .LWAIT_HERE;
276 reti = p0; 276 reti = p0;
277#if defined(ANOMALY_05000281) 277#if ANOMALY_05000281
278 nop; nop; nop; 278 nop; nop; nop;
279#endif 279#endif
280 rti; 280 rti;